pci-rcar-gen3.c 10 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Renesas RCar Gen3 PCIEC driver
  4. *
  5. * Copyright (C) 2018-2019 Marek Vasut <marek.vasut@gmail.com>
  6. *
  7. * Based on Linux PCIe driver for Renesas R-Car SoCs
  8. * Copyright (C) 2014 Renesas Electronics Europe Ltd
  9. *
  10. * Based on:
  11. * arch/sh/drivers/pci/pcie-sh7786.c
  12. * arch/sh/drivers/pci/ops-sh7786.c
  13. * Copyright (C) 2009 - 2011 Paul Mundt
  14. *
  15. * Author: Phil Edworthy <phil.edworthy@renesas.com>
  16. */
  17. #include <common.h>
  18. #include <asm/io.h>
  19. #include <clk.h>
  20. #include <dm.h>
  21. #include <errno.h>
  22. #include <pci.h>
  23. #include <wait_bit.h>
  24. #define PCIECAR 0x000010
  25. #define PCIECCTLR 0x000018
  26. #define CONFIG_SEND_ENABLE BIT(31)
  27. #define TYPE0 (0 << 8)
  28. #define TYPE1 BIT(8)
  29. #define PCIECDR 0x000020
  30. #define PCIEMSR 0x000028
  31. #define PCIEINTXR 0x000400
  32. #define PCIEPHYSR 0x0007f0
  33. #define PHYRDY BIT(0)
  34. #define PCIEMSITXR 0x000840
  35. /* Transfer control */
  36. #define PCIETCTLR 0x02000
  37. #define CFINIT 1
  38. #define PCIETSTR 0x02004
  39. #define DATA_LINK_ACTIVE 1
  40. #define PCIEERRFR 0x02020
  41. #define UNSUPPORTED_REQUEST BIT(4)
  42. #define PCIEMSIFR 0x02044
  43. #define PCIEMSIALR 0x02048
  44. #define MSIFE 1
  45. #define PCIEMSIAUR 0x0204c
  46. #define PCIEMSIIER 0x02050
  47. /* root port address */
  48. #define PCIEPRAR(x) (0x02080 + ((x) * 0x4))
  49. /* local address reg & mask */
  50. #define PCIELAR(x) (0x02200 + ((x) * 0x20))
  51. #define PCIELAMR(x) (0x02208 + ((x) * 0x20))
  52. #define LAM_PREFETCH BIT(3)
  53. #define LAM_64BIT BIT(2)
  54. #define LAR_ENABLE BIT(1)
  55. /* PCIe address reg & mask */
  56. #define PCIEPALR(x) (0x03400 + ((x) * 0x20))
  57. #define PCIEPAUR(x) (0x03404 + ((x) * 0x20))
  58. #define PCIEPAMR(x) (0x03408 + ((x) * 0x20))
  59. #define PCIEPTCTLR(x) (0x0340c + ((x) * 0x20))
  60. #define PAR_ENABLE BIT(31)
  61. #define IO_SPACE BIT(8)
  62. /* Configuration */
  63. #define PCICONF(x) (0x010000 + ((x) * 0x4))
  64. #define PMCAP(x) (0x010040 + ((x) * 0x4))
  65. #define EXPCAP(x) (0x010070 + ((x) * 0x4))
  66. #define VCCAP(x) (0x010100 + ((x) * 0x4))
  67. /* link layer */
  68. #define IDSETR1 0x011004
  69. #define TLCTLR 0x011048
  70. #define MACSR 0x011054
  71. #define SPCHGFIN BIT(4)
  72. #define SPCHGFAIL BIT(6)
  73. #define SPCHGSUC BIT(7)
  74. #define LINK_SPEED (0xf << 16)
  75. #define LINK_SPEED_2_5GTS (1 << 16)
  76. #define LINK_SPEED_5_0GTS (2 << 16)
  77. #define MACCTLR 0x011058
  78. #define SPEED_CHANGE BIT(24)
  79. #define SCRAMBLE_DISABLE BIT(27)
  80. #define MACS2R 0x011078
  81. #define MACCGSPSETR 0x011084
  82. #define SPCNGRSN BIT(31)
  83. /* R-Car H1 PHY */
  84. #define H1_PCIEPHYADRR 0x04000c
  85. #define WRITE_CMD BIT(16)
  86. #define PHY_ACK BIT(24)
  87. #define RATE_POS 12
  88. #define LANE_POS 8
  89. #define ADR_POS 0
  90. #define H1_PCIEPHYDOUTR 0x040014
  91. /* R-Car Gen2 PHY */
  92. #define GEN2_PCIEPHYADDR 0x780
  93. #define GEN2_PCIEPHYDATA 0x784
  94. #define GEN2_PCIEPHYCTRL 0x78c
  95. #define INT_PCI_MSI_NR 32
  96. #define RCONF(x) (PCICONF(0) + (x))
  97. #define RPMCAP(x) (PMCAP(0) + (x))
  98. #define REXPCAP(x) (EXPCAP(0) + (x))
  99. #define RVCCAP(x) (VCCAP(0) + (x))
  100. #define PCIE_CONF_BUS(b) (((b) & 0xff) << 24)
  101. #define PCIE_CONF_DEV(d) (((d) & 0x1f) << 19)
  102. #define PCIE_CONF_FUNC(f) (((f) & 0x7) << 16)
  103. #define RCAR_PCI_MAX_RESOURCES 4
  104. #define MAX_NR_INBOUND_MAPS 6
  105. #define PCI_EXP_FLAGS 2 /* Capabilities register */
  106. #define PCI_EXP_FLAGS_TYPE 0x00f0 /* Device/Port type */
  107. #define PCI_EXP_TYPE_ROOT_PORT 0x4 /* Root Port */
  108. #define PCI_EXP_LNKCAP 12 /* Link Capabilities */
  109. #define PCI_EXP_LNKCAP_DLLLARC 0x00100000 /* Data Link Layer Link Active Reporting Capable */
  110. #define PCI_EXP_SLTCAP 20 /* Slot Capabilities */
  111. #define PCI_EXP_SLTCAP_PSN 0xfff80000 /* Physical Slot Number */
  112. enum {
  113. RCAR_PCI_ACCESS_READ,
  114. RCAR_PCI_ACCESS_WRITE,
  115. };
  116. struct rcar_gen3_pcie_priv {
  117. fdt_addr_t regs;
  118. };
  119. static void rcar_rmw32(struct udevice *dev, int where, u32 mask, u32 data)
  120. {
  121. struct rcar_gen3_pcie_priv *priv = dev_get_platdata(dev);
  122. int shift = 8 * (where & 3);
  123. clrsetbits_le32(priv->regs + (where & ~3),
  124. mask << shift, data << shift);
  125. }
  126. static u32 rcar_read_conf(const struct udevice *dev, int where)
  127. {
  128. struct rcar_gen3_pcie_priv *priv = dev_get_platdata(dev);
  129. int shift = 8 * (where & 3);
  130. return readl(priv->regs + (where & ~3)) >> shift;
  131. }
  132. static int rcar_pcie_config_access(const struct udevice *udev,
  133. unsigned char access_type,
  134. pci_dev_t bdf, int where, ulong *data)
  135. {
  136. struct rcar_gen3_pcie_priv *priv = dev_get_platdata(udev);
  137. u32 reg = where & ~3;
  138. /* Clear errors */
  139. clrbits_le32(priv->regs + PCIEERRFR, 0);
  140. /* Set the PIO address */
  141. writel((bdf << 8) | reg, priv->regs + PCIECAR);
  142. /* Enable the configuration access */
  143. if (!PCI_BUS(bdf))
  144. writel(CONFIG_SEND_ENABLE | TYPE0, priv->regs + PCIECCTLR);
  145. else
  146. writel(CONFIG_SEND_ENABLE | TYPE1, priv->regs + PCIECCTLR);
  147. /* Check for errors */
  148. if (readl(priv->regs + PCIEERRFR) & UNSUPPORTED_REQUEST)
  149. return -ENODEV;
  150. /* Check for master and target aborts */
  151. if (rcar_read_conf(udev, RCONF(PCI_STATUS)) &
  152. (PCI_STATUS_REC_MASTER_ABORT | PCI_STATUS_REC_TARGET_ABORT))
  153. return -ENODEV;
  154. if (access_type == RCAR_PCI_ACCESS_READ)
  155. *data = readl(priv->regs + PCIECDR);
  156. else
  157. writel(*data, priv->regs + PCIECDR);
  158. /* Disable the configuration access */
  159. writel(0, priv->regs + PCIECCTLR);
  160. return 0;
  161. }
  162. static int rcar_gen3_pcie_addr_valid(pci_dev_t d, uint where)
  163. {
  164. u32 slot;
  165. if (PCI_FUNC(d))
  166. return -EINVAL;
  167. slot = PCI_DEV(d);
  168. if (slot != 1)
  169. return -EINVAL;
  170. return 0;
  171. }
  172. static int rcar_gen3_pcie_read_config(const struct udevice *dev, pci_dev_t bdf,
  173. uint where, ulong *val,
  174. enum pci_size_t size)
  175. {
  176. ulong reg;
  177. int ret;
  178. ret = rcar_gen3_pcie_addr_valid(bdf, where);
  179. if (ret) {
  180. *val = pci_get_ff(size);
  181. return 0;
  182. }
  183. ret = rcar_pcie_config_access(dev, RCAR_PCI_ACCESS_READ,
  184. bdf, where, &reg);
  185. if (ret != 0)
  186. reg = 0xffffffffUL;
  187. *val = pci_conv_32_to_size(reg, where, size);
  188. return ret;
  189. }
  190. static int rcar_gen3_pcie_write_config(struct udevice *dev, pci_dev_t bdf,
  191. uint where, ulong val,
  192. enum pci_size_t size)
  193. {
  194. ulong data;
  195. int ret;
  196. ret = rcar_gen3_pcie_addr_valid(bdf, where);
  197. if (ret)
  198. return ret;
  199. data = pci_conv_32_to_size(val, where, size);
  200. ret = rcar_pcie_config_access(dev, RCAR_PCI_ACCESS_WRITE,
  201. bdf, where, &data);
  202. return ret;
  203. }
  204. static int rcar_gen3_pcie_wait_for_phyrdy(struct udevice *dev)
  205. {
  206. struct rcar_gen3_pcie_priv *priv = dev_get_platdata(dev);
  207. return wait_for_bit_le32((void *)priv->regs + PCIEPHYSR, PHYRDY,
  208. true, 50, false);
  209. }
  210. static int rcar_gen3_pcie_wait_for_dl(struct udevice *dev)
  211. {
  212. struct rcar_gen3_pcie_priv *priv = dev_get_platdata(dev);
  213. return wait_for_bit_le32((void *)priv->regs + PCIETSTR,
  214. DATA_LINK_ACTIVE, true, 50, false);
  215. }
  216. static int rcar_gen3_pcie_hw_init(struct udevice *dev)
  217. {
  218. struct rcar_gen3_pcie_priv *priv = dev_get_platdata(dev);
  219. int ret;
  220. /* Begin initialization */
  221. writel(0, priv->regs + PCIETCTLR);
  222. /* Set mode */
  223. writel(1, priv->regs + PCIEMSR);
  224. ret = rcar_gen3_pcie_wait_for_phyrdy(dev);
  225. if (ret)
  226. return ret;
  227. /*
  228. * Initial header for port config space is type 1, set the device
  229. * class to match. Hardware takes care of propagating the IDSETR
  230. * settings, so there is no need to bother with a quirk.
  231. */
  232. writel(PCI_CLASS_BRIDGE_PCI << 16, priv->regs + IDSETR1);
  233. /*
  234. * Setup Secondary Bus Number & Subordinate Bus Number, even though
  235. * they aren't used, to avoid bridge being detected as broken.
  236. */
  237. rcar_rmw32(dev, RCONF(PCI_SECONDARY_BUS), 0xff, 1);
  238. rcar_rmw32(dev, RCONF(PCI_SUBORDINATE_BUS), 0xff, 1);
  239. /* Initialize default capabilities. */
  240. rcar_rmw32(dev, REXPCAP(0), 0xff, PCI_CAP_ID_EXP);
  241. rcar_rmw32(dev, REXPCAP(PCI_EXP_FLAGS),
  242. PCI_EXP_FLAGS_TYPE, PCI_EXP_TYPE_ROOT_PORT << 4);
  243. rcar_rmw32(dev, RCONF(PCI_HEADER_TYPE), 0x7f,
  244. PCI_HEADER_TYPE_BRIDGE);
  245. /* Enable data link layer active state reporting */
  246. rcar_rmw32(dev, REXPCAP(PCI_EXP_LNKCAP),
  247. PCI_EXP_LNKCAP_DLLLARC, PCI_EXP_LNKCAP_DLLLARC);
  248. /* Write out the physical slot number = 0 */
  249. rcar_rmw32(dev, REXPCAP(PCI_EXP_SLTCAP),
  250. PCI_EXP_SLTCAP_PSN, 0);
  251. /* Set the completion timer timeout to the maximum 50ms. */
  252. rcar_rmw32(dev, TLCTLR + 1, 0x3f, 50);
  253. /* Terminate list of capabilities (Next Capability Offset=0) */
  254. rcar_rmw32(dev, RVCCAP(0), 0xfff00000, 0);
  255. /* Finish initialization - establish a PCI Express link */
  256. writel(CFINIT, priv->regs + PCIETCTLR);
  257. return rcar_gen3_pcie_wait_for_dl(dev);
  258. }
  259. static int rcar_gen3_pcie_probe(struct udevice *dev)
  260. {
  261. struct rcar_gen3_pcie_priv *priv = dev_get_platdata(dev);
  262. struct pci_controller *hose = dev_get_uclass_priv(dev);
  263. struct clk pci_clk;
  264. u32 mask;
  265. int i, cnt, ret;
  266. ret = clk_get_by_index(dev, 0, &pci_clk);
  267. if (ret)
  268. return ret;
  269. ret = clk_enable(&pci_clk);
  270. if (ret)
  271. return ret;
  272. for (i = 0; i < hose->region_count; i++) {
  273. if (hose->regions[i].flags != PCI_REGION_SYS_MEMORY)
  274. continue;
  275. if (hose->regions[i].phys_start == 0)
  276. continue;
  277. mask = (hose->regions[i].size - 1) & ~0xf;
  278. mask |= LAR_ENABLE;
  279. writel(hose->regions[i].phys_start, priv->regs + PCIEPRAR(0));
  280. writel(hose->regions[i].phys_start, priv->regs + PCIELAR(0));
  281. writel(mask, priv->regs + PCIELAMR(0));
  282. break;
  283. }
  284. writel(0, priv->regs + PCIEPRAR(4));
  285. writel(0, priv->regs + PCIELAR(4));
  286. writel(0, priv->regs + PCIELAMR(4));
  287. ret = rcar_gen3_pcie_hw_init(dev);
  288. if (ret)
  289. return ret;
  290. for (i = 0, cnt = 0; i < hose->region_count; i++) {
  291. if (hose->regions[i].flags == PCI_REGION_SYS_MEMORY)
  292. continue;
  293. writel(0, priv->regs + PCIEPTCTLR(cnt));
  294. writel((hose->regions[i].size - 1) & ~0x7f,
  295. priv->regs + PCIEPAMR(cnt));
  296. writel(upper_32_bits(hose->regions[i].phys_start),
  297. priv->regs + PCIEPAUR(cnt));
  298. writel(lower_32_bits(hose->regions[i].phys_start),
  299. priv->regs + PCIEPALR(cnt));
  300. mask = PAR_ENABLE;
  301. if (hose->regions[i].flags == PCI_REGION_IO)
  302. mask |= IO_SPACE;
  303. writel(mask, priv->regs + PCIEPTCTLR(cnt));
  304. cnt++;
  305. }
  306. return 0;
  307. }
  308. static int rcar_gen3_pcie_ofdata_to_platdata(struct udevice *dev)
  309. {
  310. struct rcar_gen3_pcie_priv *priv = dev_get_platdata(dev);
  311. priv->regs = devfdt_get_addr_index(dev, 0);
  312. if (!priv->regs)
  313. return -EINVAL;
  314. return 0;
  315. }
  316. static const struct dm_pci_ops rcar_gen3_pcie_ops = {
  317. .read_config = rcar_gen3_pcie_read_config,
  318. .write_config = rcar_gen3_pcie_write_config,
  319. };
  320. static const struct udevice_id rcar_gen3_pcie_ids[] = {
  321. { .compatible = "renesas,pcie-rcar-gen3" },
  322. { }
  323. };
  324. U_BOOT_DRIVER(rcar_gen3_pcie) = {
  325. .name = "rcar_gen3_pcie",
  326. .id = UCLASS_PCI,
  327. .of_match = rcar_gen3_pcie_ids,
  328. .ops = &rcar_gen3_pcie_ops,
  329. .probe = rcar_gen3_pcie_probe,
  330. .ofdata_to_platdata = rcar_gen3_pcie_ofdata_to_platdata,
  331. .platdata_auto_alloc_size = sizeof(struct rcar_gen3_pcie_priv),
  332. };