pci-rcar-gen2.c 7.7 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Renesas RCar Gen2 PCIEC driver
  4. *
  5. * Copyright (C) 2018 Marek Vasut <marek.vasut@gmail.com>
  6. */
  7. #include <common.h>
  8. #include <asm/io.h>
  9. #include <clk.h>
  10. #include <dm.h>
  11. #include <errno.h>
  12. #include <pci.h>
  13. /* AHB-PCI Bridge PCI communication registers */
  14. #define RCAR_AHBPCI_PCICOM_OFFSET 0x800
  15. #define RCAR_PCIAHB_WIN1_CTR_REG (RCAR_AHBPCI_PCICOM_OFFSET + 0x00)
  16. #define RCAR_PCIAHB_WIN2_CTR_REG (RCAR_AHBPCI_PCICOM_OFFSET + 0x04)
  17. #define RCAR_PCIAHB_PREFETCH0 0x0
  18. #define RCAR_PCIAHB_PREFETCH4 0x1
  19. #define RCAR_PCIAHB_PREFETCH8 0x2
  20. #define RCAR_PCIAHB_PREFETCH16 0x3
  21. #define RCAR_AHBPCI_WIN1_CTR_REG (RCAR_AHBPCI_PCICOM_OFFSET + 0x10)
  22. #define RCAR_AHBPCI_WIN2_CTR_REG (RCAR_AHBPCI_PCICOM_OFFSET + 0x14)
  23. #define RCAR_AHBPCI_WIN_CTR_MEM (3 << 1)
  24. #define RCAR_AHBPCI_WIN_CTR_CFG (5 << 1)
  25. #define RCAR_AHBPCI_WIN1_HOST BIT(30)
  26. #define RCAR_AHBPCI_WIN1_DEVICE BIT(31)
  27. #define RCAR_PCI_INT_ENABLE_REG (RCAR_AHBPCI_PCICOM_OFFSET + 0x20)
  28. #define RCAR_PCI_INT_STATUS_REG (RCAR_AHBPCI_PCICOM_OFFSET + 0x24)
  29. #define RCAR_PCI_INT_SIGTABORT BIT(0)
  30. #define RCAR_PCI_INT_SIGRETABORT BIT(1)
  31. #define RCAR_PCI_INT_REMABORT BIT(2)
  32. #define RCAR_PCI_INT_PERR BIT(3)
  33. #define RCAR_PCI_INT_SIGSERR BIT(4)
  34. #define RCAR_PCI_INT_RESERR BIT(5)
  35. #define RCAR_PCI_INT_WIN1ERR BIT(12)
  36. #define RCAR_PCI_INT_WIN2ERR BIT(13)
  37. #define RCAR_PCI_INT_A BIT(16)
  38. #define RCAR_PCI_INT_B BIT(17)
  39. #define RCAR_PCI_INT_PME BIT(19)
  40. #define RCAR_PCI_INT_ALLERRORS (RCAR_PCI_INT_SIGTABORT | \
  41. RCAR_PCI_INT_SIGRETABORT | \
  42. RCAR_PCI_INT_SIGRETABORT | \
  43. RCAR_PCI_INT_REMABORT | \
  44. RCAR_PCI_INT_PERR | \
  45. RCAR_PCI_INT_SIGSERR | \
  46. RCAR_PCI_INT_RESERR | \
  47. RCAR_PCI_INT_WIN1ERR | \
  48. RCAR_PCI_INT_WIN2ERR)
  49. #define RCAR_AHB_BUS_CTR_REG (RCAR_AHBPCI_PCICOM_OFFSET + 0x30)
  50. #define RCAR_AHB_BUS_MMODE_HTRANS BIT(0)
  51. #define RCAR_AHB_BUS_MMODE_BYTE_BURST BIT(1)
  52. #define RCAR_AHB_BUS_MMODE_WR_INCR BIT(2)
  53. #define RCAR_AHB_BUS_MMODE_HBUS_REQ BIT(7)
  54. #define RCAR_AHB_BUS_SMODE_READYCTR BIT(17)
  55. #define RCAR_AHB_BUS_MODE (RCAR_AHB_BUS_MMODE_HTRANS | \
  56. RCAR_AHB_BUS_MMODE_BYTE_BURST | \
  57. RCAR_AHB_BUS_MMODE_WR_INCR | \
  58. RCAR_AHB_BUS_MMODE_HBUS_REQ | \
  59. RCAR_AHB_BUS_SMODE_READYCTR)
  60. #define RCAR_USBCTR_REG (RCAR_AHBPCI_PCICOM_OFFSET + 0x34)
  61. #define RCAR_USBCTR_USBH_RST BIT(0)
  62. #define RCAR_USBCTR_PCICLK_MASK BIT(1)
  63. #define RCAR_USBCTR_PLL_RST BIT(2)
  64. #define RCAR_USBCTR_DIRPD BIT(8)
  65. #define RCAR_USBCTR_PCIAHB_WIN2_EN BIT(9)
  66. #define RCAR_USBCTR_PCIAHB_WIN1_256M (0 << 10)
  67. #define RCAR_USBCTR_PCIAHB_WIN1_512M (1 << 10)
  68. #define RCAR_USBCTR_PCIAHB_WIN1_1G (2 << 10)
  69. #define RCAR_USBCTR_PCIAHB_WIN1_2G (3 << 10)
  70. #define RCAR_USBCTR_PCIAHB_WIN1_MASK (3 << 10)
  71. #define RCAR_PCI_ARBITER_CTR_REG (RCAR_AHBPCI_PCICOM_OFFSET + 0x40)
  72. #define RCAR_PCI_ARBITER_PCIREQ0 BIT(0)
  73. #define RCAR_PCI_ARBITER_PCIREQ1 BIT(1)
  74. #define RCAR_PCI_ARBITER_PCIBP_MODE BIT(12)
  75. #define RCAR_PCI_UNIT_REV_REG (RCAR_AHBPCI_PCICOM_OFFSET + 0x48)
  76. struct rcar_gen2_pci_priv {
  77. fdt_addr_t cfg_base;
  78. fdt_addr_t mem_base;
  79. };
  80. static int rcar_gen2_pci_addr_valid(pci_dev_t d, uint offset)
  81. {
  82. u32 slot;
  83. if (PCI_FUNC(d))
  84. return -EINVAL;
  85. /* Only one EHCI/OHCI device built-in */
  86. slot = PCI_DEV(d);
  87. if (slot != 1 && slot != 2)
  88. return -EINVAL;
  89. /* bridge logic only has registers to 0x40 */
  90. if (slot == 0x0 && offset >= 0x40)
  91. return -EINVAL;
  92. return 0;
  93. }
  94. static u32 get_bus_address(const struct udevice *dev, pci_dev_t bdf, u32 offset)
  95. {
  96. struct rcar_gen2_pci_priv *priv = dev_get_priv(dev);
  97. return priv->cfg_base + (PCI_DEV(bdf) >> 1) * 0x100 + (offset & ~3);
  98. }
  99. static u32 setup_bus_address(struct udevice *dev, pci_dev_t bdf, u32 offset)
  100. {
  101. struct rcar_gen2_pci_priv *priv = dev_get_priv(dev);
  102. u32 reg;
  103. reg = PCI_DEV(bdf) ? RCAR_AHBPCI_WIN1_DEVICE : RCAR_AHBPCI_WIN1_HOST;
  104. reg |= RCAR_AHBPCI_WIN_CTR_CFG;
  105. writel(reg, priv->cfg_base + RCAR_AHBPCI_WIN1_CTR_REG);
  106. return get_bus_address(dev, bdf, offset);
  107. }
  108. static int rcar_gen2_pci_read_config(const struct udevice *dev, pci_dev_t bdf,
  109. uint offset, ulong *value,
  110. enum pci_size_t size)
  111. {
  112. u32 addr, reg;
  113. int ret;
  114. ret = rcar_gen2_pci_addr_valid(bdf, offset);
  115. if (ret) {
  116. *value = pci_get_ff(size);
  117. return 0;
  118. }
  119. addr = get_bus_address(dev, bdf, offset);
  120. reg = readl(addr);
  121. *value = pci_conv_32_to_size(reg, offset, size);
  122. return 0;
  123. }
  124. static int rcar_gen2_pci_write_config(struct udevice *dev, pci_dev_t bdf,
  125. uint offset, ulong value,
  126. enum pci_size_t size)
  127. {
  128. u32 addr, reg, old;
  129. int ret;
  130. ret = rcar_gen2_pci_addr_valid(bdf, offset);
  131. if (ret)
  132. return ret;
  133. addr = get_bus_address(dev, bdf, offset);
  134. old = readl(addr);
  135. reg = pci_conv_size_to_32(old, value, offset, size);
  136. writel(reg, addr);
  137. return 0;
  138. }
  139. static int rcar_gen2_pci_probe(struct udevice *dev)
  140. {
  141. struct rcar_gen2_pci_priv *priv = dev_get_priv(dev);
  142. struct clk pci_clk;
  143. u32 devad;
  144. int ret;
  145. ret = clk_get_by_index(dev, 0, &pci_clk);
  146. if (ret)
  147. return ret;
  148. ret = clk_enable(&pci_clk);
  149. if (ret)
  150. return ret;
  151. /* Clock & Reset & Direct Power Down */
  152. clrsetbits_le32(priv->cfg_base + RCAR_USBCTR_REG,
  153. RCAR_USBCTR_DIRPD | RCAR_USBCTR_PCICLK_MASK |
  154. RCAR_USBCTR_USBH_RST,
  155. RCAR_USBCTR_PCIAHB_WIN1_1G);
  156. clrbits_le32(priv->cfg_base + RCAR_USBCTR_REG, RCAR_USBCTR_PLL_RST);
  157. /* AHB-PCI Bridge Communication Registers */
  158. writel(RCAR_AHB_BUS_MODE, priv->cfg_base + RCAR_AHB_BUS_CTR_REG);
  159. writel((CONFIG_SYS_SDRAM_BASE & 0xf0000000) | RCAR_PCIAHB_PREFETCH16,
  160. priv->cfg_base + RCAR_PCIAHB_WIN1_CTR_REG);
  161. writel(0xf0000000 | RCAR_PCIAHB_PREFETCH16,
  162. priv->cfg_base + RCAR_PCIAHB_WIN2_CTR_REG);
  163. writel(priv->mem_base | RCAR_AHBPCI_WIN_CTR_MEM,
  164. priv->cfg_base + RCAR_AHBPCI_WIN2_CTR_REG);
  165. setbits_le32(priv->cfg_base + RCAR_PCI_ARBITER_CTR_REG,
  166. RCAR_PCI_ARBITER_PCIREQ0 | RCAR_PCI_ARBITER_PCIREQ1 |
  167. RCAR_PCI_ARBITER_PCIBP_MODE);
  168. /* PCI Configuration Registers for AHBPCI */
  169. devad = setup_bus_address(dev, PCI_BDF(0, 0, 0), 0);
  170. writel(priv->cfg_base + 0x800, devad + PCI_BASE_ADDRESS_0);
  171. writel(CONFIG_SYS_SDRAM_BASE & 0xf0000000, devad + PCI_BASE_ADDRESS_1);
  172. writel(0xf0000000, devad + PCI_BASE_ADDRESS_2);
  173. writel(PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER |
  174. PCI_COMMAND_PARITY | PCI_COMMAND_SERR,
  175. devad + PCI_COMMAND);
  176. /* PCI Configuration Registers for OHCI */
  177. devad = setup_bus_address(dev, PCI_BDF(0, 1, 0), 0);
  178. writel(priv->mem_base + 0x0, devad + PCI_BASE_ADDRESS_0);
  179. writel(PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER |
  180. PCI_COMMAND_PARITY | PCI_COMMAND_SERR,
  181. devad + PCI_COMMAND);
  182. /* PCI Configuration Registers for EHCI */
  183. devad = setup_bus_address(dev, PCI_BDF(0, 2, 0), 0);
  184. writel(priv->mem_base + 0x1000, devad + PCI_BASE_ADDRESS_0);
  185. writel(PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER |
  186. PCI_COMMAND_PARITY | PCI_COMMAND_SERR,
  187. devad + PCI_COMMAND);
  188. /* Enable PCI interrupt */
  189. setbits_le32(priv->cfg_base + RCAR_PCI_INT_ENABLE_REG,
  190. RCAR_PCI_INT_A | RCAR_PCI_INT_B | RCAR_PCI_INT_PME);
  191. return 0;
  192. }
  193. static int rcar_gen2_pci_ofdata_to_platdata(struct udevice *dev)
  194. {
  195. struct rcar_gen2_pci_priv *priv = dev_get_priv(dev);
  196. priv->cfg_base = devfdt_get_addr_index(dev, 0);
  197. priv->mem_base = devfdt_get_addr_index(dev, 1);
  198. if (!priv->cfg_base || !priv->mem_base)
  199. return -EINVAL;
  200. return 0;
  201. }
  202. static const struct dm_pci_ops rcar_gen2_pci_ops = {
  203. .read_config = rcar_gen2_pci_read_config,
  204. .write_config = rcar_gen2_pci_write_config,
  205. };
  206. static const struct udevice_id rcar_gen2_pci_ids[] = {
  207. { .compatible = "renesas,pci-rcar-gen2" },
  208. { }
  209. };
  210. U_BOOT_DRIVER(rcar_gen2_pci) = {
  211. .name = "rcar_gen2_pci",
  212. .id = UCLASS_PCI,
  213. .of_match = rcar_gen2_pci_ids,
  214. .ops = &rcar_gen2_pci_ops,
  215. .probe = rcar_gen2_pci_probe,
  216. .ofdata_to_platdata = rcar_gen2_pci_ofdata_to_platdata,
  217. .priv_auto_alloc_size = sizeof(struct rcar_gen2_pci_priv),
  218. };