pci-aardvark.c 19 KB

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  1. /*
  2. * ***************************************************************************
  3. * Copyright (C) 2015 Marvell International Ltd.
  4. * ***************************************************************************
  5. * This program is free software: you can redistribute it and/or modify it
  6. * under the terms of the GNU General Public License as published by the Free
  7. * Software Foundation, either version 2 of the License, or any later version.
  8. *
  9. * This program is distributed in the hope that it will be useful,
  10. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  12. * GNU General Public License for more details.
  13. *
  14. * You should have received a copy of the GNU General Public License
  15. * along with this program. If not, see <http://www.gnu.org/licenses/>.
  16. * ***************************************************************************
  17. */
  18. /* pcie_advk.c
  19. *
  20. * Ported from Linux driver - driver/pci/host/pci-aardvark.c
  21. *
  22. * Author: Victor Gu <xigu@marvell.com>
  23. * Hezi Shahmoon <hezi.shahmoon@marvell.com>
  24. *
  25. */
  26. #include <common.h>
  27. #include <dm.h>
  28. #include <pci.h>
  29. #include <asm/io.h>
  30. #include <asm-generic/gpio.h>
  31. #include <dm/device_compat.h>
  32. #include <linux/ioport.h>
  33. /* PCIe core registers */
  34. #define PCIE_CORE_CMD_STATUS_REG 0x4
  35. #define PCIE_CORE_CMD_IO_ACCESS_EN BIT(0)
  36. #define PCIE_CORE_CMD_MEM_ACCESS_EN BIT(1)
  37. #define PCIE_CORE_CMD_MEM_IO_REQ_EN BIT(2)
  38. #define PCIE_CORE_DEV_CTRL_STATS_REG 0xc8
  39. #define PCIE_CORE_DEV_CTRL_STATS_RELAX_ORDER_DISABLE (0 << 4)
  40. #define PCIE_CORE_DEV_CTRL_STATS_SNOOP_DISABLE (0 << 11)
  41. #define PCIE_CORE_LINK_CTRL_STAT_REG 0xd0
  42. #define PCIE_CORE_LINK_TRAINING BIT(5)
  43. #define PCIE_CORE_ERR_CAPCTL_REG 0x118
  44. #define PCIE_CORE_ERR_CAPCTL_ECRC_CHK_TX BIT(5)
  45. #define PCIE_CORE_ERR_CAPCTL_ECRC_CHK_TX_EN BIT(6)
  46. #define PCIE_CORE_ERR_CAPCTL_ECRC_CHECK BIT(7)
  47. #define PCIE_CORE_ERR_CAPCTL_ECRC_CHECK_RCV BIT(8)
  48. /* PIO registers base address and register offsets */
  49. #define PIO_BASE_ADDR 0x4000
  50. #define PIO_CTRL (PIO_BASE_ADDR + 0x0)
  51. #define PIO_CTRL_TYPE_MASK GENMASK(3, 0)
  52. #define PIO_CTRL_ADDR_WIN_DISABLE BIT(24)
  53. #define PIO_STAT (PIO_BASE_ADDR + 0x4)
  54. #define PIO_COMPLETION_STATUS_SHIFT 7
  55. #define PIO_COMPLETION_STATUS_MASK GENMASK(9, 7)
  56. #define PIO_COMPLETION_STATUS_OK 0
  57. #define PIO_COMPLETION_STATUS_UR 1
  58. #define PIO_COMPLETION_STATUS_CRS 2
  59. #define PIO_COMPLETION_STATUS_CA 4
  60. #define PIO_NON_POSTED_REQ BIT(10)
  61. #define PIO_ERR_STATUS BIT(11)
  62. #define PIO_ADDR_LS (PIO_BASE_ADDR + 0x8)
  63. #define PIO_ADDR_MS (PIO_BASE_ADDR + 0xc)
  64. #define PIO_WR_DATA (PIO_BASE_ADDR + 0x10)
  65. #define PIO_WR_DATA_STRB (PIO_BASE_ADDR + 0x14)
  66. #define PIO_RD_DATA (PIO_BASE_ADDR + 0x18)
  67. #define PIO_START (PIO_BASE_ADDR + 0x1c)
  68. #define PIO_ISR (PIO_BASE_ADDR + 0x20)
  69. /* Aardvark Control registers */
  70. #define CONTROL_BASE_ADDR 0x4800
  71. #define PCIE_CORE_CTRL0_REG (CONTROL_BASE_ADDR + 0x0)
  72. #define PCIE_GEN_SEL_MSK 0x3
  73. #define PCIE_GEN_SEL_SHIFT 0x0
  74. #define SPEED_GEN_1 0
  75. #define SPEED_GEN_2 1
  76. #define SPEED_GEN_3 2
  77. #define IS_RC_MSK 1
  78. #define IS_RC_SHIFT 2
  79. #define LANE_CNT_MSK 0x18
  80. #define LANE_CNT_SHIFT 0x3
  81. #define LANE_COUNT_1 (0 << LANE_CNT_SHIFT)
  82. #define LANE_COUNT_2 (1 << LANE_CNT_SHIFT)
  83. #define LANE_COUNT_4 (2 << LANE_CNT_SHIFT)
  84. #define LANE_COUNT_8 (3 << LANE_CNT_SHIFT)
  85. #define LINK_TRAINING_EN BIT(6)
  86. #define PCIE_CORE_CTRL2_REG (CONTROL_BASE_ADDR + 0x8)
  87. #define PCIE_CORE_CTRL2_RESERVED 0x7
  88. #define PCIE_CORE_CTRL2_TD_ENABLE BIT(4)
  89. #define PCIE_CORE_CTRL2_STRICT_ORDER_ENABLE BIT(5)
  90. #define PCIE_CORE_CTRL2_ADDRWIN_MAP_ENABLE BIT(6)
  91. /* LMI registers base address and register offsets */
  92. #define LMI_BASE_ADDR 0x6000
  93. #define CFG_REG (LMI_BASE_ADDR + 0x0)
  94. #define LTSSM_SHIFT 24
  95. #define LTSSM_MASK 0x3f
  96. #define LTSSM_L0 0x10
  97. /* PCIe core controller registers */
  98. #define CTRL_CORE_BASE_ADDR 0x18000
  99. #define CTRL_CONFIG_REG (CTRL_CORE_BASE_ADDR + 0x0)
  100. #define CTRL_MODE_SHIFT 0x0
  101. #define CTRL_MODE_MASK 0x1
  102. #define PCIE_CORE_MODE_DIRECT 0x0
  103. #define PCIE_CORE_MODE_COMMAND 0x1
  104. /* Transaction types */
  105. #define PCIE_CONFIG_RD_TYPE0 0x8
  106. #define PCIE_CONFIG_RD_TYPE1 0x9
  107. #define PCIE_CONFIG_WR_TYPE0 0xa
  108. #define PCIE_CONFIG_WR_TYPE1 0xb
  109. /* PCI_BDF shifts 8bit, so we need extra 4bit shift */
  110. #define PCIE_BDF(dev) (dev << 4)
  111. #define PCIE_CONF_BUS(bus) (((bus) & 0xff) << 20)
  112. #define PCIE_CONF_DEV(dev) (((dev) & 0x1f) << 15)
  113. #define PCIE_CONF_FUNC(fun) (((fun) & 0x7) << 12)
  114. #define PCIE_CONF_REG(reg) ((reg) & 0xffc)
  115. #define PCIE_CONF_ADDR(bus, devfn, where) \
  116. (PCIE_CONF_BUS(bus) | PCIE_CONF_DEV(PCI_SLOT(devfn)) | \
  117. PCIE_CONF_FUNC(PCI_FUNC(devfn)) | PCIE_CONF_REG(where))
  118. /* PCIe Retries & Timeout definitions */
  119. #define MAX_RETRIES 10
  120. #define PIO_WAIT_TIMEOUT 100
  121. #define LINK_WAIT_TIMEOUT 100000
  122. #define CFG_RD_UR_VAL 0xFFFFFFFF
  123. #define CFG_RD_CRS_VAL 0xFFFF0001
  124. /**
  125. * struct pcie_advk - Advk PCIe controller state
  126. *
  127. * @reg_base: The base address of the register space.
  128. * @first_busno: This driver supports multiple PCIe controllers.
  129. * first_busno stores the bus number of the PCIe root-port
  130. * number which may vary depending on the PCIe setup
  131. * (PEX switches etc).
  132. * @device: The pointer to PCI uclass device.
  133. */
  134. struct pcie_advk {
  135. void *base;
  136. int first_busno;
  137. struct udevice *dev;
  138. };
  139. static inline void advk_writel(struct pcie_advk *pcie, uint val, uint reg)
  140. {
  141. writel(val, pcie->base + reg);
  142. }
  143. static inline uint advk_readl(struct pcie_advk *pcie, uint reg)
  144. {
  145. return readl(pcie->base + reg);
  146. }
  147. /**
  148. * pcie_advk_addr_valid() - Check for valid bus address
  149. *
  150. * @bdf: The PCI device to access
  151. * @first_busno: Bus number of the PCIe controller root complex
  152. *
  153. * Return: 1 on valid, 0 on invalid
  154. */
  155. static int pcie_advk_addr_valid(pci_dev_t bdf, int first_busno)
  156. {
  157. /*
  158. * In PCIE-E only a single device (0) can exist
  159. * on the local bus. Beyound the local bus, there might be
  160. * a Switch and everything is possible.
  161. */
  162. if ((PCI_BUS(bdf) == first_busno) && (PCI_DEV(bdf) > 0))
  163. return 0;
  164. return 1;
  165. }
  166. /**
  167. * pcie_advk_wait_pio() - Wait for PIO access to be accomplished
  168. *
  169. * @pcie: The PCI device to access
  170. *
  171. * Wait up to 1 micro second for PIO access to be accomplished.
  172. *
  173. * Return 1 (true) if PIO access is accomplished.
  174. * Return 0 (false) if PIO access is timed out.
  175. */
  176. static int pcie_advk_wait_pio(struct pcie_advk *pcie)
  177. {
  178. uint start, isr;
  179. uint count;
  180. for (count = 0; count < MAX_RETRIES; count++) {
  181. start = advk_readl(pcie, PIO_START);
  182. isr = advk_readl(pcie, PIO_ISR);
  183. if (!start && isr)
  184. return 1;
  185. /*
  186. * Do not check the PIO state too frequently,
  187. * 100us delay is appropriate.
  188. */
  189. udelay(PIO_WAIT_TIMEOUT);
  190. }
  191. dev_err(pcie->dev, "config read/write timed out\n");
  192. return 0;
  193. }
  194. /**
  195. * pcie_advk_check_pio_status() - Validate PIO status and get the read result
  196. *
  197. * @pcie: Pointer to the PCI bus
  198. * @read: Read from or write to configuration space - true(read) false(write)
  199. * @read_val: Pointer to the read result, only valid when read is true
  200. *
  201. */
  202. static int pcie_advk_check_pio_status(struct pcie_advk *pcie,
  203. bool read,
  204. uint *read_val)
  205. {
  206. uint reg;
  207. unsigned int status;
  208. char *strcomp_status, *str_posted;
  209. reg = advk_readl(pcie, PIO_STAT);
  210. status = (reg & PIO_COMPLETION_STATUS_MASK) >>
  211. PIO_COMPLETION_STATUS_SHIFT;
  212. switch (status) {
  213. case PIO_COMPLETION_STATUS_OK:
  214. if (reg & PIO_ERR_STATUS) {
  215. strcomp_status = "COMP_ERR";
  216. break;
  217. }
  218. /* Get the read result */
  219. if (read)
  220. *read_val = advk_readl(pcie, PIO_RD_DATA);
  221. /* No error */
  222. strcomp_status = NULL;
  223. break;
  224. case PIO_COMPLETION_STATUS_UR:
  225. if (read) {
  226. /* For reading, UR is not an error status. */
  227. *read_val = CFG_RD_UR_VAL;
  228. strcomp_status = NULL;
  229. } else {
  230. strcomp_status = "UR";
  231. }
  232. break;
  233. case PIO_COMPLETION_STATUS_CRS:
  234. if (read) {
  235. /* For reading, CRS is not an error status. */
  236. *read_val = CFG_RD_CRS_VAL;
  237. strcomp_status = NULL;
  238. } else {
  239. strcomp_status = "CRS";
  240. }
  241. break;
  242. case PIO_COMPLETION_STATUS_CA:
  243. strcomp_status = "CA";
  244. break;
  245. default:
  246. strcomp_status = "Unknown";
  247. break;
  248. }
  249. if (!strcomp_status)
  250. return 0;
  251. if (reg & PIO_NON_POSTED_REQ)
  252. str_posted = "Non-posted";
  253. else
  254. str_posted = "Posted";
  255. dev_err(pcie->dev, "%s PIO Response Status: %s, %#x @ %#x\n",
  256. str_posted, strcomp_status, reg,
  257. advk_readl(pcie, PIO_ADDR_LS));
  258. return -EFAULT;
  259. }
  260. /**
  261. * pcie_advk_read_config() - Read from configuration space
  262. *
  263. * @bus: Pointer to the PCI bus
  264. * @bdf: Identifies the PCIe device to access
  265. * @offset: The offset into the device's configuration space
  266. * @valuep: A pointer at which to store the read value
  267. * @size: Indicates the size of access to perform
  268. *
  269. * Read a value of size @size from offset @offset within the configuration
  270. * space of the device identified by the bus, device & function numbers in @bdf
  271. * on the PCI bus @bus.
  272. *
  273. * Return: 0 on success
  274. */
  275. static int pcie_advk_read_config(const struct udevice *bus, pci_dev_t bdf,
  276. uint offset, ulong *valuep,
  277. enum pci_size_t size)
  278. {
  279. struct pcie_advk *pcie = dev_get_priv(bus);
  280. uint reg;
  281. int ret;
  282. dev_dbg(pcie->dev, "PCIE CFG read: (b,d,f)=(%2d,%2d,%2d) ",
  283. PCI_BUS(bdf), PCI_DEV(bdf), PCI_FUNC(bdf));
  284. if (!pcie_advk_addr_valid(bdf, pcie->first_busno)) {
  285. dev_dbg(pcie->dev, "- out of range\n");
  286. *valuep = pci_get_ff(size);
  287. return 0;
  288. }
  289. /* Start PIO */
  290. advk_writel(pcie, 0, PIO_START);
  291. advk_writel(pcie, 1, PIO_ISR);
  292. /* Program the control register */
  293. reg = advk_readl(pcie, PIO_CTRL);
  294. reg &= ~PIO_CTRL_TYPE_MASK;
  295. if (PCI_BUS(bdf) == pcie->first_busno)
  296. reg |= PCIE_CONFIG_RD_TYPE0;
  297. else
  298. reg |= PCIE_CONFIG_RD_TYPE1;
  299. advk_writel(pcie, reg, PIO_CTRL);
  300. /* Program the address registers */
  301. reg = PCIE_BDF(bdf) | PCIE_CONF_REG(offset);
  302. advk_writel(pcie, reg, PIO_ADDR_LS);
  303. advk_writel(pcie, 0, PIO_ADDR_MS);
  304. /* Start the transfer */
  305. advk_writel(pcie, 1, PIO_START);
  306. if (!pcie_advk_wait_pio(pcie))
  307. return -EINVAL;
  308. /* Check PIO status and get the read result */
  309. ret = pcie_advk_check_pio_status(pcie, true, &reg);
  310. if (ret)
  311. return ret;
  312. dev_dbg(pcie->dev, "(addr,size,val)=(0x%04x, %d, 0x%08x)\n",
  313. offset, size, reg);
  314. *valuep = pci_conv_32_to_size(reg, offset, size);
  315. return 0;
  316. }
  317. /**
  318. * pcie_calc_datastrobe() - Calculate data strobe
  319. *
  320. * @offset: The offset into the device's configuration space
  321. * @size: Indicates the size of access to perform
  322. *
  323. * Calculate data strobe according to offset and size
  324. *
  325. */
  326. static uint pcie_calc_datastrobe(uint offset, enum pci_size_t size)
  327. {
  328. uint bytes, data_strobe;
  329. switch (size) {
  330. case PCI_SIZE_8:
  331. bytes = 1;
  332. break;
  333. case PCI_SIZE_16:
  334. bytes = 2;
  335. break;
  336. default:
  337. bytes = 4;
  338. }
  339. data_strobe = GENMASK(bytes - 1, 0) << (offset & 0x3);
  340. return data_strobe;
  341. }
  342. /**
  343. * pcie_advk_write_config() - Write to configuration space
  344. *
  345. * @bus: Pointer to the PCI bus
  346. * @bdf: Identifies the PCIe device to access
  347. * @offset: The offset into the device's configuration space
  348. * @value: The value to write
  349. * @size: Indicates the size of access to perform
  350. *
  351. * Write the value @value of size @size from offset @offset within the
  352. * configuration space of the device identified by the bus, device & function
  353. * numbers in @bdf on the PCI bus @bus.
  354. *
  355. * Return: 0 on success
  356. */
  357. static int pcie_advk_write_config(struct udevice *bus, pci_dev_t bdf,
  358. uint offset, ulong value,
  359. enum pci_size_t size)
  360. {
  361. struct pcie_advk *pcie = dev_get_priv(bus);
  362. uint reg;
  363. dev_dbg(pcie->dev, "PCIE CFG write: (b,d,f)=(%2d,%2d,%2d) ",
  364. PCI_BUS(bdf), PCI_DEV(bdf), PCI_FUNC(bdf));
  365. dev_dbg(pcie->dev, "(addr,size,val)=(0x%04x, %d, 0x%08lx)\n",
  366. offset, size, value);
  367. if (!pcie_advk_addr_valid(bdf, pcie->first_busno)) {
  368. dev_dbg(pcie->dev, "- out of range\n");
  369. return 0;
  370. }
  371. /* Start PIO */
  372. advk_writel(pcie, 0, PIO_START);
  373. advk_writel(pcie, 1, PIO_ISR);
  374. /* Program the control register */
  375. reg = advk_readl(pcie, PIO_CTRL);
  376. reg &= ~PIO_CTRL_TYPE_MASK;
  377. if (PCI_BUS(bdf) == pcie->first_busno)
  378. reg |= PCIE_CONFIG_WR_TYPE0;
  379. else
  380. reg |= PCIE_CONFIG_WR_TYPE1;
  381. advk_writel(pcie, reg, PIO_CTRL);
  382. /* Program the address registers */
  383. reg = PCIE_BDF(bdf) | PCIE_CONF_REG(offset);
  384. advk_writel(pcie, reg, PIO_ADDR_LS);
  385. advk_writel(pcie, 0, PIO_ADDR_MS);
  386. dev_dbg(pcie->dev, "\tPIO req. - addr = 0x%08x\n", reg);
  387. /* Program the data register */
  388. reg = pci_conv_size_to_32(0, value, offset, size);
  389. advk_writel(pcie, reg, PIO_WR_DATA);
  390. dev_dbg(pcie->dev, "\tPIO req. - val = 0x%08x\n", reg);
  391. /* Program the data strobe */
  392. reg = pcie_calc_datastrobe(offset, size);
  393. advk_writel(pcie, reg, PIO_WR_DATA_STRB);
  394. dev_dbg(pcie->dev, "\tPIO req. - strb = 0x%02x\n", reg);
  395. /* Start the transfer */
  396. advk_writel(pcie, 1, PIO_START);
  397. if (!pcie_advk_wait_pio(pcie)) {
  398. dev_dbg(pcie->dev, "- wait pio timeout\n");
  399. return -EINVAL;
  400. }
  401. /* Check PIO status */
  402. pcie_advk_check_pio_status(pcie, false, &reg);
  403. return 0;
  404. }
  405. /**
  406. * pcie_advk_link_up() - Check if PCIe link is up or not
  407. *
  408. * @pcie: The PCI device to access
  409. *
  410. * Return 1 (true) on link up.
  411. * Return 0 (false) on link down.
  412. */
  413. static int pcie_advk_link_up(struct pcie_advk *pcie)
  414. {
  415. u32 val, ltssm_state;
  416. val = advk_readl(pcie, CFG_REG);
  417. ltssm_state = (val >> LTSSM_SHIFT) & LTSSM_MASK;
  418. return ltssm_state >= LTSSM_L0;
  419. }
  420. /**
  421. * pcie_advk_wait_for_link() - Wait for link training to be accomplished
  422. *
  423. * @pcie: The PCI device to access
  424. *
  425. * Wait up to 1 second for link training to be accomplished.
  426. *
  427. * Return 1 (true) if link training ends up with link up success.
  428. * Return 0 (false) if link training ends up with link up failure.
  429. */
  430. static int pcie_advk_wait_for_link(struct pcie_advk *pcie)
  431. {
  432. int retries;
  433. /* check if the link is up or not */
  434. for (retries = 0; retries < MAX_RETRIES; retries++) {
  435. if (pcie_advk_link_up(pcie)) {
  436. printf("PCIE-%d: Link up\n", pcie->first_busno);
  437. return 0;
  438. }
  439. udelay(LINK_WAIT_TIMEOUT);
  440. }
  441. printf("PCIE-%d: Link down\n", pcie->first_busno);
  442. return -ETIMEDOUT;
  443. }
  444. /**
  445. * pcie_advk_setup_hw() - PCIe initailzation
  446. *
  447. * @pcie: The PCI device to access
  448. *
  449. * Return: 0 on success
  450. */
  451. static int pcie_advk_setup_hw(struct pcie_advk *pcie)
  452. {
  453. u32 reg;
  454. /* Set to Direct mode */
  455. reg = advk_readl(pcie, CTRL_CONFIG_REG);
  456. reg &= ~(CTRL_MODE_MASK << CTRL_MODE_SHIFT);
  457. reg |= ((PCIE_CORE_MODE_DIRECT & CTRL_MODE_MASK) << CTRL_MODE_SHIFT);
  458. advk_writel(pcie, reg, CTRL_CONFIG_REG);
  459. /* Set PCI global control register to RC mode */
  460. reg = advk_readl(pcie, PCIE_CORE_CTRL0_REG);
  461. reg |= (IS_RC_MSK << IS_RC_SHIFT);
  462. advk_writel(pcie, reg, PCIE_CORE_CTRL0_REG);
  463. /* Set Advanced Error Capabilities and Control PF0 register */
  464. reg = PCIE_CORE_ERR_CAPCTL_ECRC_CHK_TX |
  465. PCIE_CORE_ERR_CAPCTL_ECRC_CHK_TX_EN |
  466. PCIE_CORE_ERR_CAPCTL_ECRC_CHECK |
  467. PCIE_CORE_ERR_CAPCTL_ECRC_CHECK_RCV;
  468. advk_writel(pcie, reg, PCIE_CORE_ERR_CAPCTL_REG);
  469. /* Set PCIe Device Control and Status 1 PF0 register */
  470. reg = PCIE_CORE_DEV_CTRL_STATS_RELAX_ORDER_DISABLE |
  471. PCIE_CORE_DEV_CTRL_STATS_SNOOP_DISABLE;
  472. advk_writel(pcie, reg, PCIE_CORE_DEV_CTRL_STATS_REG);
  473. /* Program PCIe Control 2 to disable strict ordering */
  474. reg = PCIE_CORE_CTRL2_RESERVED |
  475. PCIE_CORE_CTRL2_TD_ENABLE;
  476. advk_writel(pcie, reg, PCIE_CORE_CTRL2_REG);
  477. /* Set GEN2 */
  478. reg = advk_readl(pcie, PCIE_CORE_CTRL0_REG);
  479. reg &= ~PCIE_GEN_SEL_MSK;
  480. reg |= SPEED_GEN_2;
  481. advk_writel(pcie, reg, PCIE_CORE_CTRL0_REG);
  482. /* Set lane X1 */
  483. reg = advk_readl(pcie, PCIE_CORE_CTRL0_REG);
  484. reg &= ~LANE_CNT_MSK;
  485. reg |= LANE_COUNT_1;
  486. advk_writel(pcie, reg, PCIE_CORE_CTRL0_REG);
  487. /* Enable link training */
  488. reg = advk_readl(pcie, PCIE_CORE_CTRL0_REG);
  489. reg |= LINK_TRAINING_EN;
  490. advk_writel(pcie, reg, PCIE_CORE_CTRL0_REG);
  491. /*
  492. * Enable AXI address window location generation:
  493. * When it is enabled, the default outbound window
  494. * configurations (Default User Field: 0xD0074CFC)
  495. * are used to transparent address translation for
  496. * the outbound transactions. Thus, PCIe address
  497. * windows are not required.
  498. */
  499. reg = advk_readl(pcie, PCIE_CORE_CTRL2_REG);
  500. reg |= PCIE_CORE_CTRL2_ADDRWIN_MAP_ENABLE;
  501. advk_writel(pcie, reg, PCIE_CORE_CTRL2_REG);
  502. /*
  503. * Bypass the address window mapping for PIO:
  504. * Since PIO access already contains all required
  505. * info over AXI interface by PIO registers, the
  506. * address window is not required.
  507. */
  508. reg = advk_readl(pcie, PIO_CTRL);
  509. reg |= PIO_CTRL_ADDR_WIN_DISABLE;
  510. advk_writel(pcie, reg, PIO_CTRL);
  511. /* Start link training */
  512. reg = advk_readl(pcie, PCIE_CORE_LINK_CTRL_STAT_REG);
  513. reg |= PCIE_CORE_LINK_TRAINING;
  514. advk_writel(pcie, reg, PCIE_CORE_LINK_CTRL_STAT_REG);
  515. /* Wait for PCIe link up */
  516. if (pcie_advk_wait_for_link(pcie))
  517. return -ENXIO;
  518. reg = advk_readl(pcie, PCIE_CORE_CMD_STATUS_REG);
  519. reg |= PCIE_CORE_CMD_MEM_ACCESS_EN |
  520. PCIE_CORE_CMD_IO_ACCESS_EN |
  521. PCIE_CORE_CMD_MEM_IO_REQ_EN;
  522. advk_writel(pcie, reg, PCIE_CORE_CMD_STATUS_REG);
  523. return 0;
  524. }
  525. /**
  526. * pcie_advk_probe() - Probe the PCIe bus for active link
  527. *
  528. * @dev: A pointer to the device being operated on
  529. *
  530. * Probe for an active link on the PCIe bus and configure the controller
  531. * to enable this port.
  532. *
  533. * Return: 0 on success, else -ENODEV
  534. */
  535. static int pcie_advk_probe(struct udevice *dev)
  536. {
  537. struct pcie_advk *pcie = dev_get_priv(dev);
  538. #if CONFIG_IS_ENABLED(DM_GPIO)
  539. struct gpio_desc reset_gpio;
  540. gpio_request_by_name(dev, "reset-gpio", 0, &reset_gpio,
  541. GPIOD_IS_OUT);
  542. /*
  543. * Issue reset to add-in card through the dedicated GPIO.
  544. * Some boards are connecting the card reset pin to common system
  545. * reset wire and others are using separate GPIO port.
  546. * In the last case we have to release a reset of the addon card
  547. * using this GPIO.
  548. *
  549. * FIX-ME:
  550. * The PCIe RESET signal is not supposed to be released along
  551. * with the SOC RESET signal. It should be lowered as early as
  552. * possible before PCIe PHY initialization. Moreover, the PCIe
  553. * clock should be gated as well.
  554. */
  555. if (dm_gpio_is_valid(&reset_gpio)) {
  556. dev_dbg(pcie->dev, "Toggle PCIE Reset GPIO ...\n");
  557. dm_gpio_set_value(&reset_gpio, 0);
  558. mdelay(200);
  559. dm_gpio_set_value(&reset_gpio, 1);
  560. }
  561. #else
  562. dev_dbg(pcie->dev, "PCIE Reset on GPIO support is missing\n");
  563. #endif /* DM_GPIO */
  564. pcie->first_busno = dev->seq;
  565. pcie->dev = pci_get_controller(dev);
  566. return pcie_advk_setup_hw(pcie);
  567. }
  568. /**
  569. * pcie_advk_ofdata_to_platdata() - Translate from DT to device state
  570. *
  571. * @dev: A pointer to the device being operated on
  572. *
  573. * Translate relevant data from the device tree pertaining to device @dev into
  574. * state that the driver will later make use of. This state is stored in the
  575. * device's private data structure.
  576. *
  577. * Return: 0 on success, else -EINVAL
  578. */
  579. static int pcie_advk_ofdata_to_platdata(struct udevice *dev)
  580. {
  581. struct pcie_advk *pcie = dev_get_priv(dev);
  582. /* Get the register base address */
  583. pcie->base = (void *)dev_read_addr_index(dev, 0);
  584. if ((fdt_addr_t)pcie->base == FDT_ADDR_T_NONE)
  585. return -EINVAL;
  586. return 0;
  587. }
  588. static const struct dm_pci_ops pcie_advk_ops = {
  589. .read_config = pcie_advk_read_config,
  590. .write_config = pcie_advk_write_config,
  591. };
  592. static const struct udevice_id pcie_advk_ids[] = {
  593. { .compatible = "marvell,armada-37xx-pcie" },
  594. { }
  595. };
  596. U_BOOT_DRIVER(pcie_advk) = {
  597. .name = "pcie_advk",
  598. .id = UCLASS_PCI,
  599. .of_match = pcie_advk_ids,
  600. .ops = &pcie_advk_ops,
  601. .ofdata_to_platdata = pcie_advk_ofdata_to_platdata,
  602. .probe = pcie_advk_probe,
  603. .priv_auto_alloc_size = sizeof(struct pcie_advk),
  604. };