omap24xx_i2c.c 30 KB

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  1. /*
  2. * Basic I2C functions
  3. *
  4. * Copyright (c) 2004 Texas Instruments
  5. *
  6. * This package is free software; you can redistribute it and/or
  7. * modify it under the terms of the license found in the file
  8. * named COPYING that should have accompanied this file.
  9. *
  10. * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
  11. * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
  12. * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
  13. *
  14. * Author: Jian Zhang jzhang@ti.com, Texas Instruments
  15. *
  16. * Copyright (c) 2003 Wolfgang Denk, wd@denx.de
  17. * Rewritten to fit into the current U-Boot framework
  18. *
  19. * Adapted for OMAP2420 I2C, r-woodruff2@ti.com
  20. *
  21. * Copyright (c) 2013 Lubomir Popov <lpopov@mm-sol.com>, MM Solutions
  22. * New i2c_read, i2c_write and i2c_probe functions, tested on OMAP4
  23. * (4430/60/70), OMAP5 (5430) and AM335X (3359); should work on older
  24. * OMAPs and derivatives as well. The only anticipated exception would
  25. * be the OMAP2420, which shall require driver modification.
  26. * - Rewritten i2c_read to operate correctly with all types of chips
  27. * (old function could not read consistent data from some I2C slaves).
  28. * - Optimized i2c_write.
  29. * - New i2c_probe, performs write access vs read. The old probe could
  30. * hang the system under certain conditions (e.g. unconfigured pads).
  31. * - The read/write/probe functions try to identify unconfigured bus.
  32. * - Status functions now read irqstatus_raw as per TRM guidelines
  33. * (except for OMAP243X and OMAP34XX).
  34. * - Driver now supports up to I2C5 (OMAP5).
  35. *
  36. * Copyright (c) 2014 Hannes Schmelzer <oe5hpm@oevsv.at>, B&R
  37. * - Added support for set_speed
  38. *
  39. */
  40. #include <common.h>
  41. #include <dm.h>
  42. #include <i2c.h>
  43. #include <asm/io.h>
  44. #include <asm/omap_i2c.h>
  45. /*
  46. * Provide access to architecture-specific I2C header files for platforms
  47. * that are NOT yet solely relying on CONFIG_DM_I2C, CONFIG_OF_CONTROL, and
  48. * the defaults provided in 'omap24xx_i2c.h' for all U-Boot stages where I2C
  49. * access is desired.
  50. */
  51. #ifndef CONFIG_ARCH_K3
  52. #include <asm/arch/i2c.h>
  53. #endif
  54. #include "omap24xx_i2c.h"
  55. #define I2C_TIMEOUT 1000
  56. /* Absolutely safe for status update at 100 kHz I2C: */
  57. #define I2C_WAIT 200
  58. enum {
  59. OMAP_I2C_REV_REG = 0, /* Only on IP V1 (OMAP34XX) */
  60. OMAP_I2C_IE_REG, /* Only on IP V1 (OMAP34XX) */
  61. OMAP_I2C_STAT_REG,
  62. OMAP_I2C_WE_REG,
  63. OMAP_I2C_SYSS_REG,
  64. OMAP_I2C_BUF_REG,
  65. OMAP_I2C_CNT_REG,
  66. OMAP_I2C_DATA_REG,
  67. OMAP_I2C_SYSC_REG,
  68. OMAP_I2C_CON_REG,
  69. OMAP_I2C_OA_REG,
  70. OMAP_I2C_SA_REG,
  71. OMAP_I2C_PSC_REG,
  72. OMAP_I2C_SCLL_REG,
  73. OMAP_I2C_SCLH_REG,
  74. OMAP_I2C_SYSTEST_REG,
  75. OMAP_I2C_BUFSTAT_REG,
  76. /* Only on IP V2 (OMAP4430, etc.) */
  77. OMAP_I2C_IP_V2_REVNB_LO,
  78. OMAP_I2C_IP_V2_REVNB_HI,
  79. OMAP_I2C_IP_V2_IRQSTATUS_RAW,
  80. OMAP_I2C_IP_V2_IRQENABLE_SET,
  81. OMAP_I2C_IP_V2_IRQENABLE_CLR,
  82. };
  83. static const u8 __maybe_unused reg_map_ip_v1[] = {
  84. [OMAP_I2C_REV_REG] = 0x00,
  85. [OMAP_I2C_IE_REG] = 0x04,
  86. [OMAP_I2C_STAT_REG] = 0x08,
  87. [OMAP_I2C_WE_REG] = 0x0c,
  88. [OMAP_I2C_SYSS_REG] = 0x10,
  89. [OMAP_I2C_BUF_REG] = 0x14,
  90. [OMAP_I2C_CNT_REG] = 0x18,
  91. [OMAP_I2C_DATA_REG] = 0x1c,
  92. [OMAP_I2C_SYSC_REG] = 0x20,
  93. [OMAP_I2C_CON_REG] = 0x24,
  94. [OMAP_I2C_OA_REG] = 0x28,
  95. [OMAP_I2C_SA_REG] = 0x2c,
  96. [OMAP_I2C_PSC_REG] = 0x30,
  97. [OMAP_I2C_SCLL_REG] = 0x34,
  98. [OMAP_I2C_SCLH_REG] = 0x38,
  99. [OMAP_I2C_SYSTEST_REG] = 0x3c,
  100. [OMAP_I2C_BUFSTAT_REG] = 0x40,
  101. };
  102. static const u8 __maybe_unused reg_map_ip_v2[] = {
  103. [OMAP_I2C_STAT_REG] = 0x28,
  104. [OMAP_I2C_WE_REG] = 0x34,
  105. [OMAP_I2C_SYSS_REG] = 0x90,
  106. [OMAP_I2C_BUF_REG] = 0x94,
  107. [OMAP_I2C_CNT_REG] = 0x98,
  108. [OMAP_I2C_DATA_REG] = 0x9c,
  109. [OMAP_I2C_SYSC_REG] = 0x10,
  110. [OMAP_I2C_CON_REG] = 0xa4,
  111. [OMAP_I2C_OA_REG] = 0xa8,
  112. [OMAP_I2C_SA_REG] = 0xac,
  113. [OMAP_I2C_PSC_REG] = 0xb0,
  114. [OMAP_I2C_SCLL_REG] = 0xb4,
  115. [OMAP_I2C_SCLH_REG] = 0xb8,
  116. [OMAP_I2C_SYSTEST_REG] = 0xbc,
  117. [OMAP_I2C_BUFSTAT_REG] = 0xc0,
  118. [OMAP_I2C_IP_V2_REVNB_LO] = 0x00,
  119. [OMAP_I2C_IP_V2_REVNB_HI] = 0x04,
  120. [OMAP_I2C_IP_V2_IRQSTATUS_RAW] = 0x24,
  121. [OMAP_I2C_IP_V2_IRQENABLE_SET] = 0x2c,
  122. [OMAP_I2C_IP_V2_IRQENABLE_CLR] = 0x30,
  123. };
  124. struct omap_i2c {
  125. struct udevice *clk;
  126. int ip_rev;
  127. struct i2c *regs;
  128. unsigned int speed;
  129. int waitdelay;
  130. int clk_id;
  131. };
  132. static inline const u8 *omap_i2c_get_ip_reg_map(int ip_rev)
  133. {
  134. switch (ip_rev) {
  135. case OMAP_I2C_REV_V1:
  136. return reg_map_ip_v1;
  137. case OMAP_I2C_REV_V2:
  138. /* Fall through... */
  139. default:
  140. return reg_map_ip_v2;
  141. }
  142. }
  143. static inline void omap_i2c_write_reg(void __iomem *base, int ip_rev,
  144. u16 val, int reg)
  145. {
  146. writew(val, base + omap_i2c_get_ip_reg_map(ip_rev)[reg]);
  147. }
  148. static inline u16 omap_i2c_read_reg(void __iomem *base, int ip_rev, int reg)
  149. {
  150. return readw(base + omap_i2c_get_ip_reg_map(ip_rev)[reg]);
  151. }
  152. static int omap24_i2c_findpsc(u32 *pscl, u32 *psch, uint speed)
  153. {
  154. unsigned long internal_clk = 0, fclk;
  155. unsigned int prescaler;
  156. /*
  157. * This method is only called for Standard and Fast Mode speeds
  158. *
  159. * For some TI SoCs it is explicitly written in TRM (e,g, SPRUHZ6G,
  160. * page 5685, Table 24-7)
  161. * that the internal I2C clock (after prescaler) should be between
  162. * 7-12 MHz (at least for Fast Mode (FS)).
  163. *
  164. * Such approach is used in v4.9 Linux kernel in:
  165. * ./drivers/i2c/busses/i2c-omap.c (omap_i2c_init function).
  166. */
  167. speed /= 1000; /* convert speed to kHz */
  168. if (speed > 100)
  169. internal_clk = 9600;
  170. else
  171. internal_clk = 4000;
  172. fclk = I2C_IP_CLK / 1000;
  173. prescaler = fclk / internal_clk;
  174. prescaler = prescaler - 1;
  175. if (speed > 100) {
  176. unsigned long scl;
  177. /* Fast mode */
  178. scl = internal_clk / speed;
  179. *pscl = scl - (scl / 3) - I2C_FASTSPEED_SCLL_TRIM;
  180. *psch = (scl / 3) - I2C_FASTSPEED_SCLH_TRIM;
  181. } else {
  182. /* Standard mode */
  183. *pscl = internal_clk / (speed * 2) - I2C_FASTSPEED_SCLL_TRIM;
  184. *psch = internal_clk / (speed * 2) - I2C_FASTSPEED_SCLH_TRIM;
  185. }
  186. debug("%s: speed [kHz]: %d psc: 0x%x sscl: 0x%x ssch: 0x%x\n",
  187. __func__, speed, prescaler, *pscl, *psch);
  188. if (*pscl <= 0 || *psch <= 0 || prescaler <= 0)
  189. return -EINVAL;
  190. return prescaler;
  191. }
  192. /*
  193. * Wait for the bus to be free by checking the Bus Busy (BB)
  194. * bit to become clear
  195. */
  196. static int wait_for_bb(void __iomem *i2c_base, int ip_rev, int waitdelay)
  197. {
  198. int timeout = I2C_TIMEOUT;
  199. int irq_stat_reg;
  200. u16 stat;
  201. irq_stat_reg = (ip_rev == OMAP_I2C_REV_V1) ?
  202. OMAP_I2C_STAT_REG : OMAP_I2C_IP_V2_IRQSTATUS_RAW;
  203. /* clear current interrupts */
  204. omap_i2c_write_reg(i2c_base, ip_rev, 0xFFFF, OMAP_I2C_STAT_REG);
  205. while ((stat = omap_i2c_read_reg(i2c_base, ip_rev, irq_stat_reg) &
  206. I2C_STAT_BB) && timeout--) {
  207. omap_i2c_write_reg(i2c_base, ip_rev, stat, OMAP_I2C_STAT_REG);
  208. udelay(waitdelay);
  209. }
  210. if (timeout <= 0) {
  211. printf("Timed out in %s: status=%04x\n", __func__, stat);
  212. return 1;
  213. }
  214. /* clear delayed stuff */
  215. omap_i2c_write_reg(i2c_base, ip_rev, 0xFFFF, OMAP_I2C_STAT_REG);
  216. return 0;
  217. }
  218. /*
  219. * Wait for the I2C controller to complete current action
  220. * and update status
  221. */
  222. static u16 wait_for_event(void __iomem *i2c_base, int ip_rev, int waitdelay)
  223. {
  224. u16 status;
  225. int timeout = I2C_TIMEOUT;
  226. int irq_stat_reg;
  227. irq_stat_reg = (ip_rev == OMAP_I2C_REV_V1) ?
  228. OMAP_I2C_STAT_REG : OMAP_I2C_IP_V2_IRQSTATUS_RAW;
  229. do {
  230. udelay(waitdelay);
  231. status = omap_i2c_read_reg(i2c_base, ip_rev, irq_stat_reg);
  232. } while (!(status &
  233. (I2C_STAT_ROVR | I2C_STAT_XUDF | I2C_STAT_XRDY |
  234. I2C_STAT_RRDY | I2C_STAT_ARDY | I2C_STAT_NACK |
  235. I2C_STAT_AL)) && timeout--);
  236. if (timeout <= 0) {
  237. printf("Timed out in %s: status=%04x\n", __func__, status);
  238. /*
  239. * If status is still 0 here, probably the bus pads have
  240. * not been configured for I2C, and/or pull-ups are missing.
  241. */
  242. printf("Check if pads/pull-ups of bus are properly configured\n");
  243. omap_i2c_write_reg(i2c_base, ip_rev, 0xFFFF, OMAP_I2C_STAT_REG);
  244. status = 0;
  245. }
  246. return status;
  247. }
  248. static void flush_fifo(void __iomem *i2c_base, int ip_rev)
  249. {
  250. u16 stat;
  251. /*
  252. * note: if you try and read data when its not there or ready
  253. * you get a bus error
  254. */
  255. while (1) {
  256. stat = omap_i2c_read_reg(i2c_base, ip_rev, OMAP_I2C_STAT_REG);
  257. if (stat == I2C_STAT_RRDY) {
  258. omap_i2c_read_reg(i2c_base, ip_rev, OMAP_I2C_DATA_REG);
  259. omap_i2c_write_reg(i2c_base, ip_rev,
  260. I2C_STAT_RRDY, OMAP_I2C_STAT_REG);
  261. udelay(1000);
  262. } else
  263. break;
  264. }
  265. }
  266. static int __omap24_i2c_setspeed(void __iomem *i2c_base, int ip_rev, uint speed,
  267. int *waitdelay)
  268. {
  269. int psc, fsscll = 0, fssclh = 0;
  270. int hsscll = 0, hssclh = 0;
  271. u32 scll = 0, sclh = 0;
  272. if (speed >= I2C_SPEED_HIGH_RATE) {
  273. /* High speed */
  274. psc = I2C_IP_CLK / I2C_INTERNAL_SAMPLING_CLK;
  275. psc -= 1;
  276. if (psc < I2C_PSC_MIN) {
  277. printf("Error : I2C unsupported prescaler %d\n", psc);
  278. return -1;
  279. }
  280. /* For first phase of HS mode */
  281. fsscll = I2C_INTERNAL_SAMPLING_CLK / (2 * speed);
  282. fssclh = fsscll;
  283. fsscll -= I2C_HIGHSPEED_PHASE_ONE_SCLL_TRIM;
  284. fssclh -= I2C_HIGHSPEED_PHASE_ONE_SCLH_TRIM;
  285. if (((fsscll < 0) || (fssclh < 0)) ||
  286. ((fsscll > 255) || (fssclh > 255))) {
  287. puts("Error : I2C initializing first phase clock\n");
  288. return -1;
  289. }
  290. /* For second phase of HS mode */
  291. hsscll = hssclh = I2C_INTERNAL_SAMPLING_CLK / (2 * speed);
  292. hsscll -= I2C_HIGHSPEED_PHASE_TWO_SCLL_TRIM;
  293. hssclh -= I2C_HIGHSPEED_PHASE_TWO_SCLH_TRIM;
  294. if (((fsscll < 0) || (fssclh < 0)) ||
  295. ((fsscll > 255) || (fssclh > 255))) {
  296. puts("Error : I2C initializing second phase clock\n");
  297. return -1;
  298. }
  299. scll = (unsigned int)hsscll << 8 | (unsigned int)fsscll;
  300. sclh = (unsigned int)hssclh << 8 | (unsigned int)fssclh;
  301. } else {
  302. /* Standard and fast speed */
  303. psc = omap24_i2c_findpsc(&scll, &sclh, speed);
  304. if (0 > psc) {
  305. puts("Error : I2C initializing clock\n");
  306. return -1;
  307. }
  308. }
  309. /* wait for 20 clkperiods */
  310. *waitdelay = (10000000 / speed) * 2;
  311. omap_i2c_write_reg(i2c_base, ip_rev, 0, OMAP_I2C_CON_REG);
  312. omap_i2c_write_reg(i2c_base, ip_rev, psc, OMAP_I2C_PSC_REG);
  313. omap_i2c_write_reg(i2c_base, ip_rev, scll, OMAP_I2C_SCLL_REG);
  314. omap_i2c_write_reg(i2c_base, ip_rev, sclh, OMAP_I2C_SCLH_REG);
  315. omap_i2c_write_reg(i2c_base, ip_rev, I2C_CON_EN, OMAP_I2C_CON_REG);
  316. /* clear all pending status */
  317. omap_i2c_write_reg(i2c_base, ip_rev, 0xFFFF, OMAP_I2C_STAT_REG);
  318. return 0;
  319. }
  320. static void omap24_i2c_deblock(void __iomem *i2c_base, int ip_rev)
  321. {
  322. int i;
  323. u16 systest;
  324. u16 orgsystest;
  325. /* set test mode ST_EN = 1 */
  326. orgsystest = omap_i2c_read_reg(i2c_base, ip_rev, OMAP_I2C_SYSTEST_REG);
  327. systest = orgsystest;
  328. /* enable testmode */
  329. systest |= I2C_SYSTEST_ST_EN;
  330. omap_i2c_write_reg(i2c_base, ip_rev, systest, OMAP_I2C_SYSTEST_REG);
  331. systest &= ~I2C_SYSTEST_TMODE_MASK;
  332. systest |= 3 << I2C_SYSTEST_TMODE_SHIFT;
  333. omap_i2c_write_reg(i2c_base, ip_rev, systest, OMAP_I2C_SYSTEST_REG);
  334. /* set SCL, SDA = 1 */
  335. systest |= I2C_SYSTEST_SCL_O | I2C_SYSTEST_SDA_O;
  336. omap_i2c_write_reg(i2c_base, ip_rev, systest, OMAP_I2C_SYSTEST_REG);
  337. udelay(10);
  338. /* toggle scl 9 clocks */
  339. for (i = 0; i < 9; i++) {
  340. /* SCL = 0 */
  341. systest &= ~I2C_SYSTEST_SCL_O;
  342. omap_i2c_write_reg(i2c_base, ip_rev,
  343. systest, OMAP_I2C_SYSTEST_REG);
  344. udelay(10);
  345. /* SCL = 1 */
  346. systest |= I2C_SYSTEST_SCL_O;
  347. omap_i2c_write_reg(i2c_base, ip_rev,
  348. systest, OMAP_I2C_SYSTEST_REG);
  349. udelay(10);
  350. }
  351. /* send stop */
  352. systest &= ~I2C_SYSTEST_SDA_O;
  353. omap_i2c_write_reg(i2c_base, ip_rev, systest, OMAP_I2C_SYSTEST_REG);
  354. udelay(10);
  355. systest |= I2C_SYSTEST_SCL_O | I2C_SYSTEST_SDA_O;
  356. omap_i2c_write_reg(i2c_base, ip_rev, systest, OMAP_I2C_SYSTEST_REG);
  357. udelay(10);
  358. /* restore original mode */
  359. omap_i2c_write_reg(i2c_base, ip_rev, orgsystest, OMAP_I2C_SYSTEST_REG);
  360. }
  361. static void __omap24_i2c_init(void __iomem *i2c_base, int ip_rev, int speed,
  362. int slaveadd, int *waitdelay)
  363. {
  364. int timeout = I2C_TIMEOUT;
  365. int deblock = 1;
  366. retry:
  367. if (omap_i2c_read_reg(i2c_base, ip_rev, OMAP_I2C_CON_REG) &
  368. I2C_CON_EN) {
  369. omap_i2c_write_reg(i2c_base, ip_rev, 0, OMAP_I2C_CON_REG);
  370. udelay(50000);
  371. }
  372. /* for ES2 after soft reset */
  373. omap_i2c_write_reg(i2c_base, ip_rev, 0x2, OMAP_I2C_SYSC_REG);
  374. udelay(1000);
  375. omap_i2c_write_reg(i2c_base, ip_rev, I2C_CON_EN, OMAP_I2C_CON_REG);
  376. while (!(omap_i2c_read_reg(i2c_base, ip_rev, OMAP_I2C_SYSS_REG) &
  377. I2C_SYSS_RDONE) && timeout--) {
  378. if (timeout <= 0) {
  379. puts("ERROR: Timeout in soft-reset\n");
  380. return;
  381. }
  382. udelay(1000);
  383. }
  384. if (__omap24_i2c_setspeed(i2c_base, ip_rev, speed, waitdelay)) {
  385. printf("ERROR: failed to setup I2C bus-speed!\n");
  386. return;
  387. }
  388. /* own address */
  389. omap_i2c_write_reg(i2c_base, ip_rev, slaveadd, OMAP_I2C_OA_REG);
  390. if (ip_rev == OMAP_I2C_REV_V1) {
  391. /*
  392. * Have to enable interrupts for OMAP2/3, these IPs don't have
  393. * an 'irqstatus_raw' register and we shall have to poll 'stat'
  394. */
  395. omap_i2c_write_reg(i2c_base, ip_rev, I2C_IE_XRDY_IE |
  396. I2C_IE_RRDY_IE | I2C_IE_ARDY_IE |
  397. I2C_IE_NACK_IE | I2C_IE_AL_IE,
  398. OMAP_I2C_IE_REG);
  399. }
  400. udelay(1000);
  401. flush_fifo(i2c_base, ip_rev);
  402. omap_i2c_write_reg(i2c_base, ip_rev, 0xFFFF, OMAP_I2C_STAT_REG);
  403. /* Handle possible failed I2C state */
  404. if (wait_for_bb(i2c_base, ip_rev, *waitdelay))
  405. if (deblock == 1) {
  406. omap24_i2c_deblock(i2c_base, ip_rev);
  407. deblock = 0;
  408. goto retry;
  409. }
  410. }
  411. /*
  412. * i2c_probe: Use write access. Allows to identify addresses that are
  413. * write-only (like the config register of dual-port EEPROMs)
  414. */
  415. static int __omap24_i2c_probe(void __iomem *i2c_base, int ip_rev, int waitdelay,
  416. uchar chip)
  417. {
  418. u16 status;
  419. int res = 1; /* default = fail */
  420. if (chip == omap_i2c_read_reg(i2c_base, ip_rev, OMAP_I2C_OA_REG))
  421. return res;
  422. /* Wait until bus is free */
  423. if (wait_for_bb(i2c_base, ip_rev, waitdelay))
  424. return res;
  425. /* No data transfer, slave addr only */
  426. omap_i2c_write_reg(i2c_base, ip_rev, chip, OMAP_I2C_SA_REG);
  427. /* Stop bit needed here */
  428. omap_i2c_write_reg(i2c_base, ip_rev, I2C_CON_EN | I2C_CON_MST |
  429. I2C_CON_STT | I2C_CON_TRX | I2C_CON_STP,
  430. OMAP_I2C_CON_REG);
  431. status = wait_for_event(i2c_base, ip_rev, waitdelay);
  432. if ((status & ~I2C_STAT_XRDY) == 0 || (status & I2C_STAT_AL)) {
  433. /*
  434. * With current high-level command implementation, notifying
  435. * the user shall flood the console with 127 messages. If
  436. * silent exit is desired upon unconfigured bus, remove the
  437. * following 'if' section:
  438. */
  439. if (status == I2C_STAT_XRDY)
  440. printf("i2c_probe: pads on bus probably not configured (status=0x%x)\n",
  441. status);
  442. goto pr_exit;
  443. }
  444. /* Check for ACK (!NAK) */
  445. if (!(status & I2C_STAT_NACK)) {
  446. res = 0; /* Device found */
  447. udelay(waitdelay);/* Required by AM335X in SPL */
  448. /* Abort transfer (force idle state) */
  449. omap_i2c_write_reg(i2c_base, ip_rev, I2C_CON_MST | I2C_CON_TRX,
  450. OMAP_I2C_CON_REG); /* Reset */
  451. udelay(1000);
  452. omap_i2c_write_reg(i2c_base, ip_rev, I2C_CON_EN | I2C_CON_MST |
  453. I2C_CON_TRX | I2C_CON_STP,
  454. OMAP_I2C_CON_REG); /* STP */
  455. }
  456. pr_exit:
  457. flush_fifo(i2c_base, ip_rev);
  458. omap_i2c_write_reg(i2c_base, ip_rev, 0xFFFF, OMAP_I2C_STAT_REG);
  459. return res;
  460. }
  461. /*
  462. * i2c_read: Function now uses a single I2C read transaction with bulk transfer
  463. * of the requested number of bytes (note that the 'i2c md' command
  464. * limits this to 16 bytes anyway). If CONFIG_I2C_REPEATED_START is
  465. * defined in the board config header, this transaction shall be with
  466. * Repeated Start (Sr) between the address and data phases; otherwise
  467. * Stop-Start (P-S) shall be used (some I2C chips do require a P-S).
  468. * The address (reg offset) may be 0, 1 or 2 bytes long.
  469. * Function now reads correctly from chips that return more than one
  470. * byte of data per addressed register (like TI temperature sensors),
  471. * or that do not need a register address at all (such as some clock
  472. * distributors).
  473. */
  474. static int __omap24_i2c_read(void __iomem *i2c_base, int ip_rev, int waitdelay,
  475. uchar chip, uint addr, int alen, uchar *buffer,
  476. int len)
  477. {
  478. int i2c_error = 0;
  479. u16 status;
  480. if (alen < 0) {
  481. puts("I2C read: addr len < 0\n");
  482. return 1;
  483. }
  484. if (len < 0) {
  485. puts("I2C read: data len < 0\n");
  486. return 1;
  487. }
  488. if (buffer == NULL) {
  489. puts("I2C read: NULL pointer passed\n");
  490. return 1;
  491. }
  492. if (alen > 2) {
  493. printf("I2C read: addr len %d not supported\n", alen);
  494. return 1;
  495. }
  496. if (addr + len > (1 << 16)) {
  497. puts("I2C read: address out of range\n");
  498. return 1;
  499. }
  500. #ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
  501. /*
  502. * EEPROM chips that implement "address overflow" are ones
  503. * like Catalyst 24WC04/08/16 which has 9/10/11 bits of
  504. * address and the extra bits end up in the "chip address"
  505. * bit slots. This makes a 24WC08 (1Kbyte) chip look like
  506. * four 256 byte chips.
  507. *
  508. * Note that we consider the length of the address field to
  509. * still be one byte because the extra address bits are
  510. * hidden in the chip address.
  511. */
  512. if (alen > 0)
  513. chip |= ((addr >> (alen * 8)) &
  514. CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW);
  515. #endif
  516. /* Wait until bus not busy */
  517. if (wait_for_bb(i2c_base, ip_rev, waitdelay))
  518. return 1;
  519. /* Zero, one or two bytes reg address (offset) */
  520. omap_i2c_write_reg(i2c_base, ip_rev, alen, OMAP_I2C_CNT_REG);
  521. /* Set slave address */
  522. omap_i2c_write_reg(i2c_base, ip_rev, chip, OMAP_I2C_SA_REG);
  523. if (alen) {
  524. /* Must write reg offset first */
  525. #ifdef CONFIG_I2C_REPEATED_START
  526. /* No stop bit, use Repeated Start (Sr) */
  527. omap_i2c_write_reg(i2c_base, ip_rev, I2C_CON_EN | I2C_CON_MST |
  528. I2C_CON_STT | I2C_CON_TRX, OMAP_I2C_CON_REG);
  529. #else
  530. /* Stop - Start (P-S) */
  531. omap_i2c_write_reg(i2c_base, ip_rev, I2C_CON_EN | I2C_CON_MST |
  532. I2C_CON_STT | I2C_CON_STP | I2C_CON_TRX,
  533. OMAP_I2C_CON_REG);
  534. #endif
  535. /* Send register offset */
  536. while (1) {
  537. status = wait_for_event(i2c_base, ip_rev, waitdelay);
  538. /* Try to identify bus that is not padconf'd for I2C */
  539. if (status == I2C_STAT_XRDY) {
  540. i2c_error = 2;
  541. printf("i2c_read (addr phase): pads on bus probably not configured (status=0x%x)\n",
  542. status);
  543. goto rd_exit;
  544. }
  545. if (status == 0 || (status & I2C_STAT_NACK)) {
  546. i2c_error = 1;
  547. printf("i2c_read: error waiting for addr ACK (status=0x%x)\n",
  548. status);
  549. goto rd_exit;
  550. }
  551. if (alen) {
  552. if (status & I2C_STAT_XRDY) {
  553. u8 addr_byte;
  554. alen--;
  555. addr_byte = (addr >> (8 * alen)) & 0xff;
  556. omap_i2c_write_reg(i2c_base, ip_rev,
  557. addr_byte,
  558. OMAP_I2C_DATA_REG);
  559. omap_i2c_write_reg(i2c_base, ip_rev,
  560. I2C_STAT_XRDY,
  561. OMAP_I2C_STAT_REG);
  562. }
  563. }
  564. if (status & I2C_STAT_ARDY) {
  565. omap_i2c_write_reg(i2c_base, ip_rev,
  566. I2C_STAT_ARDY,
  567. OMAP_I2C_STAT_REG);
  568. break;
  569. }
  570. }
  571. }
  572. /* Set slave address */
  573. omap_i2c_write_reg(i2c_base, ip_rev, chip, OMAP_I2C_SA_REG);
  574. /* Read len bytes from slave */
  575. omap_i2c_write_reg(i2c_base, ip_rev, len, OMAP_I2C_CNT_REG);
  576. /* Need stop bit here */
  577. omap_i2c_write_reg(i2c_base, ip_rev, I2C_CON_EN | I2C_CON_MST |
  578. I2C_CON_STT | I2C_CON_STP, OMAP_I2C_CON_REG);
  579. /* Receive data */
  580. while (1) {
  581. status = wait_for_event(i2c_base, ip_rev, waitdelay);
  582. /*
  583. * Try to identify bus that is not padconf'd for I2C. This
  584. * state could be left over from previous transactions if
  585. * the address phase is skipped due to alen=0.
  586. */
  587. if (status == I2C_STAT_XRDY) {
  588. i2c_error = 2;
  589. printf("i2c_read (data phase): pads on bus probably not configured (status=0x%x)\n",
  590. status);
  591. goto rd_exit;
  592. }
  593. if (status == 0 || (status & I2C_STAT_NACK)) {
  594. i2c_error = 1;
  595. goto rd_exit;
  596. }
  597. if (status & I2C_STAT_RRDY) {
  598. *buffer++ = omap_i2c_read_reg(i2c_base, ip_rev,
  599. OMAP_I2C_DATA_REG);
  600. omap_i2c_write_reg(i2c_base, ip_rev,
  601. I2C_STAT_RRDY, OMAP_I2C_STAT_REG);
  602. }
  603. if (status & I2C_STAT_ARDY) {
  604. omap_i2c_write_reg(i2c_base, ip_rev,
  605. I2C_STAT_ARDY, OMAP_I2C_STAT_REG);
  606. break;
  607. }
  608. }
  609. rd_exit:
  610. flush_fifo(i2c_base, ip_rev);
  611. omap_i2c_write_reg(i2c_base, ip_rev, 0xFFFF, OMAP_I2C_STAT_REG);
  612. return i2c_error;
  613. }
  614. /* i2c_write: Address (reg offset) may be 0, 1 or 2 bytes long. */
  615. static int __omap24_i2c_write(void __iomem *i2c_base, int ip_rev, int waitdelay,
  616. uchar chip, uint addr, int alen, uchar *buffer,
  617. int len)
  618. {
  619. int i;
  620. u16 status;
  621. int i2c_error = 0;
  622. int timeout = I2C_TIMEOUT;
  623. if (alen < 0) {
  624. puts("I2C write: addr len < 0\n");
  625. return 1;
  626. }
  627. if (len < 0) {
  628. puts("I2C write: data len < 0\n");
  629. return 1;
  630. }
  631. if (buffer == NULL) {
  632. puts("I2C write: NULL pointer passed\n");
  633. return 1;
  634. }
  635. if (alen > 2) {
  636. printf("I2C write: addr len %d not supported\n", alen);
  637. return 1;
  638. }
  639. if (addr + len > (1 << 16)) {
  640. printf("I2C write: address 0x%x + 0x%x out of range\n",
  641. addr, len);
  642. return 1;
  643. }
  644. #ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
  645. /*
  646. * EEPROM chips that implement "address overflow" are ones
  647. * like Catalyst 24WC04/08/16 which has 9/10/11 bits of
  648. * address and the extra bits end up in the "chip address"
  649. * bit slots. This makes a 24WC08 (1Kbyte) chip look like
  650. * four 256 byte chips.
  651. *
  652. * Note that we consider the length of the address field to
  653. * still be one byte because the extra address bits are
  654. * hidden in the chip address.
  655. */
  656. if (alen > 0)
  657. chip |= ((addr >> (alen * 8)) &
  658. CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW);
  659. #endif
  660. /* Wait until bus not busy */
  661. if (wait_for_bb(i2c_base, ip_rev, waitdelay))
  662. return 1;
  663. /* Start address phase - will write regoffset + len bytes data */
  664. omap_i2c_write_reg(i2c_base, ip_rev, alen + len, OMAP_I2C_CNT_REG);
  665. /* Set slave address */
  666. omap_i2c_write_reg(i2c_base, ip_rev, chip, OMAP_I2C_SA_REG);
  667. /* Stop bit needed here */
  668. omap_i2c_write_reg(i2c_base, ip_rev, I2C_CON_EN | I2C_CON_MST |
  669. I2C_CON_STT | I2C_CON_TRX | I2C_CON_STP,
  670. OMAP_I2C_CON_REG);
  671. while (alen) {
  672. /* Must write reg offset (one or two bytes) */
  673. status = wait_for_event(i2c_base, ip_rev, waitdelay);
  674. /* Try to identify bus that is not padconf'd for I2C */
  675. if (status == I2C_STAT_XRDY) {
  676. i2c_error = 2;
  677. printf("i2c_write: pads on bus probably not configured (status=0x%x)\n",
  678. status);
  679. goto wr_exit;
  680. }
  681. if (status == 0 || (status & I2C_STAT_NACK)) {
  682. i2c_error = 1;
  683. printf("i2c_write: error waiting for addr ACK (status=0x%x)\n",
  684. status);
  685. goto wr_exit;
  686. }
  687. if (status & I2C_STAT_XRDY) {
  688. alen--;
  689. omap_i2c_write_reg(i2c_base, ip_rev,
  690. (addr >> (8 * alen)) & 0xff,
  691. OMAP_I2C_DATA_REG);
  692. omap_i2c_write_reg(i2c_base, ip_rev,
  693. I2C_STAT_XRDY, OMAP_I2C_STAT_REG);
  694. } else {
  695. i2c_error = 1;
  696. printf("i2c_write: bus not ready for addr Tx (status=0x%x)\n",
  697. status);
  698. goto wr_exit;
  699. }
  700. }
  701. /* Address phase is over, now write data */
  702. for (i = 0; i < len; i++) {
  703. status = wait_for_event(i2c_base, ip_rev, waitdelay);
  704. if (status == 0 || (status & I2C_STAT_NACK)) {
  705. i2c_error = 1;
  706. printf("i2c_write: error waiting for data ACK (status=0x%x)\n",
  707. status);
  708. goto wr_exit;
  709. }
  710. if (status & I2C_STAT_XRDY) {
  711. omap_i2c_write_reg(i2c_base, ip_rev,
  712. buffer[i], OMAP_I2C_DATA_REG);
  713. omap_i2c_write_reg(i2c_base, ip_rev,
  714. I2C_STAT_XRDY, OMAP_I2C_STAT_REG);
  715. } else {
  716. i2c_error = 1;
  717. printf("i2c_write: bus not ready for data Tx (i=%d)\n",
  718. i);
  719. goto wr_exit;
  720. }
  721. }
  722. /*
  723. * poll ARDY bit for making sure that last byte really has been
  724. * transferred on the bus.
  725. */
  726. do {
  727. status = wait_for_event(i2c_base, ip_rev, waitdelay);
  728. } while (!(status & I2C_STAT_ARDY) && timeout--);
  729. if (timeout <= 0)
  730. printf("i2c_write: timed out writig last byte!\n");
  731. wr_exit:
  732. flush_fifo(i2c_base, ip_rev);
  733. omap_i2c_write_reg(i2c_base, ip_rev, 0xFFFF, OMAP_I2C_STAT_REG);
  734. return i2c_error;
  735. }
  736. #ifndef CONFIG_DM_I2C
  737. /*
  738. * The legacy I2C functions. These need to get removed once
  739. * all users of this driver are converted to DM.
  740. */
  741. static void __iomem *omap24_get_base(struct i2c_adapter *adap)
  742. {
  743. switch (adap->hwadapnr) {
  744. case 0:
  745. return (void __iomem *)I2C_BASE1;
  746. break;
  747. case 1:
  748. return (void __iomem *)I2C_BASE2;
  749. break;
  750. #if (CONFIG_SYS_I2C_BUS_MAX > 2)
  751. case 2:
  752. return (void __iomem *)I2C_BASE3;
  753. break;
  754. #if (CONFIG_SYS_I2C_BUS_MAX > 3)
  755. case 3:
  756. return (void __iomem *)I2C_BASE4;
  757. break;
  758. #if (CONFIG_SYS_I2C_BUS_MAX > 4)
  759. case 4:
  760. return (void __iomem *)I2C_BASE5;
  761. break;
  762. #endif
  763. #endif
  764. #endif
  765. default:
  766. printf("wrong hwadapnr: %d\n", adap->hwadapnr);
  767. break;
  768. }
  769. return NULL;
  770. }
  771. static int omap24_get_ip_rev(void)
  772. {
  773. #ifdef CONFIG_OMAP34XX
  774. return OMAP_I2C_REV_V1;
  775. #else
  776. return OMAP_I2C_REV_V2;
  777. #endif
  778. }
  779. static int omap24_i2c_read(struct i2c_adapter *adap, uchar chip, uint addr,
  780. int alen, uchar *buffer, int len)
  781. {
  782. void __iomem *i2c_base = omap24_get_base(adap);
  783. int ip_rev = omap24_get_ip_rev();
  784. return __omap24_i2c_read(i2c_base, ip_rev, adap->waitdelay, chip, addr,
  785. alen, buffer, len);
  786. }
  787. static int omap24_i2c_write(struct i2c_adapter *adap, uchar chip, uint addr,
  788. int alen, uchar *buffer, int len)
  789. {
  790. void __iomem *i2c_base = omap24_get_base(adap);
  791. int ip_rev = omap24_get_ip_rev();
  792. return __omap24_i2c_write(i2c_base, ip_rev, adap->waitdelay, chip, addr,
  793. alen, buffer, len);
  794. }
  795. static uint omap24_i2c_setspeed(struct i2c_adapter *adap, uint speed)
  796. {
  797. void __iomem *i2c_base = omap24_get_base(adap);
  798. int ip_rev = omap24_get_ip_rev();
  799. int ret;
  800. ret = __omap24_i2c_setspeed(i2c_base, ip_rev, speed, &adap->waitdelay);
  801. if (ret) {
  802. pr_err("%s: set i2c speed failed\n", __func__);
  803. return ret;
  804. }
  805. adap->speed = speed;
  806. return 0;
  807. }
  808. static void omap24_i2c_init(struct i2c_adapter *adap, int speed, int slaveadd)
  809. {
  810. void __iomem *i2c_base = omap24_get_base(adap);
  811. int ip_rev = omap24_get_ip_rev();
  812. return __omap24_i2c_init(i2c_base, ip_rev, speed, slaveadd,
  813. &adap->waitdelay);
  814. }
  815. static int omap24_i2c_probe(struct i2c_adapter *adap, uchar chip)
  816. {
  817. void __iomem *i2c_base = omap24_get_base(adap);
  818. int ip_rev = omap24_get_ip_rev();
  819. return __omap24_i2c_probe(i2c_base, ip_rev, adap->waitdelay, chip);
  820. }
  821. #if !defined(CONFIG_SYS_OMAP24_I2C_SPEED1)
  822. #define CONFIG_SYS_OMAP24_I2C_SPEED1 CONFIG_SYS_OMAP24_I2C_SPEED
  823. #endif
  824. #if !defined(CONFIG_SYS_OMAP24_I2C_SLAVE1)
  825. #define CONFIG_SYS_OMAP24_I2C_SLAVE1 CONFIG_SYS_OMAP24_I2C_SLAVE
  826. #endif
  827. U_BOOT_I2C_ADAP_COMPLETE(omap24_0, omap24_i2c_init, omap24_i2c_probe,
  828. omap24_i2c_read, omap24_i2c_write, omap24_i2c_setspeed,
  829. CONFIG_SYS_OMAP24_I2C_SPEED,
  830. CONFIG_SYS_OMAP24_I2C_SLAVE,
  831. 0)
  832. U_BOOT_I2C_ADAP_COMPLETE(omap24_1, omap24_i2c_init, omap24_i2c_probe,
  833. omap24_i2c_read, omap24_i2c_write, omap24_i2c_setspeed,
  834. CONFIG_SYS_OMAP24_I2C_SPEED1,
  835. CONFIG_SYS_OMAP24_I2C_SLAVE1,
  836. 1)
  837. #if (CONFIG_SYS_I2C_BUS_MAX > 2)
  838. #if !defined(CONFIG_SYS_OMAP24_I2C_SPEED2)
  839. #define CONFIG_SYS_OMAP24_I2C_SPEED2 CONFIG_SYS_OMAP24_I2C_SPEED
  840. #endif
  841. #if !defined(CONFIG_SYS_OMAP24_I2C_SLAVE2)
  842. #define CONFIG_SYS_OMAP24_I2C_SLAVE2 CONFIG_SYS_OMAP24_I2C_SLAVE
  843. #endif
  844. U_BOOT_I2C_ADAP_COMPLETE(omap24_2, omap24_i2c_init, omap24_i2c_probe,
  845. omap24_i2c_read, omap24_i2c_write, NULL,
  846. CONFIG_SYS_OMAP24_I2C_SPEED2,
  847. CONFIG_SYS_OMAP24_I2C_SLAVE2,
  848. 2)
  849. #if (CONFIG_SYS_I2C_BUS_MAX > 3)
  850. #if !defined(CONFIG_SYS_OMAP24_I2C_SPEED3)
  851. #define CONFIG_SYS_OMAP24_I2C_SPEED3 CONFIG_SYS_OMAP24_I2C_SPEED
  852. #endif
  853. #if !defined(CONFIG_SYS_OMAP24_I2C_SLAVE3)
  854. #define CONFIG_SYS_OMAP24_I2C_SLAVE3 CONFIG_SYS_OMAP24_I2C_SLAVE
  855. #endif
  856. U_BOOT_I2C_ADAP_COMPLETE(omap24_3, omap24_i2c_init, omap24_i2c_probe,
  857. omap24_i2c_read, omap24_i2c_write, NULL,
  858. CONFIG_SYS_OMAP24_I2C_SPEED3,
  859. CONFIG_SYS_OMAP24_I2C_SLAVE3,
  860. 3)
  861. #if (CONFIG_SYS_I2C_BUS_MAX > 4)
  862. #if !defined(CONFIG_SYS_OMAP24_I2C_SPEED4)
  863. #define CONFIG_SYS_OMAP24_I2C_SPEED4 CONFIG_SYS_OMAP24_I2C_SPEED
  864. #endif
  865. #if !defined(CONFIG_SYS_OMAP24_I2C_SLAVE4)
  866. #define CONFIG_SYS_OMAP24_I2C_SLAVE4 CONFIG_SYS_OMAP24_I2C_SLAVE
  867. #endif
  868. U_BOOT_I2C_ADAP_COMPLETE(omap24_4, omap24_i2c_init, omap24_i2c_probe,
  869. omap24_i2c_read, omap24_i2c_write, NULL,
  870. CONFIG_SYS_OMAP24_I2C_SPEED4,
  871. CONFIG_SYS_OMAP24_I2C_SLAVE4,
  872. 4)
  873. #endif
  874. #endif
  875. #endif
  876. #else /* CONFIG_DM_I2C */
  877. static int omap_i2c_xfer(struct udevice *bus, struct i2c_msg *msg, int nmsgs)
  878. {
  879. struct omap_i2c *priv = dev_get_priv(bus);
  880. int ret;
  881. debug("i2c_xfer: %d messages\n", nmsgs);
  882. for (; nmsgs > 0; nmsgs--, msg++) {
  883. debug("i2c_xfer: chip=0x%x, len=0x%x\n", msg->addr, msg->len);
  884. if (msg->flags & I2C_M_RD) {
  885. ret = __omap24_i2c_read(priv->regs, priv->ip_rev,
  886. priv->waitdelay,
  887. msg->addr, 0, 0, msg->buf,
  888. msg->len);
  889. } else {
  890. ret = __omap24_i2c_write(priv->regs, priv->ip_rev,
  891. priv->waitdelay,
  892. msg->addr, 0, 0, msg->buf,
  893. msg->len);
  894. }
  895. if (ret) {
  896. debug("i2c_write: error sending\n");
  897. return -EREMOTEIO;
  898. }
  899. }
  900. return 0;
  901. }
  902. static int omap_i2c_set_bus_speed(struct udevice *bus, unsigned int speed)
  903. {
  904. struct omap_i2c *priv = dev_get_priv(bus);
  905. priv->speed = speed;
  906. return __omap24_i2c_setspeed(priv->regs, priv->ip_rev, speed,
  907. &priv->waitdelay);
  908. }
  909. static int omap_i2c_probe_chip(struct udevice *bus, uint chip_addr,
  910. uint chip_flags)
  911. {
  912. struct omap_i2c *priv = dev_get_priv(bus);
  913. return __omap24_i2c_probe(priv->regs, priv->ip_rev, priv->waitdelay,
  914. chip_addr);
  915. }
  916. static int omap_i2c_probe(struct udevice *bus)
  917. {
  918. struct omap_i2c *priv = dev_get_priv(bus);
  919. struct omap_i2c_platdata *plat = dev_get_platdata(bus);
  920. priv->speed = plat->speed;
  921. priv->regs = map_physmem(plat->base, sizeof(void *),
  922. MAP_NOCACHE);
  923. priv->ip_rev = plat->ip_rev;
  924. __omap24_i2c_init(priv->regs, priv->ip_rev, priv->speed, 0,
  925. &priv->waitdelay);
  926. return 0;
  927. }
  928. #if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
  929. static int omap_i2c_ofdata_to_platdata(struct udevice *bus)
  930. {
  931. struct omap_i2c_platdata *plat = dev_get_platdata(bus);
  932. plat->base = devfdt_get_addr(bus);
  933. plat->speed = dev_read_u32_default(bus, "clock-frequency",
  934. I2C_SPEED_STANDARD_RATE);
  935. plat->ip_rev = dev_get_driver_data(bus);
  936. return 0;
  937. }
  938. static const struct udevice_id omap_i2c_ids[] = {
  939. { .compatible = "ti,omap3-i2c", .data = OMAP_I2C_REV_V1 },
  940. { .compatible = "ti,omap4-i2c", .data = OMAP_I2C_REV_V2 },
  941. { }
  942. };
  943. #endif
  944. static const struct dm_i2c_ops omap_i2c_ops = {
  945. .xfer = omap_i2c_xfer,
  946. .probe_chip = omap_i2c_probe_chip,
  947. .set_bus_speed = omap_i2c_set_bus_speed,
  948. };
  949. U_BOOT_DRIVER(i2c_omap) = {
  950. .name = "i2c_omap",
  951. .id = UCLASS_I2C,
  952. #if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
  953. .of_match = omap_i2c_ids,
  954. .ofdata_to_platdata = omap_i2c_ofdata_to_platdata,
  955. .platdata_auto_alloc_size = sizeof(struct omap_i2c_platdata),
  956. #endif
  957. .probe = omap_i2c_probe,
  958. .priv_auto_alloc_size = sizeof(struct omap_i2c),
  959. .ops = &omap_i2c_ops,
  960. #if !CONFIG_IS_ENABLED(OF_CONTROL)
  961. .flags = DM_FLAG_PRE_RELOC,
  962. #endif
  963. };
  964. #endif /* CONFIG_DM_I2C */