mxc_i2c.c 28 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * i2c driver for Freescale i.MX series
  4. *
  5. * (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
  6. * (c) 2011 Marek Vasut <marek.vasut@gmail.com>
  7. *
  8. * Based on i2c-imx.c from linux kernel:
  9. * Copyright (C) 2005 Torsten Koschorrek <koschorrek at synertronixx.de>
  10. * Copyright (C) 2005 Matthias Blaschke <blaschke at synertronixx.de>
  11. * Copyright (C) 2007 RightHand Technologies, Inc.
  12. * Copyright (C) 2008 Darius Augulis <darius.augulis at teltonika.lt>
  13. *
  14. */
  15. #include <common.h>
  16. #include <asm/arch/clock.h>
  17. #include <asm/arch/imx-regs.h>
  18. #include <dm/device_compat.h>
  19. #include <linux/errno.h>
  20. #include <asm/mach-imx/mxc_i2c.h>
  21. #include <asm/mach-imx/sys_proto.h>
  22. #include <asm/io.h>
  23. #include <i2c.h>
  24. #include <watchdog.h>
  25. #include <dm.h>
  26. #include <dm/pinctrl.h>
  27. #include <fdtdec.h>
  28. DECLARE_GLOBAL_DATA_PTR;
  29. #define I2C_QUIRK_FLAG (1 << 0)
  30. #define IMX_I2C_REGSHIFT 2
  31. #define VF610_I2C_REGSHIFT 0
  32. #define I2C_EARLY_INIT_INDEX 0
  33. #ifdef CONFIG_SYS_I2C_IFDR_DIV
  34. #define I2C_IFDR_DIV_CONSERVATIVE CONFIG_SYS_I2C_IFDR_DIV
  35. #else
  36. #define I2C_IFDR_DIV_CONSERVATIVE 0x7e
  37. #endif
  38. /* Register index */
  39. #define IADR 0
  40. #define IFDR 1
  41. #define I2CR 2
  42. #define I2SR 3
  43. #define I2DR 4
  44. #define I2CR_IIEN (1 << 6)
  45. #define I2CR_MSTA (1 << 5)
  46. #define I2CR_MTX (1 << 4)
  47. #define I2CR_TX_NO_AK (1 << 3)
  48. #define I2CR_RSTA (1 << 2)
  49. #define I2SR_ICF (1 << 7)
  50. #define I2SR_IBB (1 << 5)
  51. #define I2SR_IAL (1 << 4)
  52. #define I2SR_IIF (1 << 1)
  53. #define I2SR_RX_NO_AK (1 << 0)
  54. #ifdef I2C_QUIRK_REG
  55. #define I2CR_IEN (0 << 7)
  56. #define I2CR_IDIS (1 << 7)
  57. #define I2SR_IIF_CLEAR (1 << 1)
  58. #else
  59. #define I2CR_IEN (1 << 7)
  60. #define I2CR_IDIS (0 << 7)
  61. #define I2SR_IIF_CLEAR (0 << 1)
  62. #endif
  63. #ifdef I2C_QUIRK_REG
  64. static u16 i2c_clk_div[60][2] = {
  65. { 20, 0x00 }, { 22, 0x01 }, { 24, 0x02 }, { 26, 0x03 },
  66. { 28, 0x04 }, { 30, 0x05 }, { 32, 0x09 }, { 34, 0x06 },
  67. { 36, 0x0A }, { 40, 0x07 }, { 44, 0x0C }, { 48, 0x0D },
  68. { 52, 0x43 }, { 56, 0x0E }, { 60, 0x45 }, { 64, 0x12 },
  69. { 68, 0x0F }, { 72, 0x13 }, { 80, 0x14 }, { 88, 0x15 },
  70. { 96, 0x19 }, { 104, 0x16 }, { 112, 0x1A }, { 128, 0x17 },
  71. { 136, 0x4F }, { 144, 0x1C }, { 160, 0x1D }, { 176, 0x55 },
  72. { 192, 0x1E }, { 208, 0x56 }, { 224, 0x22 }, { 228, 0x24 },
  73. { 240, 0x1F }, { 256, 0x23 }, { 288, 0x5C }, { 320, 0x25 },
  74. { 384, 0x26 }, { 448, 0x2A }, { 480, 0x27 }, { 512, 0x2B },
  75. { 576, 0x2C }, { 640, 0x2D }, { 768, 0x31 }, { 896, 0x32 },
  76. { 960, 0x2F }, { 1024, 0x33 }, { 1152, 0x34 }, { 1280, 0x35 },
  77. { 1536, 0x36 }, { 1792, 0x3A }, { 1920, 0x37 }, { 2048, 0x3B },
  78. { 2304, 0x3C }, { 2560, 0x3D }, { 3072, 0x3E }, { 3584, 0x7A },
  79. { 3840, 0x3F }, { 4096, 0x7B }, { 5120, 0x7D }, { 6144, 0x7E },
  80. };
  81. #else
  82. static u16 i2c_clk_div[50][2] = {
  83. { 22, 0x20 }, { 24, 0x21 }, { 26, 0x22 }, { 28, 0x23 },
  84. { 30, 0x00 }, { 32, 0x24 }, { 36, 0x25 }, { 40, 0x26 },
  85. { 42, 0x03 }, { 44, 0x27 }, { 48, 0x28 }, { 52, 0x05 },
  86. { 56, 0x29 }, { 60, 0x06 }, { 64, 0x2A }, { 72, 0x2B },
  87. { 80, 0x2C }, { 88, 0x09 }, { 96, 0x2D }, { 104, 0x0A },
  88. { 112, 0x2E }, { 128, 0x2F }, { 144, 0x0C }, { 160, 0x30 },
  89. { 192, 0x31 }, { 224, 0x32 }, { 240, 0x0F }, { 256, 0x33 },
  90. { 288, 0x10 }, { 320, 0x34 }, { 384, 0x35 }, { 448, 0x36 },
  91. { 480, 0x13 }, { 512, 0x37 }, { 576, 0x14 }, { 640, 0x38 },
  92. { 768, 0x39 }, { 896, 0x3A }, { 960, 0x17 }, { 1024, 0x3B },
  93. { 1152, 0x18 }, { 1280, 0x3C }, { 1536, 0x3D }, { 1792, 0x3E },
  94. { 1920, 0x1B }, { 2048, 0x3F }, { 2304, 0x1C }, { 2560, 0x1D },
  95. { 3072, 0x1E }, { 3840, 0x1F }
  96. };
  97. #endif
  98. #ifndef CONFIG_SYS_MXC_I2C1_SPEED
  99. #define CONFIG_SYS_MXC_I2C1_SPEED 100000
  100. #endif
  101. #ifndef CONFIG_SYS_MXC_I2C2_SPEED
  102. #define CONFIG_SYS_MXC_I2C2_SPEED 100000
  103. #endif
  104. #ifndef CONFIG_SYS_MXC_I2C3_SPEED
  105. #define CONFIG_SYS_MXC_I2C3_SPEED 100000
  106. #endif
  107. #ifndef CONFIG_SYS_MXC_I2C4_SPEED
  108. #define CONFIG_SYS_MXC_I2C4_SPEED 100000
  109. #endif
  110. #ifndef CONFIG_SYS_MXC_I2C1_SLAVE
  111. #define CONFIG_SYS_MXC_I2C1_SLAVE 0
  112. #endif
  113. #ifndef CONFIG_SYS_MXC_I2C2_SLAVE
  114. #define CONFIG_SYS_MXC_I2C2_SLAVE 0
  115. #endif
  116. #ifndef CONFIG_SYS_MXC_I2C3_SLAVE
  117. #define CONFIG_SYS_MXC_I2C3_SLAVE 0
  118. #endif
  119. #ifndef CONFIG_SYS_MXC_I2C4_SLAVE
  120. #define CONFIG_SYS_MXC_I2C4_SLAVE 0
  121. #endif
  122. /*
  123. * Calculate and set proper clock divider
  124. */
  125. static uint8_t i2c_imx_get_clk(struct mxc_i2c_bus *i2c_bus, unsigned int rate)
  126. {
  127. unsigned int i2c_clk_rate;
  128. unsigned int div;
  129. u8 clk_div;
  130. #if defined(CONFIG_MX31)
  131. struct clock_control_regs *sc_regs =
  132. (struct clock_control_regs *)CCM_BASE;
  133. /* start the required I2C clock */
  134. writel(readl(&sc_regs->cgr0) | (3 << CONFIG_SYS_I2C_CLK_OFFSET),
  135. &sc_regs->cgr0);
  136. #endif
  137. /* Divider value calculation */
  138. #if CONFIG_IS_ENABLED(CLK)
  139. i2c_clk_rate = clk_get_rate(&i2c_bus->per_clk);
  140. #else
  141. i2c_clk_rate = mxc_get_clock(MXC_I2C_CLK);
  142. #endif
  143. div = (i2c_clk_rate + rate - 1) / rate;
  144. if (div < i2c_clk_div[0][0])
  145. clk_div = 0;
  146. else if (div > i2c_clk_div[ARRAY_SIZE(i2c_clk_div) - 1][0])
  147. clk_div = ARRAY_SIZE(i2c_clk_div) - 1;
  148. else
  149. for (clk_div = 0; i2c_clk_div[clk_div][0] < div; clk_div++)
  150. ;
  151. /* Store divider value */
  152. return clk_div;
  153. }
  154. /*
  155. * Set I2C Bus speed
  156. */
  157. static int bus_i2c_set_bus_speed(struct mxc_i2c_bus *i2c_bus, int speed)
  158. {
  159. ulong base = i2c_bus->base;
  160. bool quirk = i2c_bus->driver_data & I2C_QUIRK_FLAG ? true : false;
  161. u8 clk_idx = i2c_imx_get_clk(i2c_bus, speed);
  162. u8 idx = i2c_clk_div[clk_idx][1];
  163. int reg_shift = quirk ? VF610_I2C_REGSHIFT : IMX_I2C_REGSHIFT;
  164. if (!base)
  165. return -EINVAL;
  166. /* Store divider value */
  167. writeb(idx, base + (IFDR << reg_shift));
  168. /* Reset module */
  169. writeb(I2CR_IDIS, base + (I2CR << reg_shift));
  170. writeb(0, base + (I2SR << reg_shift));
  171. return 0;
  172. }
  173. #define ST_BUS_IDLE (0 | (I2SR_IBB << 8))
  174. #define ST_BUS_BUSY (I2SR_IBB | (I2SR_IBB << 8))
  175. #define ST_IIF (I2SR_IIF | (I2SR_IIF << 8))
  176. static int wait_for_sr_state(struct mxc_i2c_bus *i2c_bus, unsigned state)
  177. {
  178. unsigned sr;
  179. ulong elapsed;
  180. bool quirk = i2c_bus->driver_data & I2C_QUIRK_FLAG ? true : false;
  181. int reg_shift = quirk ? VF610_I2C_REGSHIFT : IMX_I2C_REGSHIFT;
  182. ulong base = i2c_bus->base;
  183. ulong start_time = get_timer(0);
  184. for (;;) {
  185. sr = readb(base + (I2SR << reg_shift));
  186. if (sr & I2SR_IAL) {
  187. if (quirk)
  188. writeb(sr | I2SR_IAL, base +
  189. (I2SR << reg_shift));
  190. else
  191. writeb(sr & ~I2SR_IAL, base +
  192. (I2SR << reg_shift));
  193. printf("%s: Arbitration lost sr=%x cr=%x state=%x\n",
  194. __func__, sr, readb(base + (I2CR << reg_shift)),
  195. state);
  196. return -ERESTART;
  197. }
  198. if ((sr & (state >> 8)) == (unsigned char)state)
  199. return sr;
  200. WATCHDOG_RESET();
  201. elapsed = get_timer(start_time);
  202. if (elapsed > (CONFIG_SYS_HZ / 10)) /* .1 seconds */
  203. break;
  204. }
  205. printf("%s: failed sr=%x cr=%x state=%x\n", __func__,
  206. sr, readb(base + (I2CR << reg_shift)), state);
  207. return -ETIMEDOUT;
  208. }
  209. static int tx_byte(struct mxc_i2c_bus *i2c_bus, u8 byte)
  210. {
  211. int ret;
  212. int reg_shift = i2c_bus->driver_data & I2C_QUIRK_FLAG ?
  213. VF610_I2C_REGSHIFT : IMX_I2C_REGSHIFT;
  214. ulong base = i2c_bus->base;
  215. writeb(I2SR_IIF_CLEAR, base + (I2SR << reg_shift));
  216. writeb(byte, base + (I2DR << reg_shift));
  217. ret = wait_for_sr_state(i2c_bus, ST_IIF);
  218. if (ret < 0)
  219. return ret;
  220. if (ret & I2SR_RX_NO_AK)
  221. return -EREMOTEIO;
  222. return 0;
  223. }
  224. /*
  225. * Stub implementations for outer i2c slave operations.
  226. */
  227. void __i2c_force_reset_slave(void)
  228. {
  229. }
  230. void i2c_force_reset_slave(void)
  231. __attribute__((weak, alias("__i2c_force_reset_slave")));
  232. /*
  233. * Stop I2C transaction
  234. */
  235. static void i2c_imx_stop(struct mxc_i2c_bus *i2c_bus)
  236. {
  237. int ret;
  238. int reg_shift = i2c_bus->driver_data & I2C_QUIRK_FLAG ?
  239. VF610_I2C_REGSHIFT : IMX_I2C_REGSHIFT;
  240. ulong base = i2c_bus->base;
  241. unsigned int temp = readb(base + (I2CR << reg_shift));
  242. temp &= ~(I2CR_MSTA | I2CR_MTX);
  243. writeb(temp, base + (I2CR << reg_shift));
  244. ret = wait_for_sr_state(i2c_bus, ST_BUS_IDLE);
  245. if (ret < 0)
  246. printf("%s:trigger stop failed\n", __func__);
  247. }
  248. /*
  249. * Send start signal, chip address and
  250. * write register address
  251. */
  252. static int i2c_init_transfer_(struct mxc_i2c_bus *i2c_bus, u8 chip,
  253. u32 addr, int alen)
  254. {
  255. unsigned int temp;
  256. int ret;
  257. bool quirk = i2c_bus->driver_data & I2C_QUIRK_FLAG ? true : false;
  258. ulong base = i2c_bus->base;
  259. int reg_shift = quirk ? VF610_I2C_REGSHIFT : IMX_I2C_REGSHIFT;
  260. /* Reset i2c slave */
  261. i2c_force_reset_slave();
  262. /* Enable I2C controller */
  263. if (quirk)
  264. ret = readb(base + (I2CR << reg_shift)) & I2CR_IDIS;
  265. else
  266. ret = !(readb(base + (I2CR << reg_shift)) & I2CR_IEN);
  267. if (ret) {
  268. writeb(I2CR_IEN, base + (I2CR << reg_shift));
  269. /* Wait for controller to be stable */
  270. udelay(50);
  271. }
  272. if (readb(base + (IADR << reg_shift)) == (chip << 1))
  273. writeb((chip << 1) ^ 2, base + (IADR << reg_shift));
  274. writeb(I2SR_IIF_CLEAR, base + (I2SR << reg_shift));
  275. ret = wait_for_sr_state(i2c_bus, ST_BUS_IDLE);
  276. if (ret < 0)
  277. return ret;
  278. /* Start I2C transaction */
  279. temp = readb(base + (I2CR << reg_shift));
  280. temp |= I2CR_MSTA;
  281. writeb(temp, base + (I2CR << reg_shift));
  282. ret = wait_for_sr_state(i2c_bus, ST_BUS_BUSY);
  283. if (ret < 0)
  284. return ret;
  285. temp |= I2CR_MTX | I2CR_TX_NO_AK;
  286. writeb(temp, base + (I2CR << reg_shift));
  287. if (alen >= 0) {
  288. /* write slave address */
  289. ret = tx_byte(i2c_bus, chip << 1);
  290. if (ret < 0)
  291. return ret;
  292. while (alen--) {
  293. ret = tx_byte(i2c_bus, (addr >> (alen * 8)) & 0xff);
  294. if (ret < 0)
  295. return ret;
  296. }
  297. }
  298. return 0;
  299. }
  300. #ifndef CONFIG_DM_I2C
  301. int i2c_idle_bus(struct mxc_i2c_bus *i2c_bus)
  302. {
  303. if (i2c_bus && i2c_bus->idle_bus_fn)
  304. return i2c_bus->idle_bus_fn(i2c_bus->idle_bus_data);
  305. return 0;
  306. }
  307. #else
  308. /*
  309. * See Linux Documentation/devicetree/bindings/i2c/i2c-imx.txt
  310. * "
  311. * scl-gpios: specify the gpio related to SCL pin
  312. * sda-gpios: specify the gpio related to SDA pin
  313. * add pinctrl to configure i2c pins to gpio function for i2c
  314. * bus recovery, call it "gpio" state
  315. * "
  316. *
  317. * The i2c_idle_bus is an implementation following Linux Kernel.
  318. */
  319. int i2c_idle_bus(struct mxc_i2c_bus *i2c_bus)
  320. {
  321. struct udevice *bus = i2c_bus->bus;
  322. struct dm_i2c_bus *i2c = dev_get_uclass_priv(bus);
  323. struct gpio_desc *scl_gpio = &i2c_bus->scl_gpio;
  324. struct gpio_desc *sda_gpio = &i2c_bus->sda_gpio;
  325. int sda, scl, idle_sclks;
  326. int i, ret = 0;
  327. ulong elapsed, start_time;
  328. if (pinctrl_select_state(bus, "gpio")) {
  329. dev_dbg(bus, "Can not to switch to use gpio pinmux\n");
  330. /*
  331. * GPIO pinctrl for i2c force idle is not a must,
  332. * but it is strongly recommended to be used.
  333. * Because it can help you to recover from bad
  334. * i2c bus state. Do not return failure, because
  335. * it is not a must.
  336. */
  337. return 0;
  338. }
  339. dm_gpio_set_dir_flags(scl_gpio, GPIOD_IS_IN);
  340. dm_gpio_set_dir_flags(sda_gpio, GPIOD_IS_IN);
  341. scl = dm_gpio_get_value(scl_gpio);
  342. sda = dm_gpio_get_value(sda_gpio);
  343. if ((sda & scl) == 1)
  344. goto exit; /* Bus is idle already */
  345. /*
  346. * In most cases it is just enough to generate 8 + 1 SCLK
  347. * clocks to recover I2C slave device from 'stuck' state
  348. * (when for example SW reset was performed, in the middle of
  349. * I2C transmission).
  350. *
  351. * However, there are devices which send data in packets of
  352. * N bytes (N > 1). In such case we do need N * 8 + 1 SCLK
  353. * clocks.
  354. */
  355. idle_sclks = 8 + 1;
  356. if (i2c->max_transaction_bytes > 0)
  357. idle_sclks = i2c->max_transaction_bytes * 8 + 1;
  358. /* Send high and low on the SCL line */
  359. for (i = 0; i < idle_sclks; i++) {
  360. dm_gpio_set_dir_flags(scl_gpio, GPIOD_IS_OUT);
  361. dm_gpio_set_value(scl_gpio, 0);
  362. udelay(50);
  363. dm_gpio_set_dir_flags(scl_gpio, GPIOD_IS_IN);
  364. udelay(50);
  365. }
  366. start_time = get_timer(0);
  367. for (;;) {
  368. dm_gpio_set_dir_flags(scl_gpio, GPIOD_IS_IN);
  369. dm_gpio_set_dir_flags(sda_gpio, GPIOD_IS_IN);
  370. scl = dm_gpio_get_value(scl_gpio);
  371. sda = dm_gpio_get_value(sda_gpio);
  372. if ((sda & scl) == 1)
  373. break;
  374. WATCHDOG_RESET();
  375. elapsed = get_timer(start_time);
  376. if (elapsed > (CONFIG_SYS_HZ / 5)) { /* .2 seconds */
  377. ret = -EBUSY;
  378. printf("%s: failed to clear bus, sda=%d scl=%d\n", __func__, sda, scl);
  379. break;
  380. }
  381. }
  382. exit:
  383. pinctrl_select_state(bus, "default");
  384. return ret;
  385. }
  386. #endif
  387. static int i2c_init_transfer(struct mxc_i2c_bus *i2c_bus, u8 chip,
  388. u32 addr, int alen)
  389. {
  390. int retry;
  391. int ret;
  392. int reg_shift = i2c_bus->driver_data & I2C_QUIRK_FLAG ?
  393. VF610_I2C_REGSHIFT : IMX_I2C_REGSHIFT;
  394. if (!i2c_bus->base)
  395. return -EINVAL;
  396. for (retry = 0; retry < 3; retry++) {
  397. ret = i2c_init_transfer_(i2c_bus, chip, addr, alen);
  398. if (ret >= 0)
  399. return 0;
  400. i2c_imx_stop(i2c_bus);
  401. if (ret == -EREMOTEIO)
  402. return ret;
  403. printf("%s: failed for chip 0x%x retry=%d\n", __func__, chip,
  404. retry);
  405. if (ret != -ERESTART)
  406. /* Disable controller */
  407. writeb(I2CR_IDIS, i2c_bus->base + (I2CR << reg_shift));
  408. udelay(100);
  409. if (i2c_idle_bus(i2c_bus) < 0)
  410. break;
  411. }
  412. printf("%s: give up i2c_regs=0x%lx\n", __func__, i2c_bus->base);
  413. return ret;
  414. }
  415. static int i2c_write_data(struct mxc_i2c_bus *i2c_bus, u8 chip, const u8 *buf,
  416. int len)
  417. {
  418. int i, ret = 0;
  419. debug("i2c_write_data: chip=0x%x, len=0x%x\n", chip, len);
  420. debug("write_data: ");
  421. /* use rc for counter */
  422. for (i = 0; i < len; ++i)
  423. debug(" 0x%02x", buf[i]);
  424. debug("\n");
  425. for (i = 0; i < len; i++) {
  426. ret = tx_byte(i2c_bus, buf[i]);
  427. if (ret < 0) {
  428. debug("i2c_write_data(): rc=%d\n", ret);
  429. break;
  430. }
  431. }
  432. return ret;
  433. }
  434. /* Will generate a STOP after the last byte if "last" is true, i.e. this is the
  435. * final message of a transaction. If not, it switches the bus back to TX mode
  436. * and does not send a STOP, leaving the bus in a state where a repeated start
  437. * and address can be sent for another message.
  438. */
  439. static int i2c_read_data(struct mxc_i2c_bus *i2c_bus, uchar chip, uchar *buf,
  440. int len, bool last)
  441. {
  442. int ret;
  443. unsigned int temp;
  444. int i;
  445. int reg_shift = i2c_bus->driver_data & I2C_QUIRK_FLAG ?
  446. VF610_I2C_REGSHIFT : IMX_I2C_REGSHIFT;
  447. ulong base = i2c_bus->base;
  448. debug("i2c_read_data: chip=0x%x, len=0x%x\n", chip, len);
  449. /* setup bus to read data */
  450. temp = readb(base + (I2CR << reg_shift));
  451. temp &= ~(I2CR_MTX | I2CR_TX_NO_AK);
  452. if (len == 1)
  453. temp |= I2CR_TX_NO_AK;
  454. writeb(temp, base + (I2CR << reg_shift));
  455. writeb(I2SR_IIF_CLEAR, base + (I2SR << reg_shift));
  456. /* dummy read to clear ICF */
  457. readb(base + (I2DR << reg_shift));
  458. /* read data */
  459. for (i = 0; i < len; i++) {
  460. ret = wait_for_sr_state(i2c_bus, ST_IIF);
  461. if (ret < 0) {
  462. debug("i2c_read_data(): ret=%d\n", ret);
  463. i2c_imx_stop(i2c_bus);
  464. return ret;
  465. }
  466. if (i == (len - 1)) {
  467. /* Final byte has already been received by master! When
  468. * we read it from I2DR, the master will start another
  469. * cycle. We must program it first to send a STOP or
  470. * switch to TX to avoid this.
  471. */
  472. if (last) {
  473. i2c_imx_stop(i2c_bus);
  474. } else {
  475. /* Final read, no stop, switch back to tx */
  476. temp = readb(base + (I2CR << reg_shift));
  477. temp |= I2CR_MTX | I2CR_TX_NO_AK;
  478. writeb(temp, base + (I2CR << reg_shift));
  479. }
  480. } else if (i == (len - 2)) {
  481. /* Master has already recevied penultimate byte. When
  482. * we read it from I2DR, master will start RX of final
  483. * byte. We must set TX_NO_AK now so it does not ACK
  484. * that final byte.
  485. */
  486. temp = readb(base + (I2CR << reg_shift));
  487. temp |= I2CR_TX_NO_AK;
  488. writeb(temp, base + (I2CR << reg_shift));
  489. }
  490. writeb(I2SR_IIF_CLEAR, base + (I2SR << reg_shift));
  491. buf[i] = readb(base + (I2DR << reg_shift));
  492. }
  493. /* reuse ret for counter*/
  494. for (ret = 0; ret < len; ++ret)
  495. debug(" 0x%02x", buf[ret]);
  496. debug("\n");
  497. /* It is not clear to me that this is necessary */
  498. if (last)
  499. i2c_imx_stop(i2c_bus);
  500. return 0;
  501. }
  502. int __enable_i2c_clk(unsigned char enable, unsigned int i2c_num)
  503. {
  504. return 1;
  505. }
  506. int enable_i2c_clk(unsigned char enable, unsigned int i2c_num)
  507. __attribute__((weak, alias("__enable_i2c_clk")));
  508. #ifndef CONFIG_DM_I2C
  509. /*
  510. * Read data from I2C device
  511. *
  512. * The transactions use the syntax defined in the Linux kernel I2C docs.
  513. *
  514. * If alen is > 0, then this function will send a transaction of the form:
  515. * S Chip Wr [A] Addr [A] S Chip Rd [A] [data] A ... NA P
  516. * This is a normal I2C register read: writing the register address, then doing
  517. * a repeated start and reading the data.
  518. *
  519. * If alen == 0, then we get this transaction:
  520. * S Chip Wr [A] S Chip Rd [A] [data] A ... NA P
  521. * This is somewhat unusual, though valid, transaction. It addresses the chip
  522. * in write mode, but doesn't actually write any register address or data, then
  523. * does a repeated start and reads data.
  524. *
  525. * If alen < 0, then we get this transaction:
  526. * S Chip Rd [A] [data] A ... NA P
  527. * The chip is addressed in read mode and then data is read. No register
  528. * address is written first. This is perfectly valid on most devices and
  529. * required on some (usually those that don't act like an array of registers).
  530. */
  531. static int bus_i2c_read(struct mxc_i2c_bus *i2c_bus, u8 chip, u32 addr,
  532. int alen, u8 *buf, int len)
  533. {
  534. int ret = 0;
  535. u32 temp;
  536. int reg_shift = i2c_bus->driver_data & I2C_QUIRK_FLAG ?
  537. VF610_I2C_REGSHIFT : IMX_I2C_REGSHIFT;
  538. ulong base = i2c_bus->base;
  539. ret = i2c_init_transfer(i2c_bus, chip, addr, alen);
  540. if (ret < 0)
  541. return ret;
  542. if (alen >= 0) {
  543. temp = readb(base + (I2CR << reg_shift));
  544. temp |= I2CR_RSTA;
  545. writeb(temp, base + (I2CR << reg_shift));
  546. }
  547. ret = tx_byte(i2c_bus, (chip << 1) | 1);
  548. if (ret < 0) {
  549. i2c_imx_stop(i2c_bus);
  550. return ret;
  551. }
  552. ret = i2c_read_data(i2c_bus, chip, buf, len, true);
  553. i2c_imx_stop(i2c_bus);
  554. return ret;
  555. }
  556. /*
  557. * Write data to I2C device
  558. *
  559. * If alen > 0, we get this transaction:
  560. * S Chip Wr [A] addr [A] data [A] ... [A] P
  561. * An ordinary write register command.
  562. *
  563. * If alen == 0, then we get this:
  564. * S Chip Wr [A] data [A] ... [A] P
  565. * This is a simple I2C write.
  566. *
  567. * If alen < 0, then we get this:
  568. * S data [A] ... [A] P
  569. * This is most likely NOT something that should be used. It doesn't send the
  570. * chip address first, so in effect, the first byte of data will be used as the
  571. * address.
  572. */
  573. static int bus_i2c_write(struct mxc_i2c_bus *i2c_bus, u8 chip, u32 addr,
  574. int alen, const u8 *buf, int len)
  575. {
  576. int ret = 0;
  577. ret = i2c_init_transfer(i2c_bus, chip, addr, alen);
  578. if (ret < 0)
  579. return ret;
  580. ret = i2c_write_data(i2c_bus, chip, buf, len);
  581. i2c_imx_stop(i2c_bus);
  582. return ret;
  583. }
  584. #if !defined(I2C2_BASE_ADDR)
  585. #define I2C2_BASE_ADDR 0
  586. #endif
  587. #if !defined(I2C3_BASE_ADDR)
  588. #define I2C3_BASE_ADDR 0
  589. #endif
  590. #if !defined(I2C4_BASE_ADDR)
  591. #define I2C4_BASE_ADDR 0
  592. #endif
  593. #if !defined(I2C5_BASE_ADDR)
  594. #define I2C5_BASE_ADDR 0
  595. #endif
  596. #if !defined(I2C6_BASE_ADDR)
  597. #define I2C6_BASE_ADDR 0
  598. #endif
  599. #if !defined(I2C7_BASE_ADDR)
  600. #define I2C7_BASE_ADDR 0
  601. #endif
  602. #if !defined(I2C8_BASE_ADDR)
  603. #define I2C8_BASE_ADDR 0
  604. #endif
  605. static struct mxc_i2c_bus mxc_i2c_buses[] = {
  606. #if defined(CONFIG_ARCH_LS1021A) || defined(CONFIG_VF610) || \
  607. defined(CONFIG_FSL_LAYERSCAPE)
  608. { 0, I2C1_BASE_ADDR, I2C_QUIRK_FLAG },
  609. { 1, I2C2_BASE_ADDR, I2C_QUIRK_FLAG },
  610. { 2, I2C3_BASE_ADDR, I2C_QUIRK_FLAG },
  611. { 3, I2C4_BASE_ADDR, I2C_QUIRK_FLAG },
  612. { 4, I2C5_BASE_ADDR, I2C_QUIRK_FLAG },
  613. { 5, I2C6_BASE_ADDR, I2C_QUIRK_FLAG },
  614. { 6, I2C7_BASE_ADDR, I2C_QUIRK_FLAG },
  615. { 7, I2C8_BASE_ADDR, I2C_QUIRK_FLAG },
  616. #else
  617. { 0, I2C1_BASE_ADDR, 0 },
  618. { 1, I2C2_BASE_ADDR, 0 },
  619. { 2, I2C3_BASE_ADDR, 0 },
  620. { 3, I2C4_BASE_ADDR, 0 },
  621. { 4, I2C5_BASE_ADDR, 0 },
  622. { 5, I2C6_BASE_ADDR, 0 },
  623. { 6, I2C7_BASE_ADDR, 0 },
  624. { 7, I2C8_BASE_ADDR, 0 },
  625. #endif
  626. };
  627. struct mxc_i2c_bus *i2c_get_base(struct i2c_adapter *adap)
  628. {
  629. return &mxc_i2c_buses[adap->hwadapnr];
  630. }
  631. static int mxc_i2c_read(struct i2c_adapter *adap, uint8_t chip,
  632. uint addr, int alen, uint8_t *buffer,
  633. int len)
  634. {
  635. return bus_i2c_read(i2c_get_base(adap), chip, addr, alen, buffer, len);
  636. }
  637. static int mxc_i2c_write(struct i2c_adapter *adap, uint8_t chip,
  638. uint addr, int alen, uint8_t *buffer,
  639. int len)
  640. {
  641. return bus_i2c_write(i2c_get_base(adap), chip, addr, alen, buffer, len);
  642. }
  643. /*
  644. * Test if a chip at a given address responds (probe the chip)
  645. */
  646. static int mxc_i2c_probe(struct i2c_adapter *adap, uint8_t chip)
  647. {
  648. return bus_i2c_write(i2c_get_base(adap), chip, 0, 0, NULL, 0);
  649. }
  650. void bus_i2c_init(int index, int speed, int unused,
  651. int (*idle_bus_fn)(void *p), void *idle_bus_data)
  652. {
  653. int ret;
  654. if (index >= ARRAY_SIZE(mxc_i2c_buses)) {
  655. debug("Error i2c index\n");
  656. return;
  657. }
  658. if (CONFIG_IS_ENABLED(IMX_MODULE_FUSE)) {
  659. if (i2c_fused((ulong)mxc_i2c_buses[index].base)) {
  660. printf("SoC fuse indicates I2C@0x%lx is unavailable.\n",
  661. (ulong)mxc_i2c_buses[index].base);
  662. return;
  663. }
  664. }
  665. /*
  666. * Warning: Be careful to allow the assignment to a static
  667. * variable here. This function could be called while U-Boot is
  668. * still running in flash memory. So such assignment is equal
  669. * to write data to flash without erasing.
  670. */
  671. if (idle_bus_fn)
  672. mxc_i2c_buses[index].idle_bus_fn = idle_bus_fn;
  673. if (idle_bus_data)
  674. mxc_i2c_buses[index].idle_bus_data = idle_bus_data;
  675. ret = enable_i2c_clk(1, index);
  676. if (ret < 0) {
  677. debug("I2C-%d clk fail to enable.\n", index);
  678. return;
  679. }
  680. bus_i2c_set_bus_speed(&mxc_i2c_buses[index], speed);
  681. }
  682. /*
  683. * Early init I2C for prepare read the clk through I2C.
  684. */
  685. void i2c_early_init_f(void)
  686. {
  687. ulong base = mxc_i2c_buses[I2C_EARLY_INIT_INDEX].base;
  688. bool quirk = mxc_i2c_buses[I2C_EARLY_INIT_INDEX].driver_data
  689. & I2C_QUIRK_FLAG ? true : false;
  690. int reg_shift = quirk ? VF610_I2C_REGSHIFT : IMX_I2C_REGSHIFT;
  691. /* Set I2C divider value */
  692. writeb(I2C_IFDR_DIV_CONSERVATIVE, base + (IFDR << reg_shift));
  693. /* Reset module */
  694. writeb(I2CR_IDIS, base + (I2CR << reg_shift));
  695. writeb(0, base + (I2SR << reg_shift));
  696. /* Enable I2C */
  697. writeb(I2CR_IEN, base + (I2CR << reg_shift));
  698. }
  699. /*
  700. * Init I2C Bus
  701. */
  702. static void mxc_i2c_init(struct i2c_adapter *adap, int speed, int slaveaddr)
  703. {
  704. bus_i2c_init(adap->hwadapnr, speed, slaveaddr, NULL, NULL);
  705. }
  706. /*
  707. * Set I2C Speed
  708. */
  709. static u32 mxc_i2c_set_bus_speed(struct i2c_adapter *adap, uint speed)
  710. {
  711. return bus_i2c_set_bus_speed(i2c_get_base(adap), speed);
  712. }
  713. /*
  714. * Register mxc i2c adapters
  715. */
  716. #ifdef CONFIG_SYS_I2C_MXC_I2C1
  717. U_BOOT_I2C_ADAP_COMPLETE(mxc0, mxc_i2c_init, mxc_i2c_probe,
  718. mxc_i2c_read, mxc_i2c_write,
  719. mxc_i2c_set_bus_speed,
  720. CONFIG_SYS_MXC_I2C1_SPEED,
  721. CONFIG_SYS_MXC_I2C1_SLAVE, 0)
  722. #endif
  723. #ifdef CONFIG_SYS_I2C_MXC_I2C2
  724. U_BOOT_I2C_ADAP_COMPLETE(mxc1, mxc_i2c_init, mxc_i2c_probe,
  725. mxc_i2c_read, mxc_i2c_write,
  726. mxc_i2c_set_bus_speed,
  727. CONFIG_SYS_MXC_I2C2_SPEED,
  728. CONFIG_SYS_MXC_I2C2_SLAVE, 1)
  729. #endif
  730. #ifdef CONFIG_SYS_I2C_MXC_I2C3
  731. U_BOOT_I2C_ADAP_COMPLETE(mxc2, mxc_i2c_init, mxc_i2c_probe,
  732. mxc_i2c_read, mxc_i2c_write,
  733. mxc_i2c_set_bus_speed,
  734. CONFIG_SYS_MXC_I2C3_SPEED,
  735. CONFIG_SYS_MXC_I2C3_SLAVE, 2)
  736. #endif
  737. #ifdef CONFIG_SYS_I2C_MXC_I2C4
  738. U_BOOT_I2C_ADAP_COMPLETE(mxc3, mxc_i2c_init, mxc_i2c_probe,
  739. mxc_i2c_read, mxc_i2c_write,
  740. mxc_i2c_set_bus_speed,
  741. CONFIG_SYS_MXC_I2C4_SPEED,
  742. CONFIG_SYS_MXC_I2C4_SLAVE, 3)
  743. #endif
  744. #ifdef CONFIG_SYS_I2C_MXC_I2C5
  745. U_BOOT_I2C_ADAP_COMPLETE(mxc4, mxc_i2c_init, mxc_i2c_probe,
  746. mxc_i2c_read, mxc_i2c_write,
  747. mxc_i2c_set_bus_speed,
  748. CONFIG_SYS_MXC_I2C5_SPEED,
  749. CONFIG_SYS_MXC_I2C5_SLAVE, 4)
  750. #endif
  751. #ifdef CONFIG_SYS_I2C_MXC_I2C6
  752. U_BOOT_I2C_ADAP_COMPLETE(mxc5, mxc_i2c_init, mxc_i2c_probe,
  753. mxc_i2c_read, mxc_i2c_write,
  754. mxc_i2c_set_bus_speed,
  755. CONFIG_SYS_MXC_I2C6_SPEED,
  756. CONFIG_SYS_MXC_I2C6_SLAVE, 5)
  757. #endif
  758. #ifdef CONFIG_SYS_I2C_MXC_I2C7
  759. U_BOOT_I2C_ADAP_COMPLETE(mxc6, mxc_i2c_init, mxc_i2c_probe,
  760. mxc_i2c_read, mxc_i2c_write,
  761. mxc_i2c_set_bus_speed,
  762. CONFIG_SYS_MXC_I2C7_SPEED,
  763. CONFIG_SYS_MXC_I2C7_SLAVE, 6)
  764. #endif
  765. #ifdef CONFIG_SYS_I2C_MXC_I2C8
  766. U_BOOT_I2C_ADAP_COMPLETE(mxc7, mxc_i2c_init, mxc_i2c_probe,
  767. mxc_i2c_read, mxc_i2c_write,
  768. mxc_i2c_set_bus_speed,
  769. CONFIG_SYS_MXC_I2C8_SPEED,
  770. CONFIG_SYS_MXC_I2C8_SLAVE, 7)
  771. #endif
  772. #else
  773. static int mxc_i2c_set_bus_speed(struct udevice *bus, unsigned int speed)
  774. {
  775. struct mxc_i2c_bus *i2c_bus = dev_get_priv(bus);
  776. return bus_i2c_set_bus_speed(i2c_bus, speed);
  777. }
  778. static int mxc_i2c_probe(struct udevice *bus)
  779. {
  780. struct mxc_i2c_bus *i2c_bus = dev_get_priv(bus);
  781. const void *fdt = gd->fdt_blob;
  782. int node = dev_of_offset(bus);
  783. fdt_addr_t addr;
  784. int ret, ret2;
  785. i2c_bus->driver_data = dev_get_driver_data(bus);
  786. addr = devfdt_get_addr(bus);
  787. if (addr == FDT_ADDR_T_NONE)
  788. return -EINVAL;
  789. if (CONFIG_IS_ENABLED(IMX_MODULE_FUSE)) {
  790. if (i2c_fused((ulong)addr)) {
  791. printf("SoC fuse indicates I2C@0x%lx is unavailable.\n",
  792. (ulong)addr);
  793. return -ENODEV;
  794. }
  795. }
  796. i2c_bus->base = addr;
  797. i2c_bus->index = bus->seq;
  798. i2c_bus->bus = bus;
  799. /* Enable clk */
  800. #if CONFIG_IS_ENABLED(CLK)
  801. ret = clk_get_by_index(bus, 0, &i2c_bus->per_clk);
  802. if (ret) {
  803. printf("Failed to get i2c clk\n");
  804. return ret;
  805. }
  806. ret = clk_enable(&i2c_bus->per_clk);
  807. if (ret) {
  808. printf("Failed to enable i2c clk\n");
  809. return ret;
  810. }
  811. #else
  812. ret = enable_i2c_clk(1, bus->seq);
  813. if (ret < 0)
  814. return ret;
  815. #endif
  816. /*
  817. * See Documentation/devicetree/bindings/i2c/i2c-imx.txt
  818. * Use gpio to force bus idle when necessary.
  819. */
  820. ret = fdt_stringlist_search(fdt, node, "pinctrl-names", "gpio");
  821. if (ret < 0) {
  822. debug("i2c bus %d at 0x%2lx, no gpio pinctrl state.\n", bus->seq, i2c_bus->base);
  823. } else {
  824. ret = gpio_request_by_name_nodev(offset_to_ofnode(node),
  825. "scl-gpios", 0, &i2c_bus->scl_gpio,
  826. GPIOD_IS_OUT);
  827. ret2 = gpio_request_by_name_nodev(offset_to_ofnode(node),
  828. "sda-gpios", 0, &i2c_bus->sda_gpio,
  829. GPIOD_IS_OUT);
  830. if (!dm_gpio_is_valid(&i2c_bus->sda_gpio) ||
  831. !dm_gpio_is_valid(&i2c_bus->scl_gpio) ||
  832. ret || ret2) {
  833. dev_err(dev, "i2c bus %d at %lu, fail to request scl/sda gpio\n", bus->seq, i2c_bus->base);
  834. return -EINVAL;
  835. }
  836. }
  837. /*
  838. * Pinmux settings are in board file now, until pinmux is supported,
  839. * we can set pinmux here in probe function.
  840. */
  841. debug("i2c : controller bus %d at %lu , speed %d: ",
  842. bus->seq, i2c_bus->base,
  843. i2c_bus->speed);
  844. return 0;
  845. }
  846. /* Sends: S Addr Wr [A|NA] P */
  847. static int mxc_i2c_probe_chip(struct udevice *bus, u32 chip_addr,
  848. u32 chip_flags)
  849. {
  850. int ret;
  851. struct mxc_i2c_bus *i2c_bus = dev_get_priv(bus);
  852. ret = i2c_init_transfer(i2c_bus, chip_addr, 0, 0);
  853. if (ret < 0) {
  854. debug("%s failed, ret = %d\n", __func__, ret);
  855. return ret;
  856. }
  857. i2c_imx_stop(i2c_bus);
  858. return 0;
  859. }
  860. static int mxc_i2c_xfer(struct udevice *bus, struct i2c_msg *msg, int nmsgs)
  861. {
  862. struct mxc_i2c_bus *i2c_bus = dev_get_priv(bus);
  863. int ret = 0;
  864. ulong base = i2c_bus->base;
  865. int reg_shift = i2c_bus->driver_data & I2C_QUIRK_FLAG ?
  866. VF610_I2C_REGSHIFT : IMX_I2C_REGSHIFT;
  867. int read_mode;
  868. /* Here address len is set to -1 to not send any address at first.
  869. * Otherwise i2c_init_transfer will send the chip address with write
  870. * mode set. This is wrong if the 1st message is read.
  871. */
  872. ret = i2c_init_transfer(i2c_bus, msg->addr, 0, -1);
  873. if (ret < 0) {
  874. debug("i2c_init_transfer error: %d\n", ret);
  875. return ret;
  876. }
  877. read_mode = -1; /* So it's always different on the first message */
  878. for (; nmsgs > 0; nmsgs--, msg++) {
  879. const int msg_is_read = !!(msg->flags & I2C_M_RD);
  880. debug("i2c_xfer: chip=0x%x, len=0x%x, dir=%c\n", msg->addr,
  881. msg->len, msg_is_read ? 'R' : 'W');
  882. if (msg_is_read != read_mode) {
  883. /* Send repeated start if not 1st message */
  884. if (read_mode != -1) {
  885. debug("i2c_xfer: [RSTART]\n");
  886. ret = readb(base + (I2CR << reg_shift));
  887. ret |= I2CR_RSTA;
  888. writeb(ret, base + (I2CR << reg_shift));
  889. }
  890. debug("i2c_xfer: [ADDR %02x | %c]\n", msg->addr,
  891. msg_is_read ? 'R' : 'W');
  892. ret = tx_byte(i2c_bus, (msg->addr << 1) | msg_is_read);
  893. if (ret < 0) {
  894. debug("i2c_xfer: [STOP]\n");
  895. i2c_imx_stop(i2c_bus);
  896. break;
  897. }
  898. read_mode = msg_is_read;
  899. }
  900. if (msg->flags & I2C_M_RD)
  901. ret = i2c_read_data(i2c_bus, msg->addr, msg->buf,
  902. msg->len, nmsgs == 1 ||
  903. (msg->flags & I2C_M_STOP));
  904. else
  905. ret = i2c_write_data(i2c_bus, msg->addr, msg->buf,
  906. msg->len);
  907. if (ret < 0)
  908. break;
  909. }
  910. if (ret)
  911. debug("i2c_write: error sending\n");
  912. i2c_imx_stop(i2c_bus);
  913. return ret;
  914. }
  915. static const struct dm_i2c_ops mxc_i2c_ops = {
  916. .xfer = mxc_i2c_xfer,
  917. .probe_chip = mxc_i2c_probe_chip,
  918. .set_bus_speed = mxc_i2c_set_bus_speed,
  919. };
  920. static const struct udevice_id mxc_i2c_ids[] = {
  921. { .compatible = "fsl,imx21-i2c", },
  922. { .compatible = "fsl,vf610-i2c", .data = I2C_QUIRK_FLAG, },
  923. {}
  924. };
  925. U_BOOT_DRIVER(i2c_mxc) = {
  926. .name = "i2c_mxc",
  927. .id = UCLASS_I2C,
  928. .of_match = mxc_i2c_ids,
  929. .probe = mxc_i2c_probe,
  930. .priv_auto_alloc_size = sizeof(struct mxc_i2c_bus),
  931. .ops = &mxc_i2c_ops,
  932. .flags = DM_FLAG_PRE_RELOC,
  933. };
  934. #endif