fsl_i2c.c 17 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Copyright 2006,2009 Freescale Semiconductor, Inc.
  4. *
  5. * 2012, Heiko Schocher, DENX Software Engineering, hs@denx.de.
  6. * Changes for multibus/multiadapter I2C support.
  7. */
  8. #include <common.h>
  9. #include <command.h>
  10. #include <i2c.h> /* Functional interface */
  11. #include <time.h>
  12. #include <asm/io.h>
  13. #include <asm/fsl_i2c.h> /* HW definitions */
  14. #include <clk.h>
  15. #include <dm.h>
  16. #include <mapmem.h>
  17. /* The maximum number of microseconds we will wait until another master has
  18. * released the bus. If not defined in the board header file, then use a
  19. * generic value.
  20. */
  21. #ifndef CONFIG_I2C_MBB_TIMEOUT
  22. #define CONFIG_I2C_MBB_TIMEOUT 100000
  23. #endif
  24. /* The maximum number of microseconds we will wait for a read or write
  25. * operation to complete. If not defined in the board header file, then use a
  26. * generic value.
  27. */
  28. #ifndef CONFIG_I2C_TIMEOUT
  29. #define CONFIG_I2C_TIMEOUT 100000
  30. #endif
  31. #define I2C_READ_BIT 1
  32. #define I2C_WRITE_BIT 0
  33. DECLARE_GLOBAL_DATA_PTR;
  34. #ifndef CONFIG_DM_I2C
  35. static const struct fsl_i2c_base *i2c_base[4] = {
  36. (struct fsl_i2c_base *)(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_I2C_OFFSET),
  37. #ifdef CONFIG_SYS_FSL_I2C2_OFFSET
  38. (struct fsl_i2c_base *)(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_I2C2_OFFSET),
  39. #endif
  40. #ifdef CONFIG_SYS_FSL_I2C3_OFFSET
  41. (struct fsl_i2c_base *)(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_I2C3_OFFSET),
  42. #endif
  43. #ifdef CONFIG_SYS_FSL_I2C4_OFFSET
  44. (struct fsl_i2c_base *)(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_I2C4_OFFSET)
  45. #endif
  46. };
  47. #endif
  48. /* I2C speed map for a DFSR value of 1 */
  49. #ifdef __M68K__
  50. /*
  51. * Map I2C frequency dividers to FDR and DFSR values
  52. *
  53. * This structure is used to define the elements of a table that maps I2C
  54. * frequency divider (I2C clock rate divided by I2C bus speed) to a value to be
  55. * programmed into the Frequency Divider Ratio (FDR) and Digital Filter
  56. * Sampling Rate (DFSR) registers.
  57. *
  58. * The actual table should be defined in the board file, and it must be called
  59. * fsl_i2c_speed_map[].
  60. *
  61. * The last entry of the table must have a value of {-1, X}, where X is same
  62. * FDR/DFSR values as the second-to-last entry. This guarantees that any
  63. * search through the array will always find a match.
  64. *
  65. * The values of the divider must be in increasing numerical order, i.e.
  66. * fsl_i2c_speed_map[x+1].divider > fsl_i2c_speed_map[x].divider.
  67. *
  68. * For this table, the values are based on a value of 1 for the DFSR
  69. * register. See the application note AN2919 "Determining the I2C Frequency
  70. * Divider Ratio for SCL"
  71. *
  72. * ColdFire I2C frequency dividers for FDR values are different from
  73. * PowerPC. The protocol to use the I2C module is still the same.
  74. * A different table is defined and are based on MCF5xxx user manual.
  75. *
  76. */
  77. static const struct {
  78. unsigned short divider;
  79. u8 fdr;
  80. } fsl_i2c_speed_map[] = {
  81. {20, 32}, {22, 33}, {24, 34}, {26, 35},
  82. {28, 0}, {28, 36}, {30, 1}, {32, 37},
  83. {34, 2}, {36, 38}, {40, 3}, {40, 39},
  84. {44, 4}, {48, 5}, {48, 40}, {56, 6},
  85. {56, 41}, {64, 42}, {68, 7}, {72, 43},
  86. {80, 8}, {80, 44}, {88, 9}, {96, 41},
  87. {104, 10}, {112, 42}, {128, 11}, {128, 43},
  88. {144, 12}, {160, 13}, {160, 48}, {192, 14},
  89. {192, 49}, {224, 50}, {240, 15}, {256, 51},
  90. {288, 16}, {320, 17}, {320, 52}, {384, 18},
  91. {384, 53}, {448, 54}, {480, 19}, {512, 55},
  92. {576, 20}, {640, 21}, {640, 56}, {768, 22},
  93. {768, 57}, {960, 23}, {896, 58}, {1024, 59},
  94. {1152, 24}, {1280, 25}, {1280, 60}, {1536, 26},
  95. {1536, 61}, {1792, 62}, {1920, 27}, {2048, 63},
  96. {2304, 28}, {2560, 29}, {3072, 30}, {3840, 31},
  97. {-1, 31}
  98. };
  99. #endif
  100. /**
  101. * Set the I2C bus speed for a given I2C device
  102. *
  103. * @param base: the I2C device registers
  104. * @i2c_clk: I2C bus clock frequency
  105. * @speed: the desired speed of the bus
  106. *
  107. * The I2C device must be stopped before calling this function.
  108. *
  109. * The return value is the actual bus speed that is set.
  110. */
  111. static uint set_i2c_bus_speed(const struct fsl_i2c_base *base,
  112. uint i2c_clk, uint speed)
  113. {
  114. ushort divider = min(i2c_clk / speed, (uint)USHRT_MAX);
  115. /*
  116. * We want to choose an FDR/DFSR that generates an I2C bus speed that
  117. * is equal to or lower than the requested speed. That means that we
  118. * want the first divider that is equal to or greater than the
  119. * calculated divider.
  120. */
  121. #ifdef __PPC__
  122. u8 dfsr, fdr = 0x31; /* Default if no FDR found */
  123. /* a, b and dfsr matches identifiers A,B and C respectively in AN2919 */
  124. ushort a, b, ga, gb;
  125. ulong c_div, est_div;
  126. #ifdef CONFIG_FSL_I2C_CUSTOM_DFSR
  127. dfsr = CONFIG_FSL_I2C_CUSTOM_DFSR;
  128. #else
  129. /* Condition 1: dfsr <= 50/T */
  130. dfsr = (5 * (i2c_clk / 1000)) / 100000;
  131. #endif
  132. #ifdef CONFIG_FSL_I2C_CUSTOM_FDR
  133. fdr = CONFIG_FSL_I2C_CUSTOM_FDR;
  134. speed = i2c_clk / divider; /* Fake something */
  135. #else
  136. debug("Requested speed:%d, i2c_clk:%d\n", speed, i2c_clk);
  137. if (!dfsr)
  138. dfsr = 1;
  139. est_div = ~0;
  140. for (ga = 0x4, a = 10; a <= 30; ga++, a += 2) {
  141. for (gb = 0; gb < 8; gb++) {
  142. b = 16 << gb;
  143. c_div = b * (a + ((3 * dfsr) / b) * 2);
  144. if (c_div > divider && c_div < est_div) {
  145. ushort bin_gb, bin_ga;
  146. est_div = c_div;
  147. bin_gb = gb << 2;
  148. bin_ga = (ga & 0x3) | ((ga & 0x4) << 3);
  149. fdr = bin_gb | bin_ga;
  150. speed = i2c_clk / est_div;
  151. debug("FDR: 0x%.2x, ", fdr);
  152. debug("div: %ld, ", est_div);
  153. debug("ga: 0x%x, gb: 0x%x, ", ga, gb);
  154. debug("a: %d, b: %d, speed: %d\n", a, b, speed);
  155. /* Condition 2 not accounted for */
  156. debug("Tr <= %d ns\n",
  157. (b - 3 * dfsr) * 1000000 /
  158. (i2c_clk / 1000));
  159. }
  160. }
  161. if (a == 20)
  162. a += 2;
  163. if (a == 24)
  164. a += 4;
  165. }
  166. debug("divider: %d, est_div: %ld, DFSR: %d\n", divider, est_div, dfsr);
  167. debug("FDR: 0x%.2x, speed: %d\n", fdr, speed);
  168. #endif
  169. writeb(dfsr, &base->dfsrr); /* set default filter */
  170. writeb(fdr, &base->fdr); /* set bus speed */
  171. #else
  172. uint i;
  173. for (i = 0; i < ARRAY_SIZE(fsl_i2c_speed_map); i++)
  174. if (fsl_i2c_speed_map[i].divider >= divider) {
  175. u8 fdr;
  176. fdr = fsl_i2c_speed_map[i].fdr;
  177. speed = i2c_clk / fsl_i2c_speed_map[i].divider;
  178. writeb(fdr, &base->fdr); /* set bus speed */
  179. break;
  180. }
  181. #endif
  182. return speed;
  183. }
  184. #ifndef CONFIG_DM_I2C
  185. static uint get_i2c_clock(int bus)
  186. {
  187. if (bus)
  188. return gd->arch.i2c2_clk; /* I2C2 clock */
  189. else
  190. return gd->arch.i2c1_clk; /* I2C1 clock */
  191. }
  192. #endif
  193. static int fsl_i2c_fixup(const struct fsl_i2c_base *base)
  194. {
  195. const unsigned long long timeout = usec2ticks(CONFIG_I2C_MBB_TIMEOUT);
  196. unsigned long long timeval = 0;
  197. int ret = -1;
  198. uint flags = 0;
  199. #ifdef CONFIG_SYS_FSL_ERRATUM_I2C_A004447
  200. uint svr = get_svr();
  201. if ((SVR_SOC_VER(svr) == SVR_8548 && IS_SVR_REV(svr, 3, 1)) ||
  202. (SVR_REV(svr) <= CONFIG_SYS_FSL_A004447_SVR_REV))
  203. flags = I2C_CR_BIT6;
  204. #endif
  205. writeb(I2C_CR_MEN | I2C_CR_MSTA, &base->cr);
  206. timeval = get_ticks();
  207. while (!(readb(&base->sr) & I2C_SR_MBB)) {
  208. if ((get_ticks() - timeval) > timeout)
  209. goto err;
  210. }
  211. if (readb(&base->sr) & I2C_SR_MAL) {
  212. /* SDA is stuck low */
  213. writeb(0, &base->cr);
  214. udelay(100);
  215. writeb(I2C_CR_MSTA | flags, &base->cr);
  216. writeb(I2C_CR_MEN | I2C_CR_MSTA | flags, &base->cr);
  217. }
  218. readb(&base->dr);
  219. timeval = get_ticks();
  220. while (!(readb(&base->sr) & I2C_SR_MIF)) {
  221. if ((get_ticks() - timeval) > timeout)
  222. goto err;
  223. }
  224. ret = 0;
  225. err:
  226. writeb(I2C_CR_MEN | flags, &base->cr);
  227. writeb(0, &base->sr);
  228. udelay(100);
  229. return ret;
  230. }
  231. static void __i2c_init(const struct fsl_i2c_base *base, int speed, int
  232. slaveadd, int i2c_clk, int busnum)
  233. {
  234. const unsigned long long timeout = usec2ticks(CONFIG_I2C_MBB_TIMEOUT);
  235. unsigned long long timeval;
  236. #ifdef CONFIG_SYS_I2C_INIT_BOARD
  237. /* Call board specific i2c bus reset routine before accessing the
  238. * environment, which might be in a chip on that bus. For details
  239. * about this problem see doc/I2C_Edge_Conditions.
  240. */
  241. i2c_init_board();
  242. #endif
  243. writeb(0, &base->cr); /* stop I2C controller */
  244. udelay(5); /* let it shutdown in peace */
  245. set_i2c_bus_speed(base, i2c_clk, speed);
  246. writeb(slaveadd << 1, &base->adr);/* write slave address */
  247. writeb(0x0, &base->sr); /* clear status register */
  248. writeb(I2C_CR_MEN, &base->cr); /* start I2C controller */
  249. timeval = get_ticks();
  250. while (readb(&base->sr) & I2C_SR_MBB) {
  251. if ((get_ticks() - timeval) < timeout)
  252. continue;
  253. if (fsl_i2c_fixup(base))
  254. debug("i2c_init: BUS#%d failed to init\n",
  255. busnum);
  256. break;
  257. }
  258. }
  259. static int i2c_wait4bus(const struct fsl_i2c_base *base)
  260. {
  261. unsigned long long timeval = get_ticks();
  262. const unsigned long long timeout = usec2ticks(CONFIG_I2C_MBB_TIMEOUT);
  263. while (readb(&base->sr) & I2C_SR_MBB) {
  264. if ((get_ticks() - timeval) > timeout)
  265. return -1;
  266. }
  267. return 0;
  268. }
  269. static int i2c_wait(const struct fsl_i2c_base *base, int write)
  270. {
  271. u32 csr;
  272. unsigned long long timeval = get_ticks();
  273. const unsigned long long timeout = usec2ticks(CONFIG_I2C_TIMEOUT);
  274. do {
  275. csr = readb(&base->sr);
  276. if (!(csr & I2C_SR_MIF))
  277. continue;
  278. /* Read again to allow register to stabilise */
  279. csr = readb(&base->sr);
  280. writeb(0x0, &base->sr);
  281. if (csr & I2C_SR_MAL) {
  282. debug("%s: MAL\n", __func__);
  283. return -1;
  284. }
  285. if (!(csr & I2C_SR_MCF)) {
  286. debug("%s: unfinished\n", __func__);
  287. return -1;
  288. }
  289. if (write == I2C_WRITE_BIT && (csr & I2C_SR_RXAK)) {
  290. debug("%s: No RXACK\n", __func__);
  291. return -1;
  292. }
  293. return 0;
  294. } while ((get_ticks() - timeval) < timeout);
  295. debug("%s: timed out\n", __func__);
  296. return -1;
  297. }
  298. static int i2c_write_addr(const struct fsl_i2c_base *base, u8 dev,
  299. u8 dir, int rsta)
  300. {
  301. writeb(I2C_CR_MEN | I2C_CR_MSTA | I2C_CR_MTX
  302. | (rsta ? I2C_CR_RSTA : 0),
  303. &base->cr);
  304. writeb((dev << 1) | dir, &base->dr);
  305. if (i2c_wait(base, I2C_WRITE_BIT) < 0)
  306. return 0;
  307. return 1;
  308. }
  309. static int __i2c_write_data(const struct fsl_i2c_base *base, u8 *data,
  310. int length)
  311. {
  312. int i;
  313. for (i = 0; i < length; i++) {
  314. writeb(data[i], &base->dr);
  315. if (i2c_wait(base, I2C_WRITE_BIT) < 0)
  316. break;
  317. }
  318. return i;
  319. }
  320. static int __i2c_read_data(const struct fsl_i2c_base *base, u8 *data,
  321. int length)
  322. {
  323. int i;
  324. writeb(I2C_CR_MEN | I2C_CR_MSTA | ((length == 1) ? I2C_CR_TXAK : 0),
  325. &base->cr);
  326. /* dummy read */
  327. readb(&base->dr);
  328. for (i = 0; i < length; i++) {
  329. if (i2c_wait(base, I2C_READ_BIT) < 0)
  330. break;
  331. /* Generate ack on last next to last byte */
  332. if (i == length - 2)
  333. writeb(I2C_CR_MEN | I2C_CR_MSTA | I2C_CR_TXAK,
  334. &base->cr);
  335. /* Do not generate stop on last byte */
  336. if (i == length - 1)
  337. writeb(I2C_CR_MEN | I2C_CR_MSTA | I2C_CR_MTX,
  338. &base->cr);
  339. data[i] = readb(&base->dr);
  340. }
  341. return i;
  342. }
  343. static int __i2c_read(const struct fsl_i2c_base *base, u8 chip_addr, u8 *offset,
  344. int olen, u8 *data, int dlen)
  345. {
  346. int ret = -1; /* signal error */
  347. if (i2c_wait4bus(base) < 0)
  348. return -1;
  349. /* Some drivers use offset lengths in excess of 4 bytes. These drivers
  350. * adhere to the following convention:
  351. * - the offset length is passed as negative (that is, the absolute
  352. * value of olen is the actual offset length)
  353. * - the offset itself is passed in data, which is overwritten by the
  354. * subsequent read operation
  355. */
  356. if (olen < 0) {
  357. if (i2c_write_addr(base, chip_addr, I2C_WRITE_BIT, 0) != 0)
  358. ret = __i2c_write_data(base, data, -olen);
  359. if (ret != -olen)
  360. return -1;
  361. if (dlen && i2c_write_addr(base, chip_addr,
  362. I2C_READ_BIT, 1) != 0)
  363. ret = __i2c_read_data(base, data, dlen);
  364. } else {
  365. if ((!dlen || olen > 0) &&
  366. i2c_write_addr(base, chip_addr, I2C_WRITE_BIT, 0) != 0 &&
  367. __i2c_write_data(base, offset, olen) == olen)
  368. ret = 0; /* No error so far */
  369. if (dlen && i2c_write_addr(base, chip_addr, I2C_READ_BIT,
  370. olen ? 1 : 0) != 0)
  371. ret = __i2c_read_data(base, data, dlen);
  372. }
  373. writeb(I2C_CR_MEN, &base->cr);
  374. if (i2c_wait4bus(base)) /* Wait until STOP */
  375. debug("i2c_read: wait4bus timed out\n");
  376. if (ret == dlen)
  377. return 0;
  378. return -1;
  379. }
  380. static int __i2c_write(const struct fsl_i2c_base *base, u8 chip_addr,
  381. u8 *offset, int olen, u8 *data, int dlen)
  382. {
  383. int ret = -1; /* signal error */
  384. if (i2c_wait4bus(base) < 0)
  385. return -1;
  386. if (i2c_write_addr(base, chip_addr, I2C_WRITE_BIT, 0) != 0 &&
  387. __i2c_write_data(base, offset, olen) == olen) {
  388. ret = __i2c_write_data(base, data, dlen);
  389. }
  390. writeb(I2C_CR_MEN, &base->cr);
  391. if (i2c_wait4bus(base)) /* Wait until STOP */
  392. debug("i2c_write: wait4bus timed out\n");
  393. if (ret == dlen)
  394. return 0;
  395. return -1;
  396. }
  397. static int __i2c_probe_chip(const struct fsl_i2c_base *base, uchar chip)
  398. {
  399. /* For unknown reason the controller will ACK when
  400. * probing for a slave with the same address, so skip
  401. * it.
  402. */
  403. if (chip == (readb(&base->adr) >> 1))
  404. return -1;
  405. return __i2c_read(base, chip, 0, 0, NULL, 0);
  406. }
  407. static uint __i2c_set_bus_speed(const struct fsl_i2c_base *base,
  408. uint speed, int i2c_clk)
  409. {
  410. writeb(0, &base->cr); /* stop controller */
  411. set_i2c_bus_speed(base, i2c_clk, speed);
  412. writeb(I2C_CR_MEN, &base->cr); /* start controller */
  413. return 0;
  414. }
  415. #ifndef CONFIG_DM_I2C
  416. static void fsl_i2c_init(struct i2c_adapter *adap, int speed, int slaveadd)
  417. {
  418. __i2c_init(i2c_base[adap->hwadapnr], speed, slaveadd,
  419. get_i2c_clock(adap->hwadapnr), adap->hwadapnr);
  420. }
  421. static int fsl_i2c_probe_chip(struct i2c_adapter *adap, uchar chip)
  422. {
  423. return __i2c_probe_chip(i2c_base[adap->hwadapnr], chip);
  424. }
  425. static int fsl_i2c_read(struct i2c_adapter *adap, u8 chip_addr, uint offset,
  426. int olen, u8 *data, int dlen)
  427. {
  428. u8 *o = (u8 *)&offset;
  429. return __i2c_read(i2c_base[adap->hwadapnr], chip_addr, &o[4 - olen],
  430. olen, data, dlen);
  431. }
  432. static int fsl_i2c_write(struct i2c_adapter *adap, u8 chip_addr, uint offset,
  433. int olen, u8 *data, int dlen)
  434. {
  435. u8 *o = (u8 *)&offset;
  436. return __i2c_write(i2c_base[adap->hwadapnr], chip_addr, &o[4 - olen],
  437. olen, data, dlen);
  438. }
  439. static uint fsl_i2c_set_bus_speed(struct i2c_adapter *adap, uint speed)
  440. {
  441. return __i2c_set_bus_speed(i2c_base[adap->hwadapnr], speed,
  442. get_i2c_clock(adap->hwadapnr));
  443. }
  444. /*
  445. * Register fsl i2c adapters
  446. */
  447. U_BOOT_I2C_ADAP_COMPLETE(fsl_0, fsl_i2c_init, fsl_i2c_probe_chip, fsl_i2c_read,
  448. fsl_i2c_write, fsl_i2c_set_bus_speed,
  449. CONFIG_SYS_FSL_I2C_SPEED, CONFIG_SYS_FSL_I2C_SLAVE,
  450. 0)
  451. #ifdef CONFIG_SYS_FSL_I2C2_OFFSET
  452. U_BOOT_I2C_ADAP_COMPLETE(fsl_1, fsl_i2c_init, fsl_i2c_probe_chip, fsl_i2c_read,
  453. fsl_i2c_write, fsl_i2c_set_bus_speed,
  454. CONFIG_SYS_FSL_I2C2_SPEED, CONFIG_SYS_FSL_I2C2_SLAVE,
  455. 1)
  456. #endif
  457. #ifdef CONFIG_SYS_FSL_I2C3_OFFSET
  458. U_BOOT_I2C_ADAP_COMPLETE(fsl_2, fsl_i2c_init, fsl_i2c_probe_chip, fsl_i2c_read,
  459. fsl_i2c_write, fsl_i2c_set_bus_speed,
  460. CONFIG_SYS_FSL_I2C3_SPEED, CONFIG_SYS_FSL_I2C3_SLAVE,
  461. 2)
  462. #endif
  463. #ifdef CONFIG_SYS_FSL_I2C4_OFFSET
  464. U_BOOT_I2C_ADAP_COMPLETE(fsl_3, fsl_i2c_init, fsl_i2c_probe_chip, fsl_i2c_read,
  465. fsl_i2c_write, fsl_i2c_set_bus_speed,
  466. CONFIG_SYS_FSL_I2C4_SPEED, CONFIG_SYS_FSL_I2C4_SLAVE,
  467. 3)
  468. #endif
  469. #else /* CONFIG_DM_I2C */
  470. static int fsl_i2c_probe_chip(struct udevice *bus, u32 chip_addr,
  471. u32 chip_flags)
  472. {
  473. struct fsl_i2c_dev *dev = dev_get_priv(bus);
  474. return __i2c_probe_chip(dev->base, chip_addr);
  475. }
  476. static int fsl_i2c_set_bus_speed(struct udevice *bus, uint speed)
  477. {
  478. struct fsl_i2c_dev *dev = dev_get_priv(bus);
  479. return __i2c_set_bus_speed(dev->base, speed, dev->i2c_clk);
  480. }
  481. static int fsl_i2c_ofdata_to_platdata(struct udevice *bus)
  482. {
  483. struct fsl_i2c_dev *dev = dev_get_priv(bus);
  484. struct clk clock;
  485. dev->base = map_sysmem(dev_read_addr(bus), sizeof(struct fsl_i2c_base));
  486. if (!dev->base)
  487. return -ENOMEM;
  488. dev->index = dev_read_u32_default(bus, "cell-index", -1);
  489. dev->slaveadd = dev_read_u32_default(bus, "u-boot,i2c-slave-addr",
  490. 0x7f);
  491. dev->speed = dev_read_u32_default(bus, "clock-frequency",
  492. I2C_SPEED_FAST_RATE);
  493. if (!clk_get_by_index(bus, 0, &clock))
  494. dev->i2c_clk = clk_get_rate(&clock);
  495. else
  496. dev->i2c_clk = dev->index ? gd->arch.i2c2_clk :
  497. gd->arch.i2c1_clk;
  498. return 0;
  499. }
  500. static int fsl_i2c_probe(struct udevice *bus)
  501. {
  502. struct fsl_i2c_dev *dev = dev_get_priv(bus);
  503. __i2c_init(dev->base, dev->speed, dev->slaveadd, dev->i2c_clk,
  504. dev->index);
  505. return 0;
  506. }
  507. static int fsl_i2c_xfer(struct udevice *bus, struct i2c_msg *msg, int nmsgs)
  508. {
  509. struct fsl_i2c_dev *dev = dev_get_priv(bus);
  510. struct i2c_msg *dmsg, *omsg, dummy;
  511. memset(&dummy, 0, sizeof(struct i2c_msg));
  512. /* We expect either two messages (one with an offset and one with the
  513. * actual data) or one message (just data)
  514. */
  515. if (nmsgs > 2 || nmsgs == 0) {
  516. debug("%s: Only one or two messages are supported.", __func__);
  517. return -1;
  518. }
  519. omsg = nmsgs == 1 ? &dummy : msg;
  520. dmsg = nmsgs == 1 ? msg : msg + 1;
  521. if (dmsg->flags & I2C_M_RD)
  522. return __i2c_read(dev->base, dmsg->addr, omsg->buf, omsg->len,
  523. dmsg->buf, dmsg->len);
  524. else
  525. return __i2c_write(dev->base, dmsg->addr, omsg->buf, omsg->len,
  526. dmsg->buf, dmsg->len);
  527. }
  528. static const struct dm_i2c_ops fsl_i2c_ops = {
  529. .xfer = fsl_i2c_xfer,
  530. .probe_chip = fsl_i2c_probe_chip,
  531. .set_bus_speed = fsl_i2c_set_bus_speed,
  532. };
  533. static const struct udevice_id fsl_i2c_ids[] = {
  534. { .compatible = "fsl-i2c", },
  535. { /* sentinel */ }
  536. };
  537. U_BOOT_DRIVER(i2c_fsl) = {
  538. .name = "i2c_fsl",
  539. .id = UCLASS_I2C,
  540. .of_match = fsl_i2c_ids,
  541. .probe = fsl_i2c_probe,
  542. .ofdata_to_platdata = fsl_i2c_ofdata_to_platdata,
  543. .priv_auto_alloc_size = sizeof(struct fsl_i2c_dev),
  544. .ops = &fsl_i2c_ops,
  545. };
  546. #endif /* CONFIG_DM_I2C */