exynos_hs_i2c.c 15 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (c) 2016, Google Inc
  4. *
  5. * (C) Copyright 2002
  6. * David Mueller, ELSOFT AG, d.mueller@elsoft.ch
  7. */
  8. #include <common.h>
  9. #include <dm.h>
  10. #include <i2c.h>
  11. #include <asm/arch/clk.h>
  12. #include <asm/arch/cpu.h>
  13. #include <asm/arch/pinmux.h>
  14. #include "s3c24x0_i2c.h"
  15. DECLARE_GLOBAL_DATA_PTR;
  16. /* HSI2C-specific register description */
  17. /* I2C_CTL Register bits */
  18. #define HSI2C_FUNC_MODE_I2C (1u << 0)
  19. #define HSI2C_MASTER (1u << 3)
  20. #define HSI2C_RXCHON (1u << 6) /* Write/Send */
  21. #define HSI2C_TXCHON (1u << 7) /* Read/Receive */
  22. #define HSI2C_SW_RST (1u << 31)
  23. /* I2C_FIFO_CTL Register bits */
  24. #define HSI2C_RXFIFO_EN (1u << 0)
  25. #define HSI2C_TXFIFO_EN (1u << 1)
  26. #define HSI2C_TXFIFO_TRIGGER_LEVEL (0x20 << 16)
  27. #define HSI2C_RXFIFO_TRIGGER_LEVEL (0x20 << 4)
  28. /* I2C_TRAILING_CTL Register bits */
  29. #define HSI2C_TRAILING_COUNT (0xff)
  30. /* I2C_INT_EN Register bits */
  31. #define HSI2C_TX_UNDERRUN_EN (1u << 2)
  32. #define HSI2C_TX_OVERRUN_EN (1u << 3)
  33. #define HSI2C_RX_UNDERRUN_EN (1u << 4)
  34. #define HSI2C_RX_OVERRUN_EN (1u << 5)
  35. #define HSI2C_INT_TRAILING_EN (1u << 6)
  36. #define HSI2C_INT_I2C_EN (1u << 9)
  37. #define HSI2C_INT_ERROR_MASK (HSI2C_TX_UNDERRUN_EN |\
  38. HSI2C_TX_OVERRUN_EN |\
  39. HSI2C_RX_UNDERRUN_EN |\
  40. HSI2C_RX_OVERRUN_EN |\
  41. HSI2C_INT_TRAILING_EN)
  42. /* I2C_CONF Register bits */
  43. #define HSI2C_AUTO_MODE (1u << 31)
  44. #define HSI2C_10BIT_ADDR_MODE (1u << 30)
  45. #define HSI2C_HS_MODE (1u << 29)
  46. /* I2C_AUTO_CONF Register bits */
  47. #define HSI2C_READ_WRITE (1u << 16)
  48. #define HSI2C_STOP_AFTER_TRANS (1u << 17)
  49. #define HSI2C_MASTER_RUN (1u << 31)
  50. /* I2C_TIMEOUT Register bits */
  51. #define HSI2C_TIMEOUT_EN (1u << 31)
  52. /* I2C_TRANS_STATUS register bits */
  53. #define HSI2C_MASTER_BUSY (1u << 17)
  54. #define HSI2C_SLAVE_BUSY (1u << 16)
  55. #define HSI2C_TIMEOUT_AUTO (1u << 4)
  56. #define HSI2C_NO_DEV (1u << 3)
  57. #define HSI2C_NO_DEV_ACK (1u << 2)
  58. #define HSI2C_TRANS_ABORT (1u << 1)
  59. #define HSI2C_TRANS_SUCCESS (1u << 0)
  60. #define HSI2C_TRANS_ERROR_MASK (HSI2C_TIMEOUT_AUTO |\
  61. HSI2C_NO_DEV | HSI2C_NO_DEV_ACK |\
  62. HSI2C_TRANS_ABORT)
  63. #define HSI2C_TRANS_FINISHED_MASK (HSI2C_TRANS_ERROR_MASK | HSI2C_TRANS_SUCCESS)
  64. /* I2C_FIFO_STAT Register bits */
  65. #define HSI2C_RX_FIFO_EMPTY (1u << 24)
  66. #define HSI2C_RX_FIFO_FULL (1u << 23)
  67. #define HSI2C_TX_FIFO_EMPTY (1u << 8)
  68. #define HSI2C_TX_FIFO_FULL (1u << 7)
  69. #define HSI2C_RX_FIFO_LEVEL(x) (((x) >> 16) & 0x7f)
  70. #define HSI2C_TX_FIFO_LEVEL(x) ((x) & 0x7f)
  71. #define HSI2C_SLV_ADDR_MAS(x) ((x & 0x3ff) << 10)
  72. #define HSI2C_TIMEOUT_US 10000 /* 10 ms, finer granularity */
  73. /*
  74. * Wait for transfer completion.
  75. *
  76. * This function reads the interrupt status register waiting for the INT_I2C
  77. * bit to be set, which indicates copletion of a transaction.
  78. *
  79. * @param i2c: pointer to the appropriate register bank
  80. *
  81. * @return: I2C_OK in case of successful completion, I2C_NOK_TIMEOUT in case
  82. * the status bits do not get set in time, or an approrpiate error
  83. * value in case of transfer errors.
  84. */
  85. static int hsi2c_wait_for_trx(struct exynos5_hsi2c *i2c)
  86. {
  87. int i = HSI2C_TIMEOUT_US;
  88. while (i-- > 0) {
  89. u32 int_status = readl(&i2c->usi_int_stat);
  90. if (int_status & HSI2C_INT_I2C_EN) {
  91. u32 trans_status = readl(&i2c->usi_trans_status);
  92. /* Deassert pending interrupt. */
  93. writel(int_status, &i2c->usi_int_stat);
  94. if (trans_status & HSI2C_NO_DEV_ACK) {
  95. debug("%s: no ACK from device\n", __func__);
  96. return I2C_NACK;
  97. }
  98. if (trans_status & HSI2C_NO_DEV) {
  99. debug("%s: no device\n", __func__);
  100. return I2C_NOK;
  101. }
  102. if (trans_status & HSI2C_TRANS_ABORT) {
  103. debug("%s: arbitration lost\n", __func__);
  104. return I2C_NOK_LA;
  105. }
  106. if (trans_status & HSI2C_TIMEOUT_AUTO) {
  107. debug("%s: device timed out\n", __func__);
  108. return I2C_NOK_TOUT;
  109. }
  110. return I2C_OK;
  111. }
  112. udelay(1);
  113. }
  114. debug("%s: transaction timeout!\n", __func__);
  115. return I2C_NOK_TOUT;
  116. }
  117. static int hsi2c_get_clk_details(struct s3c24x0_i2c_bus *i2c_bus)
  118. {
  119. struct exynos5_hsi2c *hsregs = i2c_bus->hsregs;
  120. ulong clkin;
  121. unsigned int op_clk = i2c_bus->clock_frequency;
  122. unsigned int i = 0, utemp0 = 0, utemp1 = 0;
  123. unsigned int t_ftl_cycle;
  124. #if (defined CONFIG_EXYNOS4 || defined CONFIG_EXYNOS5)
  125. clkin = get_i2c_clk();
  126. #else
  127. clkin = get_PCLK();
  128. #endif
  129. /* FPCLK / FI2C =
  130. * (CLK_DIV + 1) * (TSCLK_L + TSCLK_H + 2) + 8 + 2 * FLT_CYCLE
  131. * uTemp0 = (CLK_DIV + 1) * (TSCLK_L + TSCLK_H + 2)
  132. * uTemp1 = (TSCLK_L + TSCLK_H + 2)
  133. * uTemp2 = TSCLK_L + TSCLK_H
  134. */
  135. t_ftl_cycle = (readl(&hsregs->usi_conf) >> 16) & 0x7;
  136. utemp0 = (clkin / op_clk) - 8 - 2 * t_ftl_cycle;
  137. /* CLK_DIV max is 256 */
  138. for (i = 0; i < 256; i++) {
  139. utemp1 = utemp0 / (i + 1);
  140. if ((utemp1 < 512) && (utemp1 > 4)) {
  141. i2c_bus->clk_cycle = utemp1 - 2;
  142. i2c_bus->clk_div = i;
  143. return 0;
  144. }
  145. }
  146. return -EINVAL;
  147. }
  148. static void hsi2c_ch_init(struct s3c24x0_i2c_bus *i2c_bus)
  149. {
  150. struct exynos5_hsi2c *hsregs = i2c_bus->hsregs;
  151. unsigned int t_sr_release;
  152. unsigned int n_clkdiv;
  153. unsigned int t_start_su, t_start_hd;
  154. unsigned int t_stop_su;
  155. unsigned int t_data_su, t_data_hd;
  156. unsigned int t_scl_l, t_scl_h;
  157. u32 i2c_timing_s1;
  158. u32 i2c_timing_s2;
  159. u32 i2c_timing_s3;
  160. u32 i2c_timing_sla;
  161. n_clkdiv = i2c_bus->clk_div;
  162. t_scl_l = i2c_bus->clk_cycle / 2;
  163. t_scl_h = i2c_bus->clk_cycle / 2;
  164. t_start_su = t_scl_l;
  165. t_start_hd = t_scl_l;
  166. t_stop_su = t_scl_l;
  167. t_data_su = t_scl_l / 2;
  168. t_data_hd = t_scl_l / 2;
  169. t_sr_release = i2c_bus->clk_cycle;
  170. i2c_timing_s1 = t_start_su << 24 | t_start_hd << 16 | t_stop_su << 8;
  171. i2c_timing_s2 = t_data_su << 24 | t_scl_l << 8 | t_scl_h << 0;
  172. i2c_timing_s3 = n_clkdiv << 16 | t_sr_release << 0;
  173. i2c_timing_sla = t_data_hd << 0;
  174. writel(HSI2C_TRAILING_COUNT, &hsregs->usi_trailing_ctl);
  175. /* Clear to enable Timeout */
  176. clrsetbits_le32(&hsregs->usi_timeout, HSI2C_TIMEOUT_EN, 0);
  177. /* set AUTO mode */
  178. writel(readl(&hsregs->usi_conf) | HSI2C_AUTO_MODE, &hsregs->usi_conf);
  179. /* Enable completion conditions' reporting. */
  180. writel(HSI2C_INT_I2C_EN, &hsregs->usi_int_en);
  181. /* Enable FIFOs */
  182. writel(HSI2C_RXFIFO_EN | HSI2C_TXFIFO_EN, &hsregs->usi_fifo_ctl);
  183. /* Currently operating in Fast speed mode. */
  184. writel(i2c_timing_s1, &hsregs->usi_timing_fs1);
  185. writel(i2c_timing_s2, &hsregs->usi_timing_fs2);
  186. writel(i2c_timing_s3, &hsregs->usi_timing_fs3);
  187. writel(i2c_timing_sla, &hsregs->usi_timing_sla);
  188. }
  189. /* SW reset for the high speed bus */
  190. static void exynos5_i2c_reset(struct s3c24x0_i2c_bus *i2c_bus)
  191. {
  192. struct exynos5_hsi2c *i2c = i2c_bus->hsregs;
  193. u32 i2c_ctl;
  194. /* Set and clear the bit for reset */
  195. i2c_ctl = readl(&i2c->usi_ctl);
  196. i2c_ctl |= HSI2C_SW_RST;
  197. writel(i2c_ctl, &i2c->usi_ctl);
  198. i2c_ctl = readl(&i2c->usi_ctl);
  199. i2c_ctl &= ~HSI2C_SW_RST;
  200. writel(i2c_ctl, &i2c->usi_ctl);
  201. /* Initialize the configure registers */
  202. hsi2c_ch_init(i2c_bus);
  203. }
  204. /*
  205. * Poll the appropriate bit of the fifo status register until the interface is
  206. * ready to process the next byte or timeout expires.
  207. *
  208. * In addition to the FIFO status register this function also polls the
  209. * interrupt status register to be able to detect unexpected transaction
  210. * completion.
  211. *
  212. * When FIFO is ready to process the next byte, this function returns I2C_OK.
  213. * If in course of polling the INT_I2C assertion is detected, the function
  214. * returns I2C_NOK. If timeout happens before any of the above conditions is
  215. * met - the function returns I2C_NOK_TOUT;
  216. * @param i2c: pointer to the appropriate i2c register bank.
  217. * @param rx_transfer: set to True if the receive transaction is in progress.
  218. * @return: as described above.
  219. */
  220. static unsigned hsi2c_poll_fifo(struct exynos5_hsi2c *i2c, bool rx_transfer)
  221. {
  222. u32 fifo_bit = rx_transfer ? HSI2C_RX_FIFO_EMPTY : HSI2C_TX_FIFO_FULL;
  223. int i = HSI2C_TIMEOUT_US;
  224. while (readl(&i2c->usi_fifo_stat) & fifo_bit) {
  225. if (readl(&i2c->usi_int_stat) & HSI2C_INT_I2C_EN) {
  226. /*
  227. * There is a chance that assertion of
  228. * HSI2C_INT_I2C_EN and deassertion of
  229. * HSI2C_RX_FIFO_EMPTY happen simultaneously. Let's
  230. * give FIFO status priority and check it one more
  231. * time before reporting interrupt. The interrupt will
  232. * be reported next time this function is called.
  233. */
  234. if (rx_transfer &&
  235. !(readl(&i2c->usi_fifo_stat) & fifo_bit))
  236. break;
  237. return I2C_NOK;
  238. }
  239. if (!i--) {
  240. debug("%s: FIFO polling timeout!\n", __func__);
  241. return I2C_NOK_TOUT;
  242. }
  243. udelay(1);
  244. }
  245. return I2C_OK;
  246. }
  247. /*
  248. * Preapre hsi2c transaction, either read or write.
  249. *
  250. * Set up transfer as described in section 27.5.1.2 'I2C Channel Auto Mode' of
  251. * the 5420 UM.
  252. *
  253. * @param i2c: pointer to the appropriate i2c register bank.
  254. * @param chip: slave address on the i2c bus (with read/write bit exlcuded)
  255. * @param len: number of bytes expected to be sent or received
  256. * @param rx_transfer: set to true for receive transactions
  257. * @param: issue_stop: set to true if i2c stop condition should be generated
  258. * after this transaction.
  259. * @return: I2C_NOK_TOUT in case the bus remained busy for HSI2C_TIMEOUT_US,
  260. * I2C_OK otherwise.
  261. */
  262. static int hsi2c_prepare_transaction(struct exynos5_hsi2c *i2c,
  263. u8 chip,
  264. u16 len,
  265. bool rx_transfer,
  266. bool issue_stop)
  267. {
  268. u32 conf;
  269. conf = len | HSI2C_MASTER_RUN;
  270. if (issue_stop)
  271. conf |= HSI2C_STOP_AFTER_TRANS;
  272. /* Clear to enable Timeout */
  273. writel(readl(&i2c->usi_timeout) & ~HSI2C_TIMEOUT_EN, &i2c->usi_timeout);
  274. /* Set slave address */
  275. writel(HSI2C_SLV_ADDR_MAS(chip), &i2c->i2c_addr);
  276. if (rx_transfer) {
  277. /* i2c master, read transaction */
  278. writel((HSI2C_RXCHON | HSI2C_FUNC_MODE_I2C | HSI2C_MASTER),
  279. &i2c->usi_ctl);
  280. /* read up to len bytes, stop after transaction is finished */
  281. writel(conf | HSI2C_READ_WRITE, &i2c->usi_auto_conf);
  282. } else {
  283. /* i2c master, write transaction */
  284. writel((HSI2C_TXCHON | HSI2C_FUNC_MODE_I2C | HSI2C_MASTER),
  285. &i2c->usi_ctl);
  286. /* write up to len bytes, stop after transaction is finished */
  287. writel(conf, &i2c->usi_auto_conf);
  288. }
  289. /* Reset all pending interrupt status bits we care about, if any */
  290. writel(HSI2C_INT_I2C_EN, &i2c->usi_int_stat);
  291. return I2C_OK;
  292. }
  293. /*
  294. * Wait while i2c bus is settling down (mostly stop gets completed).
  295. */
  296. static int hsi2c_wait_while_busy(struct exynos5_hsi2c *i2c)
  297. {
  298. int i = HSI2C_TIMEOUT_US;
  299. while (readl(&i2c->usi_trans_status) & HSI2C_MASTER_BUSY) {
  300. if (!i--) {
  301. debug("%s: bus busy\n", __func__);
  302. return I2C_NOK_TOUT;
  303. }
  304. udelay(1);
  305. }
  306. return I2C_OK;
  307. }
  308. static int hsi2c_write(struct exynos5_hsi2c *i2c,
  309. unsigned char chip,
  310. unsigned char addr[],
  311. unsigned char alen,
  312. unsigned char data[],
  313. unsigned short len,
  314. bool issue_stop)
  315. {
  316. int i, rv = 0;
  317. if (!(len + alen)) {
  318. /* Writes of zero length not supported in auto mode. */
  319. debug("%s: zero length writes not supported\n", __func__);
  320. return I2C_NOK;
  321. }
  322. rv = hsi2c_prepare_transaction
  323. (i2c, chip, len + alen, false, issue_stop);
  324. if (rv != I2C_OK)
  325. return rv;
  326. /* Move address, if any, and the data, if any, into the FIFO. */
  327. for (i = 0; i < alen; i++) {
  328. rv = hsi2c_poll_fifo(i2c, false);
  329. if (rv != I2C_OK) {
  330. debug("%s: address write failed\n", __func__);
  331. goto write_error;
  332. }
  333. writel(addr[i], &i2c->usi_txdata);
  334. }
  335. for (i = 0; i < len; i++) {
  336. rv = hsi2c_poll_fifo(i2c, false);
  337. if (rv != I2C_OK) {
  338. debug("%s: data write failed\n", __func__);
  339. goto write_error;
  340. }
  341. writel(data[i], &i2c->usi_txdata);
  342. }
  343. rv = hsi2c_wait_for_trx(i2c);
  344. write_error:
  345. if (issue_stop) {
  346. int tmp_ret = hsi2c_wait_while_busy(i2c);
  347. if (rv == I2C_OK)
  348. rv = tmp_ret;
  349. }
  350. writel(HSI2C_FUNC_MODE_I2C, &i2c->usi_ctl); /* done */
  351. return rv;
  352. }
  353. static int hsi2c_read(struct exynos5_hsi2c *i2c,
  354. unsigned char chip,
  355. unsigned char addr[],
  356. unsigned char alen,
  357. unsigned char data[],
  358. unsigned short len)
  359. {
  360. int i, rv, tmp_ret;
  361. bool drop_data = false;
  362. if (!len) {
  363. /* Reads of zero length not supported in auto mode. */
  364. debug("%s: zero length read adjusted\n", __func__);
  365. drop_data = true;
  366. len = 1;
  367. }
  368. if (alen) {
  369. /* Internal register adress needs to be written first. */
  370. rv = hsi2c_write(i2c, chip, addr, alen, NULL, 0, false);
  371. if (rv != I2C_OK)
  372. return rv;
  373. }
  374. rv = hsi2c_prepare_transaction(i2c, chip, len, true, true);
  375. if (rv != I2C_OK)
  376. return rv;
  377. for (i = 0; i < len; i++) {
  378. rv = hsi2c_poll_fifo(i2c, true);
  379. if (rv != I2C_OK)
  380. goto read_err;
  381. if (drop_data)
  382. continue;
  383. data[i] = readl(&i2c->usi_rxdata);
  384. }
  385. rv = hsi2c_wait_for_trx(i2c);
  386. read_err:
  387. tmp_ret = hsi2c_wait_while_busy(i2c);
  388. if (rv == I2C_OK)
  389. rv = tmp_ret;
  390. writel(HSI2C_FUNC_MODE_I2C, &i2c->usi_ctl); /* done */
  391. return rv;
  392. }
  393. static int exynos_hs_i2c_xfer(struct udevice *dev, struct i2c_msg *msg,
  394. int nmsgs)
  395. {
  396. struct s3c24x0_i2c_bus *i2c_bus = dev_get_priv(dev);
  397. struct exynos5_hsi2c *hsregs = i2c_bus->hsregs;
  398. int ret;
  399. for (; nmsgs > 0; nmsgs--, msg++) {
  400. if (msg->flags & I2C_M_RD) {
  401. ret = hsi2c_read(hsregs, msg->addr, 0, 0, msg->buf,
  402. msg->len);
  403. } else {
  404. ret = hsi2c_write(hsregs, msg->addr, 0, 0, msg->buf,
  405. msg->len, true);
  406. }
  407. if (ret) {
  408. exynos5_i2c_reset(i2c_bus);
  409. return -EREMOTEIO;
  410. }
  411. }
  412. return 0;
  413. }
  414. static int s3c24x0_i2c_set_bus_speed(struct udevice *dev, unsigned int speed)
  415. {
  416. struct s3c24x0_i2c_bus *i2c_bus = dev_get_priv(dev);
  417. i2c_bus->clock_frequency = speed;
  418. if (hsi2c_get_clk_details(i2c_bus))
  419. return -EFAULT;
  420. hsi2c_ch_init(i2c_bus);
  421. return 0;
  422. }
  423. static int s3c24x0_i2c_probe(struct udevice *dev, uint chip, uint chip_flags)
  424. {
  425. struct s3c24x0_i2c_bus *i2c_bus = dev_get_priv(dev);
  426. uchar buf[1];
  427. int ret;
  428. buf[0] = 0;
  429. /*
  430. * What is needed is to send the chip address and verify that the
  431. * address was <ACK>ed (i.e. there was a chip at that address which
  432. * drove the data line low).
  433. */
  434. ret = hsi2c_read(i2c_bus->hsregs, chip, 0, 0, buf, 1);
  435. return ret != I2C_OK;
  436. }
  437. static int s3c_i2c_ofdata_to_platdata(struct udevice *dev)
  438. {
  439. const void *blob = gd->fdt_blob;
  440. struct s3c24x0_i2c_bus *i2c_bus = dev_get_priv(dev);
  441. int node;
  442. node = dev_of_offset(dev);
  443. i2c_bus->hsregs = (struct exynos5_hsi2c *)devfdt_get_addr(dev);
  444. i2c_bus->id = pinmux_decode_periph_id(blob, node);
  445. i2c_bus->clock_frequency =
  446. dev_read_u32_default(dev, "clock-frequency",
  447. I2C_SPEED_STANDARD_RATE);
  448. i2c_bus->node = node;
  449. i2c_bus->bus_num = dev->seq;
  450. exynos_pinmux_config(i2c_bus->id, PINMUX_FLAG_HS_MODE);
  451. i2c_bus->active = true;
  452. return 0;
  453. }
  454. static const struct dm_i2c_ops exynos_hs_i2c_ops = {
  455. .xfer = exynos_hs_i2c_xfer,
  456. .probe_chip = s3c24x0_i2c_probe,
  457. .set_bus_speed = s3c24x0_i2c_set_bus_speed,
  458. };
  459. static const struct udevice_id exynos_hs_i2c_ids[] = {
  460. { .compatible = "samsung,exynos5-hsi2c" },
  461. { }
  462. };
  463. U_BOOT_DRIVER(hs_i2c) = {
  464. .name = "i2c_s3c_hs",
  465. .id = UCLASS_I2C,
  466. .of_match = exynos_hs_i2c_ids,
  467. .ofdata_to_platdata = s3c_i2c_ofdata_to_platdata,
  468. .priv_auto_alloc_size = sizeof(struct s3c24x0_i2c_bus),
  469. .ops = &exynos_hs_i2c_ops,
  470. };