designware_i2c_pci.c 4.0 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2009
  4. * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com.
  5. * Copyright 2019 Google Inc
  6. */
  7. #include <common.h>
  8. #include <dm.h>
  9. #include <spl.h>
  10. #include <asm/lpss.h>
  11. #include "designware_i2c.h"
  12. enum {
  13. VANILLA = 0, /* standard I2C with no tweaks */
  14. INTEL_APL, /* Apollo Lake I2C */
  15. };
  16. /* BayTrail HCNT/LCNT/SDA hold time */
  17. static struct dw_scl_sda_cfg byt_config = {
  18. .ss_hcnt = 0x200,
  19. .fs_hcnt = 0x55,
  20. .ss_lcnt = 0x200,
  21. .fs_lcnt = 0x99,
  22. .sda_hold = 0x6,
  23. };
  24. /* Have a weak function for now - possibly should be a new uclass */
  25. __weak void lpss_reset_release(void *regs);
  26. static int designware_i2c_pci_ofdata_to_platdata(struct udevice *dev)
  27. {
  28. struct dw_i2c *priv = dev_get_priv(dev);
  29. if (spl_phase() < PHASE_SPL) {
  30. u32 base;
  31. int ret;
  32. ret = dev_read_u32(dev, "early-regs", &base);
  33. if (ret)
  34. return log_msg_ret("early-regs", ret);
  35. /* Set i2c base address */
  36. dm_pci_write_config32(dev, PCI_BASE_ADDRESS_0, base);
  37. /* Enable memory access and bus master */
  38. dm_pci_write_config32(dev, PCI_COMMAND, PCI_COMMAND_MEMORY |
  39. PCI_COMMAND_MASTER);
  40. }
  41. if (spl_phase() < PHASE_BOARD_F) {
  42. /* Handle early, fixed mapping into a different address space */
  43. priv->regs = (struct i2c_regs *)dm_pci_read_bar32(dev, 0);
  44. } else {
  45. priv->regs = (struct i2c_regs *)
  46. dm_pci_map_bar(dev, PCI_BASE_ADDRESS_0, PCI_REGION_MEM);
  47. }
  48. if (!priv->regs)
  49. return -EINVAL;
  50. /* Save base address from PCI BAR */
  51. if (IS_ENABLED(CONFIG_INTEL_BAYTRAIL))
  52. /* Use BayTrail specific timing values */
  53. priv->scl_sda_cfg = &byt_config;
  54. if (dev_get_driver_data(dev) == INTEL_APL)
  55. priv->has_spk_cnt = true;
  56. return designware_i2c_ofdata_to_platdata(dev);
  57. }
  58. static int designware_i2c_pci_probe(struct udevice *dev)
  59. {
  60. struct dw_i2c *priv = dev_get_priv(dev);
  61. if (dev_get_driver_data(dev) == INTEL_APL) {
  62. /* Ensure controller is in D0 state */
  63. lpss_set_power_state(dev, STATE_D0);
  64. lpss_reset_release(priv->regs);
  65. }
  66. return designware_i2c_probe(dev);
  67. }
  68. static int designware_i2c_pci_bind(struct udevice *dev)
  69. {
  70. char name[20];
  71. /*
  72. * Create a unique device name for PCI type devices
  73. * ToDo:
  74. * Setting req_seq in the driver is probably not recommended.
  75. * But without a DT alias the number is not configured. And
  76. * using this driver is impossible for PCIe I2C devices.
  77. * This can be removed, once a better (correct) way for this
  78. * is found and implemented.
  79. *
  80. * TODO(sjg@chromium.org): Perhaps if uclasses had platdata this would
  81. * be possible. We cannot use static data in drivers since they may be
  82. * used in SPL or before relocation.
  83. */
  84. dev->req_seq = gd->arch.dw_i2c_num_cards++;
  85. sprintf(name, "i2c_designware#%u", dev->req_seq);
  86. device_set_name(dev, name);
  87. return 0;
  88. }
  89. static const struct udevice_id designware_i2c_pci_ids[] = {
  90. { .compatible = "snps,designware-i2c-pci" },
  91. { .compatible = "intel,apl-i2c", .data = INTEL_APL },
  92. { }
  93. };
  94. U_BOOT_DRIVER(i2c_designware_pci) = {
  95. .name = "i2c_designware_pci",
  96. .id = UCLASS_I2C,
  97. .of_match = designware_i2c_pci_ids,
  98. .bind = designware_i2c_pci_bind,
  99. .ofdata_to_platdata = designware_i2c_pci_ofdata_to_platdata,
  100. .probe = designware_i2c_pci_probe,
  101. .priv_auto_alloc_size = sizeof(struct dw_i2c),
  102. .remove = designware_i2c_remove,
  103. .flags = DM_FLAG_OS_PREPARE,
  104. .ops = &designware_i2c_ops,
  105. };
  106. static struct pci_device_id designware_pci_supported[] = {
  107. /* Intel BayTrail has 7 I2C controller located on the PCI bus */
  108. { PCI_VDEVICE(INTEL, 0x0f41) },
  109. { PCI_VDEVICE(INTEL, 0x0f42) },
  110. { PCI_VDEVICE(INTEL, 0x0f43) },
  111. { PCI_VDEVICE(INTEL, 0x0f44) },
  112. { PCI_VDEVICE(INTEL, 0x0f45) },
  113. { PCI_VDEVICE(INTEL, 0x0f46) },
  114. { PCI_VDEVICE(INTEL, 0x0f47) },
  115. { PCI_VDEVICE(INTEL, 0x5aac), .driver_data = INTEL_APL },
  116. { PCI_VDEVICE(INTEL, 0x5aae), .driver_data = INTEL_APL },
  117. { PCI_VDEVICE(INTEL, 0x5ab0), .driver_data = INTEL_APL },
  118. { PCI_VDEVICE(INTEL, 0x5ab2), .driver_data = INTEL_APL },
  119. { PCI_VDEVICE(INTEL, 0x5ab4), .driver_data = INTEL_APL },
  120. { PCI_VDEVICE(INTEL, 0x5ab6), .driver_data = INTEL_APL },
  121. {},
  122. };
  123. U_BOOT_PCI_DEVICE(i2c_designware_pci, designware_pci_supported);