designware_i2c.c 20 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2009
  4. * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com.
  5. */
  6. #include <common.h>
  7. #include <clk.h>
  8. #include <dm.h>
  9. #include <i2c.h>
  10. #include <malloc.h>
  11. #include <pci.h>
  12. #include <reset.h>
  13. #include <asm/io.h>
  14. #include "designware_i2c.h"
  15. #include <dm/device_compat.h>
  16. #include <linux/err.h>
  17. #ifdef CONFIG_SYS_I2C_DW_ENABLE_STATUS_UNSUPPORTED
  18. static int dw_i2c_enable(struct i2c_regs *i2c_base, bool enable)
  19. {
  20. u32 ena = enable ? IC_ENABLE_0B : 0;
  21. writel(ena, &i2c_base->ic_enable);
  22. return 0;
  23. }
  24. #else
  25. static int dw_i2c_enable(struct i2c_regs *i2c_base, bool enable)
  26. {
  27. u32 ena = enable ? IC_ENABLE_0B : 0;
  28. int timeout = 100;
  29. do {
  30. writel(ena, &i2c_base->ic_enable);
  31. if ((readl(&i2c_base->ic_enable_status) & IC_ENABLE_0B) == ena)
  32. return 0;
  33. /*
  34. * Wait 10 times the signaling period of the highest I2C
  35. * transfer supported by the driver (for 400KHz this is
  36. * 25us) as described in the DesignWare I2C databook.
  37. */
  38. udelay(25);
  39. } while (timeout--);
  40. printf("timeout in %sabling I2C adapter\n", enable ? "en" : "dis");
  41. return -ETIMEDOUT;
  42. }
  43. #endif
  44. /* High and low times in different speed modes (in ns) */
  45. enum {
  46. /* SDA Hold Time */
  47. DEFAULT_SDA_HOLD_TIME = 300,
  48. };
  49. /**
  50. * calc_counts() - Convert a period to a number of IC clk cycles
  51. *
  52. * @ic_clk: Input clock in Hz
  53. * @period_ns: Period to represent, in ns
  54. * @return calculated count
  55. */
  56. static uint calc_counts(uint ic_clk, uint period_ns)
  57. {
  58. return DIV_ROUND_UP(ic_clk / 1000 * period_ns, NANO_TO_KILO);
  59. }
  60. /**
  61. * struct i2c_mode_info - Information about an I2C speed mode
  62. *
  63. * Each speed mode has its own characteristics. This struct holds these to aid
  64. * calculations in dw_i2c_calc_timing().
  65. *
  66. * @speed: Speed in Hz
  67. * @min_scl_lowtime_ns: Minimum value for SCL low period in ns
  68. * @min_scl_hightime_ns: Minimum value for SCL high period in ns
  69. * @def_rise_time_ns: Default rise time in ns
  70. * @def_fall_time_ns: Default fall time in ns
  71. */
  72. struct i2c_mode_info {
  73. int speed;
  74. int min_scl_hightime_ns;
  75. int min_scl_lowtime_ns;
  76. int def_rise_time_ns;
  77. int def_fall_time_ns;
  78. };
  79. static const struct i2c_mode_info info_for_mode[] = {
  80. [IC_SPEED_MODE_STANDARD] = {
  81. I2C_SPEED_STANDARD_RATE,
  82. MIN_SS_SCL_HIGHTIME,
  83. MIN_SS_SCL_LOWTIME,
  84. 1000,
  85. 300,
  86. },
  87. [IC_SPEED_MODE_FAST] = {
  88. I2C_SPEED_FAST_RATE,
  89. MIN_FS_SCL_HIGHTIME,
  90. MIN_FS_SCL_LOWTIME,
  91. 300,
  92. 300,
  93. },
  94. [IC_SPEED_MODE_FAST_PLUS] = {
  95. I2C_SPEED_FAST_PLUS_RATE,
  96. MIN_FP_SCL_HIGHTIME,
  97. MIN_FP_SCL_LOWTIME,
  98. 260,
  99. 500,
  100. },
  101. [IC_SPEED_MODE_HIGH] = {
  102. I2C_SPEED_HIGH_RATE,
  103. MIN_HS_SCL_HIGHTIME,
  104. MIN_HS_SCL_LOWTIME,
  105. 120,
  106. 120,
  107. },
  108. };
  109. /**
  110. * dw_i2c_calc_timing() - Calculate the timings to use for a bus
  111. *
  112. * @priv: Bus private information (NULL if not using driver model)
  113. * @mode: Speed mode to use
  114. * @ic_clk: IC clock speed in Hz
  115. * @spk_cnt: Spike-suppression count
  116. * @config: Returns value to use
  117. * @return 0 if OK, -EINVAL if the calculation failed due to invalid data
  118. */
  119. static int dw_i2c_calc_timing(struct dw_i2c *priv, enum i2c_speed_mode mode,
  120. int ic_clk, int spk_cnt,
  121. struct dw_i2c_speed_config *config)
  122. {
  123. int fall_cnt, rise_cnt, min_tlow_cnt, min_thigh_cnt;
  124. int hcnt, lcnt, period_cnt, diff, tot;
  125. int sda_hold_time_ns, scl_rise_time_ns, scl_fall_time_ns;
  126. const struct i2c_mode_info *info;
  127. /*
  128. * Find the period, rise, fall, min tlow, and min thigh in terms of
  129. * counts of the IC clock
  130. */
  131. info = &info_for_mode[mode];
  132. period_cnt = ic_clk / info->speed;
  133. scl_rise_time_ns = priv && priv->scl_rise_time_ns ?
  134. priv->scl_rise_time_ns : info->def_rise_time_ns;
  135. scl_fall_time_ns = priv && priv->scl_fall_time_ns ?
  136. priv->scl_fall_time_ns : info->def_fall_time_ns;
  137. rise_cnt = calc_counts(ic_clk, scl_rise_time_ns);
  138. fall_cnt = calc_counts(ic_clk, scl_fall_time_ns);
  139. min_tlow_cnt = calc_counts(ic_clk, info->min_scl_lowtime_ns);
  140. min_thigh_cnt = calc_counts(ic_clk, info->min_scl_hightime_ns);
  141. debug("dw_i2c: period %d rise %d fall %d tlow %d thigh %d spk %d\n",
  142. period_cnt, rise_cnt, fall_cnt, min_tlow_cnt, min_thigh_cnt,
  143. spk_cnt);
  144. /*
  145. * Back-solve for hcnt and lcnt according to the following equations:
  146. * SCL_High_time = [(HCNT + IC_*_SPKLEN + 7) * ic_clk] + SCL_Fall_time
  147. * SCL_Low_time = [(LCNT + 1) * ic_clk] - SCL_Fall_time + SCL_Rise_time
  148. */
  149. hcnt = min_thigh_cnt - fall_cnt - 7 - spk_cnt;
  150. lcnt = min_tlow_cnt - rise_cnt + fall_cnt - 1;
  151. if (hcnt < 0 || lcnt < 0) {
  152. debug("dw_i2c: bad counts. hcnt = %d lcnt = %d\n", hcnt, lcnt);
  153. return -EINVAL;
  154. }
  155. /*
  156. * Now add things back up to ensure the period is hit. If it is off,
  157. * split the difference and bias to lcnt for remainder
  158. */
  159. tot = hcnt + lcnt + 7 + spk_cnt + rise_cnt + 1;
  160. if (tot < period_cnt) {
  161. diff = (period_cnt - tot) / 2;
  162. hcnt += diff;
  163. lcnt += diff;
  164. tot = hcnt + lcnt + 7 + spk_cnt + rise_cnt + 1;
  165. lcnt += period_cnt - tot;
  166. }
  167. config->scl_lcnt = lcnt;
  168. config->scl_hcnt = hcnt;
  169. /* Use internal default unless other value is specified */
  170. sda_hold_time_ns = priv && priv->sda_hold_time_ns ?
  171. priv->sda_hold_time_ns : DEFAULT_SDA_HOLD_TIME;
  172. config->sda_hold = calc_counts(ic_clk, sda_hold_time_ns);
  173. debug("dw_i2c: hcnt = %d lcnt = %d sda hold = %d\n", hcnt, lcnt,
  174. config->sda_hold);
  175. return 0;
  176. }
  177. static int calc_bus_speed(struct dw_i2c *priv, int speed, ulong bus_clk,
  178. struct dw_i2c_speed_config *config)
  179. {
  180. const struct dw_scl_sda_cfg *scl_sda_cfg = NULL;
  181. struct i2c_regs *regs = priv->regs;
  182. enum i2c_speed_mode i2c_spd;
  183. u32 comp_param1;
  184. int spk_cnt;
  185. int ret;
  186. comp_param1 = readl(&regs->comp_param1);
  187. if (priv)
  188. scl_sda_cfg = priv->scl_sda_cfg;
  189. /* Allow high speed if there is no config, or the config allows it */
  190. if (speed >= I2C_SPEED_HIGH_RATE)
  191. i2c_spd = IC_SPEED_MODE_HIGH;
  192. else if (speed >= I2C_SPEED_FAST_PLUS_RATE)
  193. i2c_spd = IC_SPEED_MODE_FAST_PLUS;
  194. else if (speed >= I2C_SPEED_FAST_RATE)
  195. i2c_spd = IC_SPEED_MODE_FAST;
  196. else
  197. i2c_spd = IC_SPEED_MODE_STANDARD;
  198. /* Check is high speed possible and fall back to fast mode if not */
  199. if (i2c_spd == IC_SPEED_MODE_HIGH) {
  200. if ((comp_param1 & DW_IC_COMP_PARAM_1_SPEED_MODE_MASK)
  201. != DW_IC_COMP_PARAM_1_SPEED_MODE_HIGH)
  202. i2c_spd = IC_SPEED_MODE_FAST;
  203. }
  204. /* Get the proper spike-suppression count based on target speed */
  205. if (!priv || !priv->has_spk_cnt)
  206. spk_cnt = 0;
  207. else if (i2c_spd >= IC_SPEED_MODE_HIGH)
  208. spk_cnt = readl(&regs->hs_spklen);
  209. else
  210. spk_cnt = readl(&regs->fs_spklen);
  211. if (scl_sda_cfg) {
  212. config->sda_hold = scl_sda_cfg->sda_hold;
  213. if (i2c_spd == IC_SPEED_MODE_STANDARD) {
  214. config->scl_hcnt = scl_sda_cfg->ss_hcnt;
  215. config->scl_lcnt = scl_sda_cfg->ss_lcnt;
  216. } else if (i2c_spd == IC_SPEED_MODE_HIGH) {
  217. config->scl_hcnt = scl_sda_cfg->hs_hcnt;
  218. config->scl_lcnt = scl_sda_cfg->hs_lcnt;
  219. } else {
  220. config->scl_hcnt = scl_sda_cfg->fs_hcnt;
  221. config->scl_lcnt = scl_sda_cfg->fs_lcnt;
  222. }
  223. } else {
  224. ret = dw_i2c_calc_timing(priv, i2c_spd, bus_clk, spk_cnt,
  225. config);
  226. if (ret)
  227. return log_msg_ret("gen_confg", ret);
  228. }
  229. config->speed_mode = i2c_spd;
  230. return 0;
  231. }
  232. /*
  233. * _dw_i2c_set_bus_speed - Set the i2c speed
  234. * @speed: required i2c speed
  235. *
  236. * Set the i2c speed.
  237. */
  238. static int _dw_i2c_set_bus_speed(struct dw_i2c *priv, struct i2c_regs *i2c_base,
  239. unsigned int speed, unsigned int bus_clk)
  240. {
  241. struct dw_i2c_speed_config config;
  242. unsigned int cntl;
  243. unsigned int ena;
  244. int ret;
  245. ret = calc_bus_speed(priv, speed, bus_clk, &config);
  246. if (ret)
  247. return ret;
  248. /* Get enable setting for restore later */
  249. ena = readl(&i2c_base->ic_enable) & IC_ENABLE_0B;
  250. /* to set speed cltr must be disabled */
  251. dw_i2c_enable(i2c_base, false);
  252. cntl = (readl(&i2c_base->ic_con) & (~IC_CON_SPD_MSK));
  253. switch (config.speed_mode) {
  254. case IC_SPEED_MODE_HIGH:
  255. cntl |= IC_CON_SPD_HS;
  256. writel(config.scl_hcnt, &i2c_base->ic_hs_scl_hcnt);
  257. writel(config.scl_lcnt, &i2c_base->ic_hs_scl_lcnt);
  258. break;
  259. case IC_SPEED_MODE_STANDARD:
  260. cntl |= IC_CON_SPD_SS;
  261. writel(config.scl_hcnt, &i2c_base->ic_ss_scl_hcnt);
  262. writel(config.scl_lcnt, &i2c_base->ic_ss_scl_lcnt);
  263. break;
  264. case IC_SPEED_MODE_FAST_PLUS:
  265. case IC_SPEED_MODE_FAST:
  266. default:
  267. cntl |= IC_CON_SPD_FS;
  268. writel(config.scl_hcnt, &i2c_base->ic_fs_scl_hcnt);
  269. writel(config.scl_lcnt, &i2c_base->ic_fs_scl_lcnt);
  270. break;
  271. }
  272. writel(cntl, &i2c_base->ic_con);
  273. /* Configure SDA Hold Time if required */
  274. if (config.sda_hold)
  275. writel(config.sda_hold, &i2c_base->ic_sda_hold);
  276. /* Restore back i2c now speed set */
  277. if (ena == IC_ENABLE_0B)
  278. dw_i2c_enable(i2c_base, true);
  279. return 0;
  280. }
  281. /*
  282. * i2c_setaddress - Sets the target slave address
  283. * @i2c_addr: target i2c address
  284. *
  285. * Sets the target slave address.
  286. */
  287. static void i2c_setaddress(struct i2c_regs *i2c_base, unsigned int i2c_addr)
  288. {
  289. /* Disable i2c */
  290. dw_i2c_enable(i2c_base, false);
  291. writel(i2c_addr, &i2c_base->ic_tar);
  292. /* Enable i2c */
  293. dw_i2c_enable(i2c_base, true);
  294. }
  295. /*
  296. * i2c_flush_rxfifo - Flushes the i2c RX FIFO
  297. *
  298. * Flushes the i2c RX FIFO
  299. */
  300. static void i2c_flush_rxfifo(struct i2c_regs *i2c_base)
  301. {
  302. while (readl(&i2c_base->ic_status) & IC_STATUS_RFNE)
  303. readl(&i2c_base->ic_cmd_data);
  304. }
  305. /*
  306. * i2c_wait_for_bb - Waits for bus busy
  307. *
  308. * Waits for bus busy
  309. */
  310. static int i2c_wait_for_bb(struct i2c_regs *i2c_base)
  311. {
  312. unsigned long start_time_bb = get_timer(0);
  313. while ((readl(&i2c_base->ic_status) & IC_STATUS_MA) ||
  314. !(readl(&i2c_base->ic_status) & IC_STATUS_TFE)) {
  315. /* Evaluate timeout */
  316. if (get_timer(start_time_bb) > (unsigned long)(I2C_BYTE_TO_BB))
  317. return 1;
  318. }
  319. return 0;
  320. }
  321. static int i2c_xfer_init(struct i2c_regs *i2c_base, uchar chip, uint addr,
  322. int alen)
  323. {
  324. if (i2c_wait_for_bb(i2c_base))
  325. return 1;
  326. i2c_setaddress(i2c_base, chip);
  327. while (alen) {
  328. alen--;
  329. /* high byte address going out first */
  330. writel((addr >> (alen * 8)) & 0xff,
  331. &i2c_base->ic_cmd_data);
  332. }
  333. return 0;
  334. }
  335. static int i2c_xfer_finish(struct i2c_regs *i2c_base)
  336. {
  337. ulong start_stop_det = get_timer(0);
  338. while (1) {
  339. if ((readl(&i2c_base->ic_raw_intr_stat) & IC_STOP_DET)) {
  340. readl(&i2c_base->ic_clr_stop_det);
  341. break;
  342. } else if (get_timer(start_stop_det) > I2C_STOPDET_TO) {
  343. break;
  344. }
  345. }
  346. if (i2c_wait_for_bb(i2c_base)) {
  347. printf("Timed out waiting for bus\n");
  348. return 1;
  349. }
  350. i2c_flush_rxfifo(i2c_base);
  351. return 0;
  352. }
  353. /*
  354. * i2c_read - Read from i2c memory
  355. * @chip: target i2c address
  356. * @addr: address to read from
  357. * @alen:
  358. * @buffer: buffer for read data
  359. * @len: no of bytes to be read
  360. *
  361. * Read from i2c memory.
  362. */
  363. static int __dw_i2c_read(struct i2c_regs *i2c_base, u8 dev, uint addr,
  364. int alen, u8 *buffer, int len)
  365. {
  366. unsigned long start_time_rx;
  367. unsigned int active = 0;
  368. #ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
  369. /*
  370. * EEPROM chips that implement "address overflow" are ones
  371. * like Catalyst 24WC04/08/16 which has 9/10/11 bits of
  372. * address and the extra bits end up in the "chip address"
  373. * bit slots. This makes a 24WC08 (1Kbyte) chip look like
  374. * four 256 byte chips.
  375. *
  376. * Note that we consider the length of the address field to
  377. * still be one byte because the extra address bits are
  378. * hidden in the chip address.
  379. */
  380. dev |= ((addr >> (alen * 8)) & CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW);
  381. addr &= ~(CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW << (alen * 8));
  382. debug("%s: fix addr_overflow: dev %02x addr %02x\n", __func__, dev,
  383. addr);
  384. #endif
  385. if (i2c_xfer_init(i2c_base, dev, addr, alen))
  386. return 1;
  387. start_time_rx = get_timer(0);
  388. while (len) {
  389. if (!active) {
  390. /*
  391. * Avoid writing to ic_cmd_data multiple times
  392. * in case this loop spins too quickly and the
  393. * ic_status RFNE bit isn't set after the first
  394. * write. Subsequent writes to ic_cmd_data can
  395. * trigger spurious i2c transfer.
  396. */
  397. if (len == 1)
  398. writel(IC_CMD | IC_STOP, &i2c_base->ic_cmd_data);
  399. else
  400. writel(IC_CMD, &i2c_base->ic_cmd_data);
  401. active = 1;
  402. }
  403. if (readl(&i2c_base->ic_status) & IC_STATUS_RFNE) {
  404. *buffer++ = (uchar)readl(&i2c_base->ic_cmd_data);
  405. len--;
  406. start_time_rx = get_timer(0);
  407. active = 0;
  408. } else if (get_timer(start_time_rx) > I2C_BYTE_TO) {
  409. return 1;
  410. }
  411. }
  412. return i2c_xfer_finish(i2c_base);
  413. }
  414. /*
  415. * i2c_write - Write to i2c memory
  416. * @chip: target i2c address
  417. * @addr: address to read from
  418. * @alen:
  419. * @buffer: buffer for read data
  420. * @len: no of bytes to be read
  421. *
  422. * Write to i2c memory.
  423. */
  424. static int __dw_i2c_write(struct i2c_regs *i2c_base, u8 dev, uint addr,
  425. int alen, u8 *buffer, int len)
  426. {
  427. int nb = len;
  428. unsigned long start_time_tx;
  429. #ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
  430. /*
  431. * EEPROM chips that implement "address overflow" are ones
  432. * like Catalyst 24WC04/08/16 which has 9/10/11 bits of
  433. * address and the extra bits end up in the "chip address"
  434. * bit slots. This makes a 24WC08 (1Kbyte) chip look like
  435. * four 256 byte chips.
  436. *
  437. * Note that we consider the length of the address field to
  438. * still be one byte because the extra address bits are
  439. * hidden in the chip address.
  440. */
  441. dev |= ((addr >> (alen * 8)) & CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW);
  442. addr &= ~(CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW << (alen * 8));
  443. debug("%s: fix addr_overflow: dev %02x addr %02x\n", __func__, dev,
  444. addr);
  445. #endif
  446. if (i2c_xfer_init(i2c_base, dev, addr, alen))
  447. return 1;
  448. start_time_tx = get_timer(0);
  449. while (len) {
  450. if (readl(&i2c_base->ic_status) & IC_STATUS_TFNF) {
  451. if (--len == 0) {
  452. writel(*buffer | IC_STOP,
  453. &i2c_base->ic_cmd_data);
  454. } else {
  455. writel(*buffer, &i2c_base->ic_cmd_data);
  456. }
  457. buffer++;
  458. start_time_tx = get_timer(0);
  459. } else if (get_timer(start_time_tx) > (nb * I2C_BYTE_TO)) {
  460. printf("Timed out. i2c write Failed\n");
  461. return 1;
  462. }
  463. }
  464. return i2c_xfer_finish(i2c_base);
  465. }
  466. /*
  467. * __dw_i2c_init - Init function
  468. * @speed: required i2c speed
  469. * @slaveaddr: slave address for the device
  470. *
  471. * Initialization function.
  472. */
  473. static int __dw_i2c_init(struct i2c_regs *i2c_base, int speed, int slaveaddr)
  474. {
  475. int ret;
  476. /* Disable i2c */
  477. ret = dw_i2c_enable(i2c_base, false);
  478. if (ret)
  479. return ret;
  480. writel(IC_CON_SD | IC_CON_RE | IC_CON_SPD_FS | IC_CON_MM,
  481. &i2c_base->ic_con);
  482. writel(IC_RX_TL, &i2c_base->ic_rx_tl);
  483. writel(IC_TX_TL, &i2c_base->ic_tx_tl);
  484. writel(IC_STOP_DET, &i2c_base->ic_intr_mask);
  485. #ifndef CONFIG_DM_I2C
  486. _dw_i2c_set_bus_speed(NULL, i2c_base, speed, IC_CLK);
  487. writel(slaveaddr, &i2c_base->ic_sar);
  488. #endif
  489. /* Enable i2c */
  490. ret = dw_i2c_enable(i2c_base, true);
  491. if (ret)
  492. return ret;
  493. return 0;
  494. }
  495. #ifndef CONFIG_DM_I2C
  496. /*
  497. * The legacy I2C functions. These need to get removed once
  498. * all users of this driver are converted to DM.
  499. */
  500. static struct i2c_regs *i2c_get_base(struct i2c_adapter *adap)
  501. {
  502. switch (adap->hwadapnr) {
  503. #if CONFIG_SYS_I2C_BUS_MAX >= 4
  504. case 3:
  505. return (struct i2c_regs *)CONFIG_SYS_I2C_BASE3;
  506. #endif
  507. #if CONFIG_SYS_I2C_BUS_MAX >= 3
  508. case 2:
  509. return (struct i2c_regs *)CONFIG_SYS_I2C_BASE2;
  510. #endif
  511. #if CONFIG_SYS_I2C_BUS_MAX >= 2
  512. case 1:
  513. return (struct i2c_regs *)CONFIG_SYS_I2C_BASE1;
  514. #endif
  515. case 0:
  516. return (struct i2c_regs *)CONFIG_SYS_I2C_BASE;
  517. default:
  518. printf("Wrong I2C-adapter number %d\n", adap->hwadapnr);
  519. }
  520. return NULL;
  521. }
  522. static unsigned int dw_i2c_set_bus_speed(struct i2c_adapter *adap,
  523. unsigned int speed)
  524. {
  525. adap->speed = speed;
  526. return _dw_i2c_set_bus_speed(NULL, i2c_get_base(adap), speed, IC_CLK);
  527. }
  528. static void dw_i2c_init(struct i2c_adapter *adap, int speed, int slaveaddr)
  529. {
  530. __dw_i2c_init(i2c_get_base(adap), speed, slaveaddr);
  531. }
  532. static int dw_i2c_read(struct i2c_adapter *adap, u8 dev, uint addr,
  533. int alen, u8 *buffer, int len)
  534. {
  535. return __dw_i2c_read(i2c_get_base(adap), dev, addr, alen, buffer, len);
  536. }
  537. static int dw_i2c_write(struct i2c_adapter *adap, u8 dev, uint addr,
  538. int alen, u8 *buffer, int len)
  539. {
  540. return __dw_i2c_write(i2c_get_base(adap), dev, addr, alen, buffer, len);
  541. }
  542. /* dw_i2c_probe - Probe the i2c chip */
  543. static int dw_i2c_probe(struct i2c_adapter *adap, u8 dev)
  544. {
  545. struct i2c_regs *i2c_base = i2c_get_base(adap);
  546. u32 tmp;
  547. int ret;
  548. /*
  549. * Try to read the first location of the chip.
  550. */
  551. ret = __dw_i2c_read(i2c_base, dev, 0, 1, (uchar *)&tmp, 1);
  552. if (ret)
  553. dw_i2c_init(adap, adap->speed, adap->slaveaddr);
  554. return ret;
  555. }
  556. U_BOOT_I2C_ADAP_COMPLETE(dw_0, dw_i2c_init, dw_i2c_probe, dw_i2c_read,
  557. dw_i2c_write, dw_i2c_set_bus_speed,
  558. CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE, 0)
  559. #if CONFIG_SYS_I2C_BUS_MAX >= 2
  560. U_BOOT_I2C_ADAP_COMPLETE(dw_1, dw_i2c_init, dw_i2c_probe, dw_i2c_read,
  561. dw_i2c_write, dw_i2c_set_bus_speed,
  562. CONFIG_SYS_I2C_SPEED1, CONFIG_SYS_I2C_SLAVE1, 1)
  563. #endif
  564. #if CONFIG_SYS_I2C_BUS_MAX >= 3
  565. U_BOOT_I2C_ADAP_COMPLETE(dw_2, dw_i2c_init, dw_i2c_probe, dw_i2c_read,
  566. dw_i2c_write, dw_i2c_set_bus_speed,
  567. CONFIG_SYS_I2C_SPEED2, CONFIG_SYS_I2C_SLAVE2, 2)
  568. #endif
  569. #if CONFIG_SYS_I2C_BUS_MAX >= 4
  570. U_BOOT_I2C_ADAP_COMPLETE(dw_3, dw_i2c_init, dw_i2c_probe, dw_i2c_read,
  571. dw_i2c_write, dw_i2c_set_bus_speed,
  572. CONFIG_SYS_I2C_SPEED3, CONFIG_SYS_I2C_SLAVE3, 3)
  573. #endif
  574. #else /* CONFIG_DM_I2C */
  575. /* The DM I2C functions */
  576. static int designware_i2c_xfer(struct udevice *bus, struct i2c_msg *msg,
  577. int nmsgs)
  578. {
  579. struct dw_i2c *i2c = dev_get_priv(bus);
  580. int ret;
  581. debug("i2c_xfer: %d messages\n", nmsgs);
  582. for (; nmsgs > 0; nmsgs--, msg++) {
  583. debug("i2c_xfer: chip=0x%x, len=0x%x\n", msg->addr, msg->len);
  584. if (msg->flags & I2C_M_RD) {
  585. ret = __dw_i2c_read(i2c->regs, msg->addr, 0, 0,
  586. msg->buf, msg->len);
  587. } else {
  588. ret = __dw_i2c_write(i2c->regs, msg->addr, 0, 0,
  589. msg->buf, msg->len);
  590. }
  591. if (ret) {
  592. debug("i2c_write: error sending\n");
  593. return -EREMOTEIO;
  594. }
  595. }
  596. return 0;
  597. }
  598. static int designware_i2c_set_bus_speed(struct udevice *bus, unsigned int speed)
  599. {
  600. struct dw_i2c *i2c = dev_get_priv(bus);
  601. ulong rate;
  602. #if CONFIG_IS_ENABLED(CLK)
  603. rate = clk_get_rate(&i2c->clk);
  604. if (IS_ERR_VALUE(rate))
  605. return -EINVAL;
  606. #else
  607. rate = IC_CLK;
  608. #endif
  609. return _dw_i2c_set_bus_speed(i2c, i2c->regs, speed, rate);
  610. }
  611. static int designware_i2c_probe_chip(struct udevice *bus, uint chip_addr,
  612. uint chip_flags)
  613. {
  614. struct dw_i2c *i2c = dev_get_priv(bus);
  615. struct i2c_regs *i2c_base = i2c->regs;
  616. u32 tmp;
  617. int ret;
  618. /* Try to read the first location of the chip */
  619. ret = __dw_i2c_read(i2c_base, chip_addr, 0, 1, (uchar *)&tmp, 1);
  620. if (ret)
  621. __dw_i2c_init(i2c_base, 0, 0);
  622. return ret;
  623. }
  624. int designware_i2c_ofdata_to_platdata(struct udevice *bus)
  625. {
  626. struct dw_i2c *priv = dev_get_priv(bus);
  627. int ret;
  628. if (!priv->regs)
  629. priv->regs = (struct i2c_regs *)devfdt_get_addr_ptr(bus);
  630. dev_read_u32(bus, "i2c-scl-rising-time-ns", &priv->scl_rise_time_ns);
  631. dev_read_u32(bus, "i2c-scl-falling-time-ns", &priv->scl_fall_time_ns);
  632. dev_read_u32(bus, "i2c-sda-hold-time-ns", &priv->sda_hold_time_ns);
  633. ret = reset_get_bulk(bus, &priv->resets);
  634. if (ret)
  635. dev_warn(bus, "Can't get reset: %d\n", ret);
  636. else
  637. reset_deassert_bulk(&priv->resets);
  638. #if CONFIG_IS_ENABLED(CLK)
  639. ret = clk_get_by_index(bus, 0, &priv->clk);
  640. if (ret)
  641. return ret;
  642. ret = clk_enable(&priv->clk);
  643. if (ret && ret != -ENOSYS && ret != -ENOTSUPP) {
  644. clk_free(&priv->clk);
  645. dev_err(bus, "failed to enable clock\n");
  646. return ret;
  647. }
  648. #endif
  649. return 0;
  650. }
  651. int designware_i2c_probe(struct udevice *bus)
  652. {
  653. struct dw_i2c *priv = dev_get_priv(bus);
  654. return __dw_i2c_init(priv->regs, 0, 0);
  655. }
  656. int designware_i2c_remove(struct udevice *dev)
  657. {
  658. struct dw_i2c *priv = dev_get_priv(dev);
  659. #if CONFIG_IS_ENABLED(CLK)
  660. clk_disable(&priv->clk);
  661. clk_free(&priv->clk);
  662. #endif
  663. return reset_release_bulk(&priv->resets);
  664. }
  665. const struct dm_i2c_ops designware_i2c_ops = {
  666. .xfer = designware_i2c_xfer,
  667. .probe_chip = designware_i2c_probe_chip,
  668. .set_bus_speed = designware_i2c_set_bus_speed,
  669. };
  670. static const struct udevice_id designware_i2c_ids[] = {
  671. { .compatible = "snps,designware-i2c" },
  672. { }
  673. };
  674. U_BOOT_DRIVER(i2c_designware) = {
  675. .name = "i2c_designware",
  676. .id = UCLASS_I2C,
  677. .of_match = designware_i2c_ids,
  678. .ofdata_to_platdata = designware_i2c_ofdata_to_platdata,
  679. .probe = designware_i2c_probe,
  680. .priv_auto_alloc_size = sizeof(struct dw_i2c),
  681. .remove = designware_i2c_remove,
  682. .flags = DM_FLAG_OS_PREPARE,
  683. .ops = &designware_i2c_ops,
  684. };
  685. #endif /* CONFIG_DM_I2C */