Kconfig 13 KB

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  1. #
  2. # I2C subsystem configuration
  3. #
  4. menu "I2C support"
  5. config DM_I2C
  6. bool "Enable Driver Model for I2C drivers"
  7. depends on DM
  8. help
  9. Enable driver model for I2C. The I2C uclass interface: probe, read,
  10. write and speed, is implemented with the bus drivers operations,
  11. which provide methods for bus setting and data transfer. Each chip
  12. device (bus child) info is kept as parent platdata. The interface
  13. is defined in include/i2c.h.
  14. config I2C_CROS_EC_TUNNEL
  15. tristate "Chrome OS EC tunnel I2C bus"
  16. depends on CROS_EC
  17. help
  18. This provides an I2C bus that will tunnel i2c commands through to
  19. the other side of the Chrome OS EC to the I2C bus connected there.
  20. This will work whatever the interface used to talk to the EC (SPI,
  21. I2C or LPC). Some Chromebooks use this when the hardware design
  22. does not allow direct access to the main PMIC from the AP.
  23. config I2C_CROS_EC_LDO
  24. bool "Provide access to LDOs on the Chrome OS EC"
  25. depends on CROS_EC
  26. ---help---
  27. On many Chromebooks the main PMIC is inaccessible to the AP. This is
  28. often dealt with by using an I2C pass-through interface provided by
  29. the EC. On some unfortunate models (e.g. Spring) the pass-through
  30. is not available, and an LDO message is available instead. This
  31. option enables a driver which provides very basic access to those
  32. regulators, via the EC. We implement this as an I2C bus which
  33. emulates just the TPS65090 messages we know about. This is done to
  34. avoid duplicating the logic in the TPS65090 regulator driver for
  35. enabling/disabling an LDO.
  36. config I2C_SET_DEFAULT_BUS_NUM
  37. bool "Set default I2C bus number"
  38. depends on DM_I2C
  39. help
  40. Set default number of I2C bus to be accessed. This option provides
  41. behaviour similar to old (i.e. pre DM) I2C bus driver.
  42. config I2C_DEFAULT_BUS_NUMBER
  43. hex "I2C default bus number"
  44. depends on I2C_SET_DEFAULT_BUS_NUM
  45. default 0x0
  46. help
  47. Number of default I2C bus to use
  48. config DM_I2C_GPIO
  49. bool "Enable Driver Model for software emulated I2C bus driver"
  50. depends on DM_I2C && DM_GPIO
  51. help
  52. Enable the i2c bus driver emulation by using the GPIOs. The bus GPIO
  53. configuration is given by the device tree. Kernel-style device tree
  54. bindings are supported.
  55. Binding info: doc/device-tree-bindings/i2c/i2c-gpio.txt
  56. config SYS_I2C_AT91
  57. bool "Atmel I2C driver"
  58. depends on DM_I2C && ARCH_AT91
  59. help
  60. Add support for the Atmel I2C driver. A serious problem is that there
  61. is no documented way to issue repeated START conditions for more than
  62. two messages, as needed to support combined I2C messages. Use the
  63. i2c-gpio driver unless your system can cope with this limitation.
  64. Binding info: doc/device-tree-bindings/i2c/i2c-at91.txt
  65. config SYS_I2C_IPROC
  66. bool "Broadcom I2C driver"
  67. depends on DM_I2C
  68. help
  69. Broadcom I2C driver.
  70. Add support for Broadcom I2C driver.
  71. Say yes here to to enable the Broadco I2C driver.
  72. config SYS_I2C_FSL
  73. bool "Freescale I2C bus driver"
  74. depends on DM_I2C
  75. help
  76. Add support for Freescale I2C busses as used on MPC8240, MPC8245, and
  77. MPC85xx processors.
  78. config SYS_I2C_CADENCE
  79. tristate "Cadence I2C Controller"
  80. depends on DM_I2C && (ARCH_ZYNQ || ARM64)
  81. help
  82. Say yes here to select Cadence I2C Host Controller. This controller is
  83. e.g. used by Xilinx Zynq.
  84. config SYS_I2C_DAVINCI
  85. bool "Davinci I2C Controller"
  86. depends on (ARCH_KEYSTONE || ARCH_DAVINCI)
  87. help
  88. Say yes here to add support for Davinci and Keystone I2C controller
  89. config SYS_I2C_DW
  90. bool "Designware I2C Controller"
  91. default n
  92. help
  93. Say yes here to select the Designware I2C Host Controller. This
  94. controller is used in various SoCs, e.g. the ST SPEAr, Altera
  95. SoCFPGA, Synopsys ARC700 and some Intel x86 SoCs.
  96. config SYS_I2C_DW_ENABLE_STATUS_UNSUPPORTED
  97. bool "DW I2C Enable Status Register not supported"
  98. depends on SYS_I2C_DW && (TARGET_SPEAR300 || TARGET_SPEAR310 || \
  99. TARGET_SPEAR320 || TARGET_SPEAR600 || TARGET_X600)
  100. default y
  101. help
  102. Some versions of the Designware I2C controller do not support the
  103. enable status register. This config option can be enabled in such
  104. cases.
  105. config SYS_I2C_ASPEED
  106. bool "Aspeed I2C Controller"
  107. depends on DM_I2C && ARCH_ASPEED
  108. help
  109. Say yes here to select Aspeed I2C Host Controller. The driver
  110. supports AST2500 and AST2400 controllers, but is very limited.
  111. Only single master mode is supported and only byte-by-byte
  112. synchronous reads and writes are supported, no Pool Buffers or DMA.
  113. config SYS_I2C_INTEL
  114. bool "Intel I2C/SMBUS driver"
  115. depends on DM_I2C
  116. help
  117. Add support for the Intel SMBUS driver. So far this driver is just
  118. a stub which perhaps some basic init. There is no implementation of
  119. the I2C API meaning that any I2C operations will immediately fail
  120. for now.
  121. config SYS_I2C_IMX_LPI2C
  122. bool "NXP i.MX LPI2C driver"
  123. help
  124. Add support for the NXP i.MX LPI2C driver.
  125. config SYS_I2C_MESON
  126. bool "Amlogic Meson I2C driver"
  127. depends on DM_I2C && ARCH_MESON
  128. help
  129. Add support for the I2C controller available in Amlogic Meson
  130. SoCs. The controller supports programmable bus speed including
  131. standard (100kbits/s) and fast (400kbit/s) speed and allows the
  132. software to define a flexible format of the bit streams. It has an
  133. internal buffer holding up to 8 bytes for transfers and supports
  134. both 7-bit and 10-bit addresses.
  135. config SYS_I2C_MXC
  136. bool "NXP MXC I2C driver"
  137. help
  138. Add support for the NXP I2C driver. This supports up to four bus
  139. channels and operating on standard mode up to 100 kbits/s and fast
  140. mode up to 400 kbits/s.
  141. # These settings are not used with DM_I2C, however SPL doesn't use
  142. # DM_I2C even if DM_I2C is enabled, and so might use these settings even
  143. # when main u-boot does not!
  144. if SYS_I2C_MXC && (!DM_I2C || SPL)
  145. config SYS_I2C_MXC_I2C1
  146. bool "NXP MXC I2C1"
  147. help
  148. Add support for NXP MXC I2C Controller 1.
  149. Required for SoCs which have I2C MXC controller 1 eg LS1088A, LS2080A
  150. config SYS_I2C_MXC_I2C2
  151. bool "NXP MXC I2C2"
  152. help
  153. Add support for NXP MXC I2C Controller 2.
  154. Required for SoCs which have I2C MXC controller 2 eg LS1088A, LS2080A
  155. config SYS_I2C_MXC_I2C3
  156. bool "NXP MXC I2C3"
  157. help
  158. Add support for NXP MXC I2C Controller 3.
  159. Required for SoCs which have I2C MXC controller 3 eg LS1088A, LS2080A
  160. config SYS_I2C_MXC_I2C4
  161. bool "NXP MXC I2C4"
  162. help
  163. Add support for NXP MXC I2C Controller 4.
  164. Required for SoCs which have I2C MXC controller 4 eg LS1088A, LS2080A
  165. config SYS_I2C_MXC_I2C5
  166. bool "NXP MXC I2C5"
  167. help
  168. Add support for NXP MXC I2C Controller 5.
  169. Required for SoCs which have I2C MXC controller 5 eg LX2160A
  170. config SYS_I2C_MXC_I2C6
  171. bool "NXP MXC I2C6"
  172. help
  173. Add support for NXP MXC I2C Controller 6.
  174. Required for SoCs which have I2C MXC controller 6 eg LX2160A
  175. config SYS_I2C_MXC_I2C7
  176. bool "NXP MXC I2C7"
  177. help
  178. Add support for NXP MXC I2C Controller 7.
  179. Required for SoCs which have I2C MXC controller 7 eg LX2160A
  180. config SYS_I2C_MXC_I2C8
  181. bool "NXP MXC I2C8"
  182. help
  183. Add support for NXP MXC I2C Controller 8.
  184. Required for SoCs which have I2C MXC controller 8 eg LX2160A
  185. endif
  186. if SYS_I2C_MXC_I2C1
  187. config SYS_MXC_I2C1_SPEED
  188. int "I2C Channel 1 speed"
  189. default 40000000 if TARGET_LS2080A_SIMU || TARGET_LS2080A_EMU
  190. default 100000
  191. help
  192. MXC I2C Channel 1 speed
  193. config SYS_MXC_I2C1_SLAVE
  194. int "I2C1 Slave"
  195. default 0
  196. help
  197. MXC I2C1 Slave
  198. endif
  199. if SYS_I2C_MXC_I2C2
  200. config SYS_MXC_I2C2_SPEED
  201. int "I2C Channel 2 speed"
  202. default 40000000 if TARGET_LS2080A_SIMU || TARGET_LS2080A_EMU
  203. default 100000
  204. help
  205. MXC I2C Channel 2 speed
  206. config SYS_MXC_I2C2_SLAVE
  207. int "I2C2 Slave"
  208. default 0
  209. help
  210. MXC I2C2 Slave
  211. endif
  212. if SYS_I2C_MXC_I2C3
  213. config SYS_MXC_I2C3_SPEED
  214. int "I2C Channel 3 speed"
  215. default 100000
  216. help
  217. MXC I2C Channel 3 speed
  218. config SYS_MXC_I2C3_SLAVE
  219. int "I2C3 Slave"
  220. default 0
  221. help
  222. MXC I2C3 Slave
  223. endif
  224. if SYS_I2C_MXC_I2C4
  225. config SYS_MXC_I2C4_SPEED
  226. int "I2C Channel 4 speed"
  227. default 100000
  228. help
  229. MXC I2C Channel 4 speed
  230. config SYS_MXC_I2C4_SLAVE
  231. int "I2C4 Slave"
  232. default 0
  233. help
  234. MXC I2C4 Slave
  235. endif
  236. if SYS_I2C_MXC_I2C5
  237. config SYS_MXC_I2C5_SPEED
  238. int "I2C Channel 5 speed"
  239. default 100000
  240. help
  241. MXC I2C Channel 5 speed
  242. config SYS_MXC_I2C5_SLAVE
  243. int "I2C5 Slave"
  244. default 0
  245. help
  246. MXC I2C5 Slave
  247. endif
  248. if SYS_I2C_MXC_I2C6
  249. config SYS_MXC_I2C6_SPEED
  250. int "I2C Channel 6 speed"
  251. default 100000
  252. help
  253. MXC I2C Channel 6 speed
  254. config SYS_MXC_I2C6_SLAVE
  255. int "I2C6 Slave"
  256. default 0
  257. help
  258. MXC I2C6 Slave
  259. endif
  260. if SYS_I2C_MXC_I2C7
  261. config SYS_MXC_I2C7_SPEED
  262. int "I2C Channel 7 speed"
  263. default 100000
  264. help
  265. MXC I2C Channel 7 speed
  266. config SYS_MXC_I2C7_SLAVE
  267. int "I2C7 Slave"
  268. default 0
  269. help
  270. MXC I2C7 Slave
  271. endif
  272. if SYS_I2C_MXC_I2C8
  273. config SYS_MXC_I2C8_SPEED
  274. int "I2C Channel 8 speed"
  275. default 100000
  276. help
  277. MXC I2C Channel 8 speed
  278. config SYS_MXC_I2C8_SLAVE
  279. int "I2C8 Slave"
  280. default 0
  281. help
  282. MXC I2C8 Slave
  283. endif
  284. config SYS_I2C_OMAP24XX
  285. bool "TI OMAP2+ I2C driver"
  286. depends on ARCH_OMAP2PLUS || ARCH_K3
  287. help
  288. Add support for the OMAP2+ I2C driver.
  289. if SYS_I2C_OMAP24XX
  290. config SYS_OMAP24_I2C_SLAVE
  291. int "I2C Slave addr channel 0"
  292. default 1
  293. help
  294. OMAP24xx I2C Slave address channel 0
  295. config SYS_OMAP24_I2C_SPEED
  296. int "I2C Slave channel 0 speed"
  297. default 100000
  298. help
  299. OMAP24xx Slave speed channel 0
  300. endif
  301. config SYS_I2C_RCAR_I2C
  302. bool "Renesas RCar I2C driver"
  303. depends on (RCAR_GEN3 || RCAR_GEN2) && DM_I2C
  304. help
  305. Support for Renesas RCar I2C controller.
  306. config SYS_I2C_RCAR_IIC
  307. bool "Renesas RCar Gen3 IIC driver"
  308. depends on (RCAR_GEN3 || RCAR_GEN2) && DM_I2C
  309. help
  310. Support for Renesas RCar Gen3 IIC controller.
  311. config SYS_I2C_ROCKCHIP
  312. bool "Rockchip I2C driver"
  313. depends on DM_I2C
  314. help
  315. Add support for the Rockchip I2C driver. This is used with various
  316. Rockchip parts such as RK3126, RK3128, RK3036 and RK3288. All chips
  317. have several I2C ports and all are provided, controlled by the
  318. device tree.
  319. config SYS_I2C_SANDBOX
  320. bool "Sandbox I2C driver"
  321. depends on SANDBOX && DM_I2C
  322. help
  323. Enable I2C support for sandbox. This is an emulation of a real I2C
  324. bus. Devices can be attached to the bus using the device tree
  325. which specifies the driver to use. See sandbox.dts as an example.
  326. config SYS_I2C_S3C24X0
  327. bool "Samsung I2C driver"
  328. depends on ARCH_EXYNOS4 && DM_I2C
  329. help
  330. Support for Samsung I2C controller as Samsung SoCs.
  331. config SYS_I2C_STM32F7
  332. bool "STMicroelectronics STM32F7 I2C support"
  333. depends on (STM32F7 || STM32H7 || ARCH_STM32MP) && DM_I2C
  334. help
  335. Enable this option to add support for STM32 I2C controller
  336. introduced with STM32F7/H7 SoCs. This I2C controller supports :
  337. _ Slave and master modes
  338. _ Multimaster capability
  339. _ Standard-mode (up to 100 kHz)
  340. _ Fast-mode (up to 400 kHz)
  341. _ Fast-mode Plus (up to 1 MHz)
  342. _ 7-bit and 10-bit addressing mode
  343. _ Multiple 7-bit slave addresses (2 addresses, 1 with configurable mask)
  344. _ All 7-bit addresses acknowledge mode
  345. _ General call
  346. _ Programmable setup and hold times
  347. _ Easy to use event management
  348. _ Optional clock stretching
  349. _ Software reset
  350. config SYS_I2C_TEGRA
  351. bool "NVIDIA Tegra internal I2C controller"
  352. depends on ARCH_TEGRA
  353. help
  354. Support for NVIDIA I2C controller available in Tegra SoCs.
  355. config SYS_I2C_UNIPHIER
  356. bool "UniPhier I2C driver"
  357. depends on ARCH_UNIPHIER && DM_I2C
  358. default y
  359. help
  360. Support for UniPhier I2C controller driver. This I2C controller
  361. is used on PH1-LD4, PH1-sLD8 or older UniPhier SoCs.
  362. config SYS_I2C_UNIPHIER_F
  363. bool "UniPhier FIFO-builtin I2C driver"
  364. depends on ARCH_UNIPHIER && DM_I2C
  365. default y
  366. help
  367. Support for UniPhier FIFO-builtin I2C controller driver.
  368. This I2C controller is used on PH1-Pro4 or newer UniPhier SoCs.
  369. config SYS_I2C_VERSATILE
  370. bool "Arm Ltd Versatile I2C bus driver"
  371. depends on DM_I2C && (TARGET_VEXPRESS_CA15_TC2 || TARGET_VEXPRESS64_JUNO)
  372. help
  373. Add support for the Arm Ltd Versatile Express I2C driver. The I2C host
  374. controller is present in the development boards manufactured by Arm Ltd.
  375. config SYS_I2C_MVTWSI
  376. bool "Marvell I2C driver"
  377. depends on DM_I2C
  378. help
  379. Support for Marvell I2C controllers as used on the orion5x and
  380. kirkwood SoC families.
  381. config TEGRA186_BPMP_I2C
  382. bool "Enable Tegra186 BPMP-based I2C driver"
  383. depends on TEGRA186_BPMP
  384. help
  385. Support for Tegra I2C controllers managed by the BPMP (Boot and
  386. Power Management Processor). On Tegra186, some I2C controllers are
  387. directly controlled by the main CPU, whereas others are controlled
  388. by the BPMP, and can only be accessed by the main CPU via IPC
  389. requests to the BPMP. This driver covers the latter case.
  390. config SYS_I2C_BUS_MAX
  391. int "Max I2C busses"
  392. depends on ARCH_KEYSTONE || ARCH_OMAP2PLUS || ARCH_SOCFPGA
  393. default 2 if TI816X
  394. default 3 if OMAP34XX || AM33XX || AM43XX || ARCH_KEYSTONE
  395. default 4 if ARCH_SOCFPGA || OMAP44XX || TI814X
  396. default 5 if OMAP54XX
  397. help
  398. Define the maximum number of available I2C buses.
  399. config SYS_I2C_XILINX_XIIC
  400. bool "Xilinx AXI I2C driver"
  401. depends on DM_I2C
  402. help
  403. Support for Xilinx AXI I2C controller.
  404. config SYS_I2C_IHS
  405. bool "gdsys IHS I2C driver"
  406. depends on DM_I2C
  407. help
  408. Support for gdsys IHS I2C driver on FPGA bus.
  409. source "drivers/i2c/muxes/Kconfig"
  410. endmenu