xusb-padctl-common.c 6.5 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Copyright (c) 2014-2015, NVIDIA CORPORATION. All rights reserved.
  4. */
  5. #define pr_fmt(fmt) "tegra-xusb-padctl: " fmt
  6. #include <common.h>
  7. #include <errno.h>
  8. #include "xusb-padctl-common.h"
  9. #include <asm/arch/clock.h>
  10. int tegra_xusb_phy_prepare(struct tegra_xusb_phy *phy)
  11. {
  12. if (phy && phy->ops && phy->ops->prepare)
  13. return phy->ops->prepare(phy);
  14. return phy ? -ENOSYS : -EINVAL;
  15. }
  16. int tegra_xusb_phy_enable(struct tegra_xusb_phy *phy)
  17. {
  18. if (phy && phy->ops && phy->ops->enable)
  19. return phy->ops->enable(phy);
  20. return phy ? -ENOSYS : -EINVAL;
  21. }
  22. int tegra_xusb_phy_disable(struct tegra_xusb_phy *phy)
  23. {
  24. if (phy && phy->ops && phy->ops->disable)
  25. return phy->ops->disable(phy);
  26. return phy ? -ENOSYS : -EINVAL;
  27. }
  28. int tegra_xusb_phy_unprepare(struct tegra_xusb_phy *phy)
  29. {
  30. if (phy && phy->ops && phy->ops->unprepare)
  31. return phy->ops->unprepare(phy);
  32. return phy ? -ENOSYS : -EINVAL;
  33. }
  34. struct tegra_xusb_phy *tegra_xusb_phy_get(unsigned int type)
  35. {
  36. struct tegra_xusb_phy *phy;
  37. int i;
  38. for (i = 0; i < padctl.socdata->num_phys; i++) {
  39. phy = &padctl.socdata->phys[i];
  40. if (phy->type != type)
  41. continue;
  42. return phy;
  43. }
  44. return NULL;
  45. }
  46. static const struct tegra_xusb_padctl_lane *
  47. tegra_xusb_padctl_find_lane(struct tegra_xusb_padctl *padctl, const char *name)
  48. {
  49. unsigned int i;
  50. for (i = 0; i < padctl->socdata->num_lanes; i++)
  51. if (strcmp(name, padctl->socdata->lanes[i].name) == 0)
  52. return &padctl->socdata->lanes[i];
  53. return NULL;
  54. }
  55. static int
  56. tegra_xusb_padctl_group_parse_dt(struct tegra_xusb_padctl *padctl,
  57. struct tegra_xusb_padctl_group *group,
  58. ofnode node)
  59. {
  60. unsigned int i;
  61. int len, ret;
  62. group->name = ofnode_get_name(node);
  63. len = ofnode_read_string_count(node, "nvidia,lanes");
  64. if (len < 0) {
  65. pr_err("failed to parse \"nvidia,lanes\" property");
  66. return -EINVAL;
  67. }
  68. group->num_pins = len;
  69. for (i = 0; i < group->num_pins; i++) {
  70. ret = ofnode_read_string_index(node, "nvidia,lanes", i,
  71. &group->pins[i]);
  72. if (ret) {
  73. pr_err("failed to read string from \"nvidia,lanes\" property");
  74. return -EINVAL;
  75. }
  76. }
  77. group->num_pins = len;
  78. ret = ofnode_read_string_index(node, "nvidia,function", 0,
  79. &group->func);
  80. if (ret) {
  81. pr_err("failed to parse \"nvidia,func\" property");
  82. return -EINVAL;
  83. }
  84. group->iddq = ofnode_read_u32_default(node, "nvidia,iddq", -1);
  85. return 0;
  86. }
  87. static int tegra_xusb_padctl_find_function(struct tegra_xusb_padctl *padctl,
  88. const char *name)
  89. {
  90. unsigned int i;
  91. for (i = 0; i < padctl->socdata->num_functions; i++)
  92. if (strcmp(name, padctl->socdata->functions[i]) == 0)
  93. return i;
  94. return -ENOENT;
  95. }
  96. static int
  97. tegra_xusb_padctl_lane_find_function(struct tegra_xusb_padctl *padctl,
  98. const struct tegra_xusb_padctl_lane *lane,
  99. const char *name)
  100. {
  101. unsigned int i;
  102. int func;
  103. func = tegra_xusb_padctl_find_function(padctl, name);
  104. if (func < 0)
  105. return func;
  106. for (i = 0; i < lane->num_funcs; i++)
  107. if (lane->funcs[i] == func)
  108. return i;
  109. return -ENOENT;
  110. }
  111. static int
  112. tegra_xusb_padctl_group_apply(struct tegra_xusb_padctl *padctl,
  113. const struct tegra_xusb_padctl_group *group)
  114. {
  115. unsigned int i;
  116. for (i = 0; i < group->num_pins; i++) {
  117. const struct tegra_xusb_padctl_lane *lane;
  118. unsigned int func;
  119. u32 value;
  120. lane = tegra_xusb_padctl_find_lane(padctl, group->pins[i]);
  121. if (!lane) {
  122. pr_err("no lane for pin %s", group->pins[i]);
  123. continue;
  124. }
  125. func = tegra_xusb_padctl_lane_find_function(padctl, lane,
  126. group->func);
  127. if (func < 0) {
  128. pr_err("function %s invalid for lane %s: %d",
  129. group->func, lane->name, func);
  130. continue;
  131. }
  132. value = padctl_readl(padctl, lane->offset);
  133. /* set pin function */
  134. value &= ~(lane->mask << lane->shift);
  135. value |= func << lane->shift;
  136. /*
  137. * Set IDDQ if supported on the lane and specified in the
  138. * configuration.
  139. */
  140. if (lane->iddq > 0 && group->iddq >= 0) {
  141. if (group->iddq != 0)
  142. value &= ~(1 << lane->iddq);
  143. else
  144. value |= 1 << lane->iddq;
  145. }
  146. padctl_writel(padctl, value, lane->offset);
  147. }
  148. return 0;
  149. }
  150. static int
  151. tegra_xusb_padctl_config_apply(struct tegra_xusb_padctl *padctl,
  152. struct tegra_xusb_padctl_config *config)
  153. {
  154. unsigned int i;
  155. for (i = 0; i < config->num_groups; i++) {
  156. const struct tegra_xusb_padctl_group *group;
  157. int err;
  158. group = &config->groups[i];
  159. err = tegra_xusb_padctl_group_apply(padctl, group);
  160. if (err < 0) {
  161. pr_err("failed to apply group %s: %d",
  162. group->name, err);
  163. continue;
  164. }
  165. }
  166. return 0;
  167. }
  168. static int
  169. tegra_xusb_padctl_config_parse_dt(struct tegra_xusb_padctl *padctl,
  170. struct tegra_xusb_padctl_config *config,
  171. ofnode node)
  172. {
  173. ofnode subnode;
  174. config->name = ofnode_get_name(node);
  175. ofnode_for_each_subnode(subnode, node) {
  176. struct tegra_xusb_padctl_group *group;
  177. int err;
  178. group = &config->groups[config->num_groups];
  179. err = tegra_xusb_padctl_group_parse_dt(padctl, group, subnode);
  180. if (err < 0) {
  181. pr_err("failed to parse group %s", group->name);
  182. return err;
  183. }
  184. config->num_groups++;
  185. }
  186. return 0;
  187. }
  188. static int tegra_xusb_padctl_parse_dt(struct tegra_xusb_padctl *padctl,
  189. ofnode node)
  190. {
  191. ofnode subnode;
  192. int err;
  193. err = ofnode_read_resource(node, 0, &padctl->regs);
  194. if (err < 0) {
  195. pr_err("registers not found");
  196. return err;
  197. }
  198. ofnode_for_each_subnode(subnode, node) {
  199. struct tegra_xusb_padctl_config *config = &padctl->config;
  200. debug("%s: subnode=%s\n", __func__, ofnode_get_name(subnode));
  201. err = tegra_xusb_padctl_config_parse_dt(padctl, config,
  202. subnode);
  203. if (err < 0) {
  204. pr_err("failed to parse entry %s: %d",
  205. config->name, err);
  206. continue;
  207. }
  208. }
  209. debug("%s: done\n", __func__);
  210. return 0;
  211. }
  212. struct tegra_xusb_padctl padctl;
  213. int tegra_xusb_process_nodes(ofnode nodes[], unsigned int count,
  214. const struct tegra_xusb_padctl_soc *socdata)
  215. {
  216. unsigned int i;
  217. int err;
  218. debug("%s: count=%d\n", __func__, count);
  219. for (i = 0; i < count; i++) {
  220. debug("%s: i=%d, node=%p\n", __func__, i, nodes[i].np);
  221. if (!ofnode_is_available(nodes[i]))
  222. continue;
  223. padctl.socdata = socdata;
  224. err = tegra_xusb_padctl_parse_dt(&padctl, nodes[i]);
  225. if (err < 0) {
  226. pr_err("failed to parse DT: %d", err);
  227. continue;
  228. }
  229. /* deassert XUSB padctl reset */
  230. reset_set_enable(PERIPH_ID_XUSB_PADCTL, 0);
  231. err = tegra_xusb_padctl_config_apply(&padctl, &padctl.config);
  232. if (err < 0) {
  233. pr_err("failed to apply pinmux: %d", err);
  234. continue;
  235. }
  236. /* only a single instance is supported */
  237. break;
  238. }
  239. debug("%s: done\n", __func__);
  240. return 0;
  241. }