powergate.c 2.0 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Copyright (c) 2014-2019, NVIDIA CORPORATION. All rights reserved.
  4. */
  5. #include <common.h>
  6. #include <errno.h>
  7. #include <asm/io.h>
  8. #include <asm/types.h>
  9. #include <asm/arch/powergate.h>
  10. #include <asm/arch/tegra.h>
  11. #include <asm/arch-tegra/pmc.h>
  12. #define PWRGATE_TOGGLE 0x30
  13. #define PWRGATE_TOGGLE_START (1 << 8)
  14. #define REMOVE_CLAMPING 0x34
  15. #define PWRGATE_STATUS 0x38
  16. static int tegra_powergate_set(enum tegra_powergate id, bool state)
  17. {
  18. u32 value, mask = state ? (1 << id) : 0, old_mask;
  19. unsigned long start, timeout = 25;
  20. value = tegra_pmc_readl(PWRGATE_STATUS);
  21. old_mask = value & (1 << id);
  22. if (mask == old_mask)
  23. return 0;
  24. tegra_pmc_writel(PWRGATE_TOGGLE_START | id, PWRGATE_TOGGLE);
  25. start = get_timer(0);
  26. while (get_timer(start) < timeout) {
  27. value = tegra_pmc_readl(PWRGATE_STATUS);
  28. if ((value & (1 << id)) == mask)
  29. return 0;
  30. }
  31. return -ETIMEDOUT;
  32. }
  33. int tegra_powergate_power_on(enum tegra_powergate id)
  34. {
  35. return tegra_powergate_set(id, true);
  36. }
  37. int tegra_powergate_power_off(enum tegra_powergate id)
  38. {
  39. return tegra_powergate_set(id, false);
  40. }
  41. static int tegra_powergate_remove_clamping(enum tegra_powergate id)
  42. {
  43. unsigned long value;
  44. /*
  45. * The REMOVE_CLAMPING register has the bits for the PCIE and VDEC
  46. * partitions reversed. This was originally introduced on Tegra20 but
  47. * has since been carried forward for backwards-compatibility.
  48. */
  49. if (id == TEGRA_POWERGATE_VDEC)
  50. value = 1 << TEGRA_POWERGATE_PCIE;
  51. else if (id == TEGRA_POWERGATE_PCIE)
  52. value = 1 << TEGRA_POWERGATE_VDEC;
  53. else
  54. value = 1 << id;
  55. tegra_pmc_writel(value, REMOVE_CLAMPING);
  56. return 0;
  57. }
  58. int tegra_powergate_sequence_power_up(enum tegra_powergate id,
  59. enum periph_id periph)
  60. {
  61. int err;
  62. reset_set_enable(periph, 1);
  63. err = tegra_powergate_power_on(id);
  64. if (err < 0)
  65. return err;
  66. clock_enable(periph);
  67. udelay(10);
  68. err = tegra_powergate_remove_clamping(id);
  69. if (err < 0)
  70. return err;
  71. udelay(10);
  72. reset_set_enable(periph, 0);
  73. return 0;
  74. }