ap.c 5.2 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2010-2015
  4. * NVIDIA Corporation <www.nvidia.com>
  5. */
  6. /* Tegra AP (Application Processor) code */
  7. #include <common.h>
  8. #include <linux/bug.h>
  9. #include <asm/io.h>
  10. #include <asm/arch/gp_padctrl.h>
  11. #include <asm/arch/mc.h>
  12. #include <asm/arch-tegra/ap.h>
  13. #include <asm/arch-tegra/clock.h>
  14. #include <asm/arch-tegra/fuse.h>
  15. #include <asm/arch-tegra/pmc.h>
  16. #include <asm/arch-tegra/scu.h>
  17. #include <asm/arch-tegra/tegra.h>
  18. #include <asm/arch-tegra/warmboot.h>
  19. int tegra_get_chip(void)
  20. {
  21. int rev;
  22. struct apb_misc_gp_ctlr *gp =
  23. (struct apb_misc_gp_ctlr *)NV_PA_APB_MISC_GP_BASE;
  24. /*
  25. * This is undocumented, Chip ID is bits 15:8 of the register
  26. * APB_MISC + 0x804, and has value 0x20 for Tegra20, 0x30 for
  27. * Tegra30, 0x35 for T114, and 0x40 for Tegra124.
  28. */
  29. rev = (readl(&gp->hidrev) & HIDREV_CHIPID_MASK) >> HIDREV_CHIPID_SHIFT;
  30. debug("%s: CHIPID is 0x%02X\n", __func__, rev);
  31. return rev;
  32. }
  33. int tegra_get_sku_info(void)
  34. {
  35. int sku_id;
  36. struct fuse_regs *fuse = (struct fuse_regs *)NV_PA_FUSE_BASE;
  37. sku_id = readl(&fuse->sku_info) & 0xff;
  38. debug("%s: SKU info byte is 0x%02X\n", __func__, sku_id);
  39. return sku_id;
  40. }
  41. int tegra_get_chip_sku(void)
  42. {
  43. uint sku_id, chip_id;
  44. chip_id = tegra_get_chip();
  45. sku_id = tegra_get_sku_info();
  46. switch (chip_id) {
  47. case CHIPID_TEGRA20:
  48. switch (sku_id) {
  49. case SKU_ID_T20_7:
  50. case SKU_ID_T20:
  51. return TEGRA_SOC_T20;
  52. case SKU_ID_T25SE:
  53. case SKU_ID_AP25:
  54. case SKU_ID_T25:
  55. case SKU_ID_AP25E:
  56. case SKU_ID_T25E:
  57. return TEGRA_SOC_T25;
  58. }
  59. break;
  60. case CHIPID_TEGRA30:
  61. switch (sku_id) {
  62. case SKU_ID_T33:
  63. case SKU_ID_T30:
  64. case SKU_ID_TM30MQS_P_A3:
  65. default:
  66. return TEGRA_SOC_T30;
  67. }
  68. break;
  69. case CHIPID_TEGRA114:
  70. switch (sku_id) {
  71. case SKU_ID_T114_ENG:
  72. case SKU_ID_T114_1:
  73. default:
  74. return TEGRA_SOC_T114;
  75. }
  76. break;
  77. case CHIPID_TEGRA124:
  78. switch (sku_id) {
  79. case SKU_ID_T124_ENG:
  80. default:
  81. return TEGRA_SOC_T124;
  82. }
  83. break;
  84. case CHIPID_TEGRA210:
  85. switch (sku_id) {
  86. case SKU_ID_T210_ENG:
  87. default:
  88. return TEGRA_SOC_T210;
  89. }
  90. break;
  91. }
  92. /* unknown chip/sku id */
  93. printf("%s: ERROR: UNKNOWN CHIP/SKU ID COMBO (0x%02X/0x%02X)\n",
  94. __func__, chip_id, sku_id);
  95. return TEGRA_SOC_UNKNOWN;
  96. }
  97. #ifndef CONFIG_ARM64
  98. static void enable_scu(void)
  99. {
  100. struct scu_ctlr *scu = (struct scu_ctlr *)NV_PA_ARM_PERIPHBASE;
  101. u32 reg;
  102. /* Only enable the SCU on T20/T25 */
  103. if (tegra_get_chip() != CHIPID_TEGRA20)
  104. return;
  105. /* If SCU already setup/enabled, return */
  106. if (readl(&scu->scu_ctrl) & SCU_CTRL_ENABLE)
  107. return;
  108. /* Invalidate all ways for all processors */
  109. writel(0xFFFF, &scu->scu_inv_all);
  110. /* Enable SCU - bit 0 */
  111. reg = readl(&scu->scu_ctrl);
  112. reg |= SCU_CTRL_ENABLE;
  113. writel(reg, &scu->scu_ctrl);
  114. }
  115. static u32 get_odmdata(void)
  116. {
  117. /*
  118. * ODMDATA is stored in the BCT in IRAM by the BootROM.
  119. * The BCT start and size are stored in the BIT in IRAM.
  120. * Read the data @ bct_start + (bct_size - 12). This works
  121. * on BCTs for currently supported SoCs, which are locked down.
  122. * If this changes in new chips, we can revisit this algorithm.
  123. */
  124. unsigned long bct_start;
  125. u32 odmdata;
  126. bct_start = readl(NV_PA_BASE_SRAM + NVBOOTINFOTABLE_BCTPTR);
  127. odmdata = readl(bct_start + BCT_ODMDATA_OFFSET);
  128. return odmdata;
  129. }
  130. static void init_pmc_scratch(void)
  131. {
  132. struct pmc_ctlr *const pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
  133. u32 odmdata;
  134. int i;
  135. /* SCRATCH0 is initialized by the boot ROM and shouldn't be cleared */
  136. #if defined(CONFIG_TEGRA_SUPPORT_NON_SECURE)
  137. if (!tegra_cpu_is_non_secure())
  138. #endif
  139. {
  140. for (i = 0; i < 23; i++)
  141. writel(0, &pmc->pmc_scratch1 + i);
  142. }
  143. /* ODMDATA is for kernel use to determine RAM size, LP config, etc. */
  144. odmdata = get_odmdata();
  145. writel(odmdata, &pmc->pmc_scratch20);
  146. }
  147. #ifdef CONFIG_ARMV7_SECURE_RESERVE_SIZE
  148. void protect_secure_section(void)
  149. {
  150. struct mc_ctlr *mc = (struct mc_ctlr *)NV_PA_MC_BASE;
  151. /* Must be MB aligned */
  152. BUILD_BUG_ON(CONFIG_ARMV7_SECURE_BASE & 0xFFFFF);
  153. BUILD_BUG_ON(CONFIG_ARMV7_SECURE_RESERVE_SIZE & 0xFFFFF);
  154. writel(CONFIG_ARMV7_SECURE_BASE, &mc->mc_security_cfg0);
  155. writel(CONFIG_ARMV7_SECURE_RESERVE_SIZE >> 20, &mc->mc_security_cfg1);
  156. }
  157. #endif
  158. #if defined(CONFIG_ARMV7_NONSEC)
  159. static void smmu_flush(struct mc_ctlr *mc)
  160. {
  161. (void)readl(&mc->mc_smmu_config);
  162. }
  163. static void smmu_enable(void)
  164. {
  165. struct mc_ctlr *mc = (struct mc_ctlr *)NV_PA_MC_BASE;
  166. u32 value;
  167. /*
  168. * Enable translation for all clients since access to this register
  169. * is restricted to TrustZone-secured requestors. The kernel will use
  170. * the per-SWGROUP enable bits to enable or disable translations.
  171. */
  172. writel(0xffffffff, &mc->mc_smmu_translation_enable_0);
  173. writel(0xffffffff, &mc->mc_smmu_translation_enable_1);
  174. writel(0xffffffff, &mc->mc_smmu_translation_enable_2);
  175. writel(0xffffffff, &mc->mc_smmu_translation_enable_3);
  176. /*
  177. * Enable SMMU globally since access to this register is restricted
  178. * to TrustZone-secured requestors.
  179. */
  180. value = readl(&mc->mc_smmu_config);
  181. value |= TEGRA_MC_SMMU_CONFIG_ENABLE;
  182. writel(value, &mc->mc_smmu_config);
  183. smmu_flush(mc);
  184. }
  185. #else
  186. static void smmu_enable(void)
  187. {
  188. }
  189. #endif
  190. void s_init(void)
  191. {
  192. /* Init PMC scratch memory */
  193. init_pmc_scratch();
  194. enable_scu();
  195. /* init the cache */
  196. config_cache();
  197. /* enable SMMU */
  198. smmu_enable();
  199. }
  200. #endif