nand.h 34 KB

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  1. /*
  2. * linux/include/linux/mtd/nand.h
  3. *
  4. * Copyright © 2000-2010 David Woodhouse <dwmw2@infradead.org>
  5. * Steven J. Hill <sjhill@realitydiluted.com>
  6. * Thomas Gleixner <tglx@linutronix.de>
  7. *
  8. * SPDX-License-Identifier: GPL-2.0+
  9. *
  10. * Info:
  11. * Contains standard defines and IDs for NAND flash devices
  12. *
  13. * Changelog:
  14. * See git changelog.
  15. */
  16. #ifndef __LINUX_MTD_NAND_H
  17. #define __LINUX_MTD_NAND_H
  18. #include "config.h"
  19. #include "linux/compat.h"
  20. #include "linux/mtd/mtd.h"
  21. #include "linux/mtd/flashchip.h"
  22. #include "linux/mtd/bbm.h"
  23. struct mtd_info;
  24. struct nand_flash_dev;
  25. /* Scan and identify a NAND device */
  26. extern int nand_scan(struct mtd_info *mtd, int max_chips);
  27. /*
  28. * Separate phases of nand_scan(), allowing board driver to intervene
  29. * and override command or ECC setup according to flash type.
  30. */
  31. extern int nand_scan_ident(struct mtd_info *mtd, int max_chips,
  32. struct nand_flash_dev *table);
  33. extern int nand_scan_tail(struct mtd_info *mtd);
  34. /* Free resources held by the NAND device */
  35. extern void nand_release(struct mtd_info *mtd);
  36. /* Internal helper for board drivers which need to override command function */
  37. extern void nand_wait_ready(struct mtd_info *mtd);
  38. /*
  39. * This constant declares the max. oobsize / page, which
  40. * is supported now. If you add a chip with bigger oobsize/page
  41. * adjust this accordingly.
  42. */
  43. #define NAND_MAX_OOBSIZE 1216
  44. #define NAND_MAX_PAGESIZE 16384
  45. /*
  46. * Constants for hardware specific CLE/ALE/NCE function
  47. *
  48. * These are bits which can be or'ed to set/clear multiple
  49. * bits in one go.
  50. */
  51. /* Select the chip by setting nCE to low */
  52. #define NAND_NCE 0x01
  53. /* Select the command latch by setting CLE to high */
  54. #define NAND_CLE 0x02
  55. /* Select the address latch by setting ALE to high */
  56. #define NAND_ALE 0x04
  57. #define NAND_CTRL_CLE (NAND_NCE | NAND_CLE)
  58. #define NAND_CTRL_ALE (NAND_NCE | NAND_ALE)
  59. #define NAND_CTRL_CHANGE 0x80
  60. /*
  61. * Standard NAND flash commands
  62. */
  63. #define NAND_CMD_READ0 0
  64. #define NAND_CMD_READ1 1
  65. #define NAND_CMD_RNDOUT 5
  66. #define NAND_CMD_PAGEPROG 0x10
  67. #define NAND_CMD_READOOB 0x50
  68. #define NAND_CMD_ERASE1 0x60
  69. #define NAND_CMD_STATUS 0x70
  70. #define NAND_CMD_SEQIN 0x80
  71. #define NAND_CMD_RNDIN 0x85
  72. #define NAND_CMD_READID 0x90
  73. #define NAND_CMD_ERASE2 0xd0
  74. #define NAND_CMD_PARAM 0xec
  75. #define NAND_CMD_GET_FEATURES 0xee
  76. #define NAND_CMD_SET_FEATURES 0xef
  77. #define NAND_CMD_RESET 0xff
  78. #define NAND_CMD_LOCK 0x2a
  79. #define NAND_CMD_UNLOCK1 0x23
  80. #define NAND_CMD_UNLOCK2 0x24
  81. /* Extended commands for large page devices */
  82. #define NAND_CMD_READSTART 0x30
  83. #define NAND_CMD_RNDOUTSTART 0xE0
  84. #define NAND_CMD_CACHEDPROG 0x15
  85. /* Extended commands for AG-AND device */
  86. /*
  87. * Note: the command for NAND_CMD_DEPLETE1 is really 0x00 but
  88. * there is no way to distinguish that from NAND_CMD_READ0
  89. * until the remaining sequence of commands has been completed
  90. * so add a high order bit and mask it off in the command.
  91. */
  92. #define NAND_CMD_DEPLETE1 0x100
  93. #define NAND_CMD_DEPLETE2 0x38
  94. #define NAND_CMD_STATUS_MULTI 0x71
  95. #define NAND_CMD_STATUS_ERROR 0x72
  96. /* multi-bank error status (banks 0-3) */
  97. #define NAND_CMD_STATUS_ERROR0 0x73
  98. #define NAND_CMD_STATUS_ERROR1 0x74
  99. #define NAND_CMD_STATUS_ERROR2 0x75
  100. #define NAND_CMD_STATUS_ERROR3 0x76
  101. #define NAND_CMD_STATUS_RESET 0x7f
  102. #define NAND_CMD_STATUS_CLEAR 0xff
  103. #define NAND_CMD_NONE -1
  104. /* Status bits */
  105. #define NAND_STATUS_FAIL 0x01
  106. #define NAND_STATUS_FAIL_N1 0x02
  107. #define NAND_STATUS_TRUE_READY 0x20
  108. #define NAND_STATUS_READY 0x40
  109. #define NAND_STATUS_WP 0x80
  110. /*
  111. * Constants for ECC_MODES
  112. */
  113. typedef enum {
  114. NAND_ECC_NONE,
  115. NAND_ECC_SOFT,
  116. NAND_ECC_HW,
  117. NAND_ECC_HW_SYNDROME,
  118. NAND_ECC_HW_OOB_FIRST,
  119. NAND_ECC_SOFT_BCH,
  120. } nand_ecc_modes_t;
  121. /*
  122. * Constants for Hardware ECC
  123. */
  124. /* Reset Hardware ECC for read */
  125. #define NAND_ECC_READ 0
  126. /* Reset Hardware ECC for write */
  127. #define NAND_ECC_WRITE 1
  128. /* Enable Hardware ECC before syndrome is read back from flash */
  129. #define NAND_ECC_READSYN 2
  130. /* Bit mask for flags passed to do_nand_read_ecc */
  131. #define NAND_GET_DEVICE 0x80
  132. /*
  133. * Option constants for bizarre disfunctionality and real
  134. * features.
  135. */
  136. /* Buswidth is 16 bit */
  137. #define NAND_BUSWIDTH_16 0x00000002
  138. /* Device supports partial programming without padding */
  139. #define NAND_NO_PADDING 0x00000004
  140. /* Chip has cache program function */
  141. #define NAND_CACHEPRG 0x00000008
  142. /* Chip has copy back function */
  143. #define NAND_COPYBACK 0x00000010
  144. /*
  145. * Chip requires ready check on read (for auto-incremented sequential read).
  146. * True only for small page devices; large page devices do not support
  147. * autoincrement.
  148. */
  149. #define NAND_NEED_READRDY 0x00000100
  150. /* Chip does not allow subpage writes */
  151. #define NAND_NO_SUBPAGE_WRITE 0x00000200
  152. /* Device is one of 'new' xD cards that expose fake nand command set */
  153. #define NAND_BROKEN_XD 0x00000400
  154. /* Device behaves just like nand, but is readonly */
  155. #define NAND_ROM 0x00000800
  156. /* Device supports subpage reads */
  157. #define NAND_SUBPAGE_READ 0x00001000
  158. /* Options valid for Samsung large page devices */
  159. #define NAND_SAMSUNG_LP_OPTIONS NAND_CACHEPRG
  160. /* Macros to identify the above */
  161. #define NAND_HAS_CACHEPROG(chip) ((chip->options & NAND_CACHEPRG))
  162. #define NAND_HAS_SUBPAGE_READ(chip) ((chip->options & NAND_SUBPAGE_READ))
  163. /* Non chip related options */
  164. /* This option skips the bbt scan during initialization. */
  165. #define NAND_SKIP_BBTSCAN 0x00010000
  166. /*
  167. * This option is defined if the board driver allocates its own buffers
  168. * (e.g. because it needs them DMA-coherent).
  169. */
  170. #define NAND_OWN_BUFFERS 0x00020000
  171. /* Chip may not exist, so silence any errors in scan */
  172. #define NAND_SCAN_SILENT_NODEV 0x00040000
  173. /*
  174. * Autodetect nand buswidth with readid/onfi.
  175. * This suppose the driver will configure the hardware in 8 bits mode
  176. * when calling nand_scan_ident, and update its configuration
  177. * before calling nand_scan_tail.
  178. */
  179. #define NAND_BUSWIDTH_AUTO 0x00080000
  180. /* Options set by nand scan */
  181. /* bbt has already been read */
  182. #define NAND_BBT_SCANNED 0x40000000
  183. /* Nand scan has allocated controller struct */
  184. #define NAND_CONTROLLER_ALLOC 0x80000000
  185. /* Cell info constants */
  186. #define NAND_CI_CHIPNR_MSK 0x03
  187. #define NAND_CI_CELLTYPE_MSK 0x0C
  188. #define NAND_CI_CELLTYPE_SHIFT 2
  189. /* Keep gcc happy */
  190. struct nand_chip;
  191. /* ONFI features */
  192. #define ONFI_FEATURE_16_BIT_BUS (1 << 0)
  193. #define ONFI_FEATURE_EXT_PARAM_PAGE (1 << 7)
  194. /* ONFI timing mode, used in both asynchronous and synchronous mode */
  195. #define ONFI_TIMING_MODE_0 (1 << 0)
  196. #define ONFI_TIMING_MODE_1 (1 << 1)
  197. #define ONFI_TIMING_MODE_2 (1 << 2)
  198. #define ONFI_TIMING_MODE_3 (1 << 3)
  199. #define ONFI_TIMING_MODE_4 (1 << 4)
  200. #define ONFI_TIMING_MODE_5 (1 << 5)
  201. #define ONFI_TIMING_MODE_UNKNOWN (1 << 6)
  202. /* ONFI feature address */
  203. #define ONFI_FEATURE_ADDR_TIMING_MODE 0x1
  204. /* Vendor-specific feature address (Micron) */
  205. #define ONFI_FEATURE_ADDR_READ_RETRY 0x89
  206. /* ONFI subfeature parameters length */
  207. #define ONFI_SUBFEATURE_PARAM_LEN 4
  208. /* ONFI optional commands SET/GET FEATURES supported? */
  209. #define ONFI_OPT_CMD_SET_GET_FEATURES (1 << 2)
  210. struct nand_onfi_params {
  211. /* rev info and features block */
  212. /* 'O' 'N' 'F' 'I' */
  213. u8 sig[4];
  214. __le16 revision;
  215. __le16 features;
  216. __le16 opt_cmd;
  217. u8 reserved0[2];
  218. __le16 ext_param_page_length; /* since ONFI 2.1 */
  219. u8 num_of_param_pages; /* since ONFI 2.1 */
  220. u8 reserved1[17];
  221. /* manufacturer information block */
  222. char manufacturer[12];
  223. char model[20];
  224. u8 jedec_id;
  225. __le16 date_code;
  226. u8 reserved2[13];
  227. /* memory organization block */
  228. __le32 byte_per_page;
  229. __le16 spare_bytes_per_page;
  230. __le32 data_bytes_per_ppage;
  231. __le16 spare_bytes_per_ppage;
  232. __le32 pages_per_block;
  233. __le32 blocks_per_lun;
  234. u8 lun_count;
  235. u8 addr_cycles;
  236. u8 bits_per_cell;
  237. __le16 bb_per_lun;
  238. __le16 block_endurance;
  239. u8 guaranteed_good_blocks;
  240. __le16 guaranteed_block_endurance;
  241. u8 programs_per_page;
  242. u8 ppage_attr;
  243. u8 ecc_bits;
  244. u8 interleaved_bits;
  245. u8 interleaved_ops;
  246. u8 reserved3[13];
  247. /* electrical parameter block */
  248. u8 io_pin_capacitance_max;
  249. __le16 async_timing_mode;
  250. __le16 program_cache_timing_mode;
  251. __le16 t_prog;
  252. __le16 t_bers;
  253. __le16 t_r;
  254. __le16 t_ccs;
  255. __le16 src_sync_timing_mode;
  256. __le16 src_ssync_features;
  257. __le16 clk_pin_capacitance_typ;
  258. __le16 io_pin_capacitance_typ;
  259. __le16 input_pin_capacitance_typ;
  260. u8 input_pin_capacitance_max;
  261. u8 driver_strength_support;
  262. __le16 t_int_r;
  263. __le16 t_ald;
  264. u8 reserved4[7];
  265. /* vendor */
  266. __le16 vendor_revision;
  267. u8 vendor[88];
  268. __le16 crc;
  269. } __packed;
  270. #define ONFI_CRC_BASE 0x4F4E
  271. /* Extended ECC information Block Definition (since ONFI 2.1) */
  272. struct onfi_ext_ecc_info {
  273. u8 ecc_bits;
  274. u8 codeword_size;
  275. __le16 bb_per_lun;
  276. __le16 block_endurance;
  277. u8 reserved[2];
  278. } __packed;
  279. #define ONFI_SECTION_TYPE_0 0 /* Unused section. */
  280. #define ONFI_SECTION_TYPE_1 1 /* for additional sections. */
  281. #define ONFI_SECTION_TYPE_2 2 /* for ECC information. */
  282. struct onfi_ext_section {
  283. u8 type;
  284. u8 length;
  285. } __packed;
  286. #define ONFI_EXT_SECTION_MAX 8
  287. /* Extended Parameter Page Definition (since ONFI 2.1) */
  288. struct onfi_ext_param_page {
  289. __le16 crc;
  290. u8 sig[4]; /* 'E' 'P' 'P' 'S' */
  291. u8 reserved0[10];
  292. struct onfi_ext_section sections[ONFI_EXT_SECTION_MAX];
  293. /*
  294. * The actual size of the Extended Parameter Page is in
  295. * @ext_param_page_length of nand_onfi_params{}.
  296. * The following are the variable length sections.
  297. * So we do not add any fields below. Please see the ONFI spec.
  298. */
  299. } __packed;
  300. struct nand_onfi_vendor_micron {
  301. u8 two_plane_read;
  302. u8 read_cache;
  303. u8 read_unique_id;
  304. u8 dq_imped;
  305. u8 dq_imped_num_settings;
  306. u8 dq_imped_feat_addr;
  307. u8 rb_pulldown_strength;
  308. u8 rb_pulldown_strength_feat_addr;
  309. u8 rb_pulldown_strength_num_settings;
  310. u8 otp_mode;
  311. u8 otp_page_start;
  312. u8 otp_data_prot_addr;
  313. u8 otp_num_pages;
  314. u8 otp_feat_addr;
  315. u8 read_retry_options;
  316. u8 reserved[72];
  317. u8 param_revision;
  318. } __packed;
  319. struct jedec_ecc_info {
  320. u8 ecc_bits;
  321. u8 codeword_size;
  322. __le16 bb_per_lun;
  323. __le16 block_endurance;
  324. u8 reserved[2];
  325. } __packed;
  326. /* JEDEC features */
  327. #define JEDEC_FEATURE_16_BIT_BUS (1 << 0)
  328. struct nand_jedec_params {
  329. /* rev info and features block */
  330. /* 'J' 'E' 'S' 'D' */
  331. u8 sig[4];
  332. __le16 revision;
  333. __le16 features;
  334. u8 opt_cmd[3];
  335. __le16 sec_cmd;
  336. u8 num_of_param_pages;
  337. u8 reserved0[18];
  338. /* manufacturer information block */
  339. char manufacturer[12];
  340. char model[20];
  341. u8 jedec_id[6];
  342. u8 reserved1[10];
  343. /* memory organization block */
  344. __le32 byte_per_page;
  345. __le16 spare_bytes_per_page;
  346. u8 reserved2[6];
  347. __le32 pages_per_block;
  348. __le32 blocks_per_lun;
  349. u8 lun_count;
  350. u8 addr_cycles;
  351. u8 bits_per_cell;
  352. u8 programs_per_page;
  353. u8 multi_plane_addr;
  354. u8 multi_plane_op_attr;
  355. u8 reserved3[38];
  356. /* electrical parameter block */
  357. __le16 async_sdr_speed_grade;
  358. __le16 toggle_ddr_speed_grade;
  359. __le16 sync_ddr_speed_grade;
  360. u8 async_sdr_features;
  361. u8 toggle_ddr_features;
  362. u8 sync_ddr_features;
  363. __le16 t_prog;
  364. __le16 t_bers;
  365. __le16 t_r;
  366. __le16 t_r_multi_plane;
  367. __le16 t_ccs;
  368. __le16 io_pin_capacitance_typ;
  369. __le16 input_pin_capacitance_typ;
  370. __le16 clk_pin_capacitance_typ;
  371. u8 driver_strength_support;
  372. __le16 t_ald;
  373. u8 reserved4[36];
  374. /* ECC and endurance block */
  375. u8 guaranteed_good_blocks;
  376. __le16 guaranteed_block_endurance;
  377. struct jedec_ecc_info ecc_info[4];
  378. u8 reserved5[29];
  379. /* reserved */
  380. u8 reserved6[148];
  381. /* vendor */
  382. __le16 vendor_rev_num;
  383. u8 reserved7[88];
  384. /* CRC for Parameter Page */
  385. __le16 crc;
  386. } __packed;
  387. /**
  388. * struct nand_hw_control - Control structure for hardware controller (e.g ECC generator) shared among independent devices
  389. * @lock: protection lock
  390. * @active: the mtd device which holds the controller currently
  391. * @wq: wait queue to sleep on if a NAND operation is in
  392. * progress used instead of the per chip wait queue
  393. * when a hw controller is available.
  394. */
  395. struct nand_hw_control {
  396. spinlock_t lock;
  397. struct nand_chip *active;
  398. };
  399. /**
  400. * struct nand_ecc_ctrl - Control structure for ECC
  401. * @mode: ECC mode
  402. * @steps: number of ECC steps per page
  403. * @size: data bytes per ECC step
  404. * @bytes: ECC bytes per step
  405. * @strength: max number of correctible bits per ECC step
  406. * @total: total number of ECC bytes per page
  407. * @prepad: padding information for syndrome based ECC generators
  408. * @postpad: padding information for syndrome based ECC generators
  409. * @layout: ECC layout control struct pointer
  410. * @priv: pointer to private ECC control data
  411. * @hwctl: function to control hardware ECC generator. Must only
  412. * be provided if an hardware ECC is available
  413. * @calculate: function for ECC calculation or readback from ECC hardware
  414. * @correct: function for ECC correction, matching to ECC generator (sw/hw)
  415. * @read_page_raw: function to read a raw page without ECC. This function
  416. * should hide the specific layout used by the ECC
  417. * controller and always return contiguous in-band and
  418. * out-of-band data even if they're not stored
  419. * contiguously on the NAND chip (e.g.
  420. * NAND_ECC_HW_SYNDROME interleaves in-band and
  421. * out-of-band data).
  422. * @write_page_raw: function to write a raw page without ECC. This function
  423. * should hide the specific layout used by the ECC
  424. * controller and consider the passed data as contiguous
  425. * in-band and out-of-band data. ECC controller is
  426. * responsible for doing the appropriate transformations
  427. * to adapt to its specific layout (e.g.
  428. * NAND_ECC_HW_SYNDROME interleaves in-band and
  429. * out-of-band data).
  430. * @read_page: function to read a page according to the ECC generator
  431. * requirements; returns maximum number of bitflips corrected in
  432. * any single ECC step, 0 if bitflips uncorrectable, -EIO hw error
  433. * @read_subpage: function to read parts of the page covered by ECC;
  434. * returns same as read_page()
  435. * @write_subpage: function to write parts of the page covered by ECC.
  436. * @write_page: function to write a page according to the ECC generator
  437. * requirements.
  438. * @write_oob_raw: function to write chip OOB data without ECC
  439. * @read_oob_raw: function to read chip OOB data without ECC
  440. * @read_oob: function to read chip OOB data
  441. * @write_oob: function to write chip OOB data
  442. */
  443. struct nand_ecc_ctrl {
  444. nand_ecc_modes_t mode;
  445. int steps;
  446. int size;
  447. int bytes;
  448. int total;
  449. int strength;
  450. int prepad;
  451. int postpad;
  452. struct nand_ecclayout *layout;
  453. void *priv;
  454. void (*hwctl)(struct mtd_info *mtd, int mode);
  455. int (*calculate)(struct mtd_info *mtd, const uint8_t *dat,
  456. uint8_t *ecc_code);
  457. int (*correct)(struct mtd_info *mtd, uint8_t *dat, uint8_t *read_ecc,
  458. uint8_t *calc_ecc);
  459. int (*read_page_raw)(struct mtd_info *mtd, struct nand_chip *chip,
  460. uint8_t *buf, int oob_required, int page);
  461. int (*write_page_raw)(struct mtd_info *mtd, struct nand_chip *chip,
  462. const uint8_t *buf, int oob_required);
  463. int (*read_page)(struct mtd_info *mtd, struct nand_chip *chip,
  464. uint8_t *buf, int oob_required, int page);
  465. int (*read_subpage)(struct mtd_info *mtd, struct nand_chip *chip,
  466. uint32_t offs, uint32_t len, uint8_t *buf, int page);
  467. int (*write_subpage)(struct mtd_info *mtd, struct nand_chip *chip,
  468. uint32_t offset, uint32_t data_len,
  469. const uint8_t *data_buf, int oob_required);
  470. int (*write_page)(struct mtd_info *mtd, struct nand_chip *chip,
  471. const uint8_t *buf, int oob_required);
  472. int (*write_oob_raw)(struct mtd_info *mtd, struct nand_chip *chip,
  473. int page);
  474. int (*read_oob_raw)(struct mtd_info *mtd, struct nand_chip *chip,
  475. int page);
  476. int (*read_oob)(struct mtd_info *mtd, struct nand_chip *chip, int page);
  477. int (*write_oob)(struct mtd_info *mtd, struct nand_chip *chip,
  478. int page);
  479. };
  480. /**
  481. * struct nand_buffers - buffer structure for read/write
  482. * @ecccalc: buffer pointer for calculated ECC, size is oobsize.
  483. * @ecccode: buffer pointer for ECC read from flash, size is oobsize.
  484. * @databuf: buffer pointer for data, size is (page size + oobsize).
  485. *
  486. * Do not change the order of buffers. databuf and oobrbuf must be in
  487. * consecutive order.
  488. */
  489. struct nand_buffers {
  490. uint8_t ecccalc[ALIGN(NAND_MAX_OOBSIZE, ARCH_DMA_MINALIGN)];
  491. uint8_t ecccode[ALIGN(NAND_MAX_OOBSIZE, ARCH_DMA_MINALIGN)];
  492. uint8_t databuf[ALIGN(NAND_MAX_PAGESIZE + NAND_MAX_OOBSIZE,
  493. ARCH_DMA_MINALIGN)];
  494. };
  495. /**
  496. * struct nand_chip - NAND Private Flash Chip Data
  497. * @IO_ADDR_R: [BOARDSPECIFIC] address to read the 8 I/O lines of the
  498. * flash device
  499. * @IO_ADDR_W: [BOARDSPECIFIC] address to write the 8 I/O lines of the
  500. * flash device.
  501. * @read_byte: [REPLACEABLE] read one byte from the chip
  502. * @read_word: [REPLACEABLE] read one word from the chip
  503. * @write_byte: [REPLACEABLE] write a single byte to the chip on the
  504. * low 8 I/O lines
  505. * @write_buf: [REPLACEABLE] write data from the buffer to the chip
  506. * @read_buf: [REPLACEABLE] read data from the chip into the buffer
  507. * @select_chip: [REPLACEABLE] select chip nr
  508. * @block_bad: [REPLACEABLE] check if a block is bad, using OOB markers
  509. * @block_markbad: [REPLACEABLE] mark a block bad
  510. * @cmd_ctrl: [BOARDSPECIFIC] hardwarespecific function for controlling
  511. * ALE/CLE/nCE. Also used to write command and address
  512. * @init_size: [BOARDSPECIFIC] hardwarespecific function for setting
  513. * mtd->oobsize, mtd->writesize and so on.
  514. * @id_data contains the 8 bytes values of NAND_CMD_READID.
  515. * Return with the bus width.
  516. * @dev_ready: [BOARDSPECIFIC] hardwarespecific function for accessing
  517. * device ready/busy line. If set to NULL no access to
  518. * ready/busy is available and the ready/busy information
  519. * is read from the chip status register.
  520. * @cmdfunc: [REPLACEABLE] hardwarespecific function for writing
  521. * commands to the chip.
  522. * @waitfunc: [REPLACEABLE] hardwarespecific function for wait on
  523. * ready.
  524. * @setup_read_retry: [FLASHSPECIFIC] flash (vendor) specific function for
  525. * setting the read-retry mode. Mostly needed for MLC NAND.
  526. * @ecc: [BOARDSPECIFIC] ECC control structure
  527. * @buffers: buffer structure for read/write
  528. * @hwcontrol: platform-specific hardware control structure
  529. * @erase: [REPLACEABLE] erase function
  530. * @scan_bbt: [REPLACEABLE] function to scan bad block table
  531. * @chip_delay: [BOARDSPECIFIC] chip dependent delay for transferring
  532. * data from array to read regs (tR).
  533. * @state: [INTERN] the current state of the NAND device
  534. * @oob_poi: "poison value buffer," used for laying out OOB data
  535. * before writing
  536. * @page_shift: [INTERN] number of address bits in a page (column
  537. * address bits).
  538. * @phys_erase_shift: [INTERN] number of address bits in a physical eraseblock
  539. * @bbt_erase_shift: [INTERN] number of address bits in a bbt entry
  540. * @chip_shift: [INTERN] number of address bits in one chip
  541. * @options: [BOARDSPECIFIC] various chip options. They can partly
  542. * be set to inform nand_scan about special functionality.
  543. * See the defines for further explanation.
  544. * @bbt_options: [INTERN] bad block specific options. All options used
  545. * here must come from bbm.h. By default, these options
  546. * will be copied to the appropriate nand_bbt_descr's.
  547. * @badblockpos: [INTERN] position of the bad block marker in the oob
  548. * area.
  549. * @badblockbits: [INTERN] minimum number of set bits in a good block's
  550. * bad block marker position; i.e., BBM == 11110111b is
  551. * not bad when badblockbits == 7
  552. * @bits_per_cell: [INTERN] number of bits per cell. i.e., 1 means SLC.
  553. * @ecc_strength_ds: [INTERN] ECC correctability from the datasheet.
  554. * Minimum amount of bit errors per @ecc_step_ds guaranteed
  555. * to be correctable. If unknown, set to zero.
  556. * @ecc_step_ds: [INTERN] ECC step required by the @ecc_strength_ds,
  557. * also from the datasheet. It is the recommended ECC step
  558. * size, if known; if unknown, set to zero.
  559. * @onfi_timing_mode_default: [INTERN] default ONFI timing mode. This field is
  560. * either deduced from the datasheet if the NAND
  561. * chip is not ONFI compliant or set to 0 if it is
  562. * (an ONFI chip is always configured in mode 0
  563. * after a NAND reset)
  564. * @numchips: [INTERN] number of physical chips
  565. * @chipsize: [INTERN] the size of one chip for multichip arrays
  566. * @pagemask: [INTERN] page number mask = number of (pages / chip) - 1
  567. * @pagebuf: [INTERN] holds the pagenumber which is currently in
  568. * data_buf.
  569. * @pagebuf_bitflips: [INTERN] holds the bitflip count for the page which is
  570. * currently in data_buf.
  571. * @subpagesize: [INTERN] holds the subpagesize
  572. * @onfi_version: [INTERN] holds the chip ONFI version (BCD encoded),
  573. * non 0 if ONFI supported.
  574. * @jedec_version: [INTERN] holds the chip JEDEC version (BCD encoded),
  575. * non 0 if JEDEC supported.
  576. * @onfi_params: [INTERN] holds the ONFI page parameter when ONFI is
  577. * supported, 0 otherwise.
  578. * @jedec_params: [INTERN] holds the JEDEC parameter page when JEDEC is
  579. * supported, 0 otherwise.
  580. * @read_retries: [INTERN] the number of read retry modes supported
  581. * @onfi_set_features: [REPLACEABLE] set the features for ONFI nand
  582. * @onfi_get_features: [REPLACEABLE] get the features for ONFI nand
  583. * @bbt: [INTERN] bad block table pointer
  584. * @bbt_td: [REPLACEABLE] bad block table descriptor for flash
  585. * lookup.
  586. * @bbt_md: [REPLACEABLE] bad block table mirror descriptor
  587. * @badblock_pattern: [REPLACEABLE] bad block scan pattern used for initial
  588. * bad block scan.
  589. * @controller: [REPLACEABLE] a pointer to a hardware controller
  590. * structure which is shared among multiple independent
  591. * devices.
  592. * @priv: [OPTIONAL] pointer to private chip data
  593. * @errstat: [OPTIONAL] hardware specific function to perform
  594. * additional error status checks (determine if errors are
  595. * correctable).
  596. * @write_page: [REPLACEABLE] High-level page write function
  597. */
  598. struct nand_chip {
  599. struct mtd_info mtd;
  600. void __iomem *IO_ADDR_R;
  601. void __iomem *IO_ADDR_W;
  602. uint8_t (*read_byte)(struct mtd_info *mtd);
  603. u16 (*read_word)(struct mtd_info *mtd);
  604. void (*write_byte)(struct mtd_info *mtd, uint8_t byte);
  605. void (*write_buf)(struct mtd_info *mtd, const uint8_t *buf, int len);
  606. void (*read_buf)(struct mtd_info *mtd, uint8_t *buf, int len);
  607. void (*select_chip)(struct mtd_info *mtd, int chip);
  608. int (*block_bad)(struct mtd_info *mtd, loff_t ofs, int getchip);
  609. int (*block_markbad)(struct mtd_info *mtd, loff_t ofs);
  610. void (*cmd_ctrl)(struct mtd_info *mtd, int dat, unsigned int ctrl);
  611. int (*init_size)(struct mtd_info *mtd, struct nand_chip *this,
  612. u8 *id_data);
  613. int (*dev_ready)(struct mtd_info *mtd);
  614. void (*cmdfunc)(struct mtd_info *mtd, unsigned command, int column,
  615. int page_addr);
  616. int(*waitfunc)(struct mtd_info *mtd, struct nand_chip *this);
  617. int (*erase)(struct mtd_info *mtd, int page);
  618. int (*scan_bbt)(struct mtd_info *mtd);
  619. int (*errstat)(struct mtd_info *mtd, struct nand_chip *this, int state,
  620. int status, int page);
  621. int (*write_page)(struct mtd_info *mtd, struct nand_chip *chip,
  622. uint32_t offset, int data_len, const uint8_t *buf,
  623. int oob_required, int page, int cached, int raw);
  624. int (*onfi_set_features)(struct mtd_info *mtd, struct nand_chip *chip,
  625. int feature_addr, uint8_t *subfeature_para);
  626. int (*onfi_get_features)(struct mtd_info *mtd, struct nand_chip *chip,
  627. int feature_addr, uint8_t *subfeature_para);
  628. int (*setup_read_retry)(struct mtd_info *mtd, int retry_mode);
  629. int chip_delay;
  630. unsigned int options;
  631. unsigned int bbt_options;
  632. int page_shift;
  633. int phys_erase_shift;
  634. int bbt_erase_shift;
  635. int chip_shift;
  636. int numchips;
  637. uint64_t chipsize;
  638. int pagemask;
  639. int pagebuf;
  640. unsigned int pagebuf_bitflips;
  641. int subpagesize;
  642. uint8_t bits_per_cell;
  643. uint16_t ecc_strength_ds;
  644. uint16_t ecc_step_ds;
  645. int onfi_timing_mode_default;
  646. int badblockpos;
  647. int badblockbits;
  648. int onfi_version;
  649. int jedec_version;
  650. #ifdef CONFIG_SYS_NAND_ONFI_DETECTION
  651. struct nand_onfi_params onfi_params;
  652. #endif
  653. struct nand_jedec_params jedec_params;
  654. int read_retries;
  655. flstate_t state;
  656. uint8_t *oob_poi;
  657. struct nand_hw_control *controller;
  658. struct nand_ecclayout *ecclayout;
  659. struct nand_ecc_ctrl ecc;
  660. struct nand_buffers *buffers;
  661. struct nand_hw_control hwcontrol;
  662. uint8_t *bbt;
  663. struct nand_bbt_descr *bbt_td;
  664. struct nand_bbt_descr *bbt_md;
  665. struct nand_bbt_descr *badblock_pattern;
  666. void *priv;
  667. };
  668. static inline struct nand_chip *mtd_to_nand(struct mtd_info *mtd)
  669. {
  670. return container_of(mtd, struct nand_chip, mtd);
  671. }
  672. static inline struct mtd_info *nand_to_mtd(struct nand_chip *chip)
  673. {
  674. return &chip->mtd;
  675. }
  676. static inline void *nand_get_controller_data(struct nand_chip *chip)
  677. {
  678. return chip->priv;
  679. }
  680. static inline void nand_set_controller_data(struct nand_chip *chip, void *priv)
  681. {
  682. chip->priv = priv;
  683. }
  684. /*
  685. * NAND Flash Manufacturer ID Codes
  686. */
  687. #define NAND_MFR_TOSHIBA 0x98
  688. #define NAND_MFR_SAMSUNG 0xec
  689. #define NAND_MFR_FUJITSU 0x04
  690. #define NAND_MFR_NATIONAL 0x8f
  691. #define NAND_MFR_RENESAS 0x07
  692. #define NAND_MFR_STMICRO 0x20
  693. #define NAND_MFR_HYNIX 0xad
  694. #define NAND_MFR_MICRON 0x2c
  695. #define NAND_MFR_AMD 0x01
  696. #define NAND_MFR_MACRONIX 0xc2
  697. #define NAND_MFR_EON 0x92
  698. #define NAND_MFR_SANDISK 0x45
  699. #define NAND_MFR_INTEL 0x89
  700. #define NAND_MFR_ATO 0x9b
  701. /* The maximum expected count of bytes in the NAND ID sequence */
  702. #define NAND_MAX_ID_LEN 8
  703. /*
  704. * A helper for defining older NAND chips where the second ID byte fully
  705. * defined the chip, including the geometry (chip size, eraseblock size, page
  706. * size). All these chips have 512 bytes NAND page size.
  707. */
  708. #define LEGACY_ID_NAND(nm, devid, chipsz, erasesz, opts) \
  709. { .name = (nm), {{ .dev_id = (devid) }}, .pagesize = 512, \
  710. .chipsize = (chipsz), .erasesize = (erasesz), .options = (opts) }
  711. /*
  712. * A helper for defining newer chips which report their page size and
  713. * eraseblock size via the extended ID bytes.
  714. *
  715. * The real difference between LEGACY_ID_NAND and EXTENDED_ID_NAND is that with
  716. * EXTENDED_ID_NAND, manufacturers overloaded the same device ID so that the
  717. * device ID now only represented a particular total chip size (and voltage,
  718. * buswidth), and the page size, eraseblock size, and OOB size could vary while
  719. * using the same device ID.
  720. */
  721. #define EXTENDED_ID_NAND(nm, devid, chipsz, opts) \
  722. { .name = (nm), {{ .dev_id = (devid) }}, .chipsize = (chipsz), \
  723. .options = (opts) }
  724. #define NAND_ECC_INFO(_strength, _step) \
  725. { .strength_ds = (_strength), .step_ds = (_step) }
  726. #define NAND_ECC_STRENGTH(type) ((type)->ecc.strength_ds)
  727. #define NAND_ECC_STEP(type) ((type)->ecc.step_ds)
  728. /**
  729. * struct nand_flash_dev - NAND Flash Device ID Structure
  730. * @name: a human-readable name of the NAND chip
  731. * @dev_id: the device ID (the second byte of the full chip ID array)
  732. * @mfr_id: manufecturer ID part of the full chip ID array (refers the same
  733. * memory address as @id[0])
  734. * @dev_id: device ID part of the full chip ID array (refers the same memory
  735. * address as @id[1])
  736. * @id: full device ID array
  737. * @pagesize: size of the NAND page in bytes; if 0, then the real page size (as
  738. * well as the eraseblock size) is determined from the extended NAND
  739. * chip ID array)
  740. * @chipsize: total chip size in MiB
  741. * @erasesize: eraseblock size in bytes (determined from the extended ID if 0)
  742. * @options: stores various chip bit options
  743. * @id_len: The valid length of the @id.
  744. * @oobsize: OOB size
  745. * @ecc: ECC correctability and step information from the datasheet.
  746. * @ecc.strength_ds: The ECC correctability from the datasheet, same as the
  747. * @ecc_strength_ds in nand_chip{}.
  748. * @ecc.step_ds: The ECC step required by the @ecc.strength_ds, same as the
  749. * @ecc_step_ds in nand_chip{}, also from the datasheet.
  750. * For example, the "4bit ECC for each 512Byte" can be set with
  751. * NAND_ECC_INFO(4, 512).
  752. * @onfi_timing_mode_default: the default ONFI timing mode entered after a NAND
  753. * reset. Should be deduced from timings described
  754. * in the datasheet.
  755. *
  756. */
  757. struct nand_flash_dev {
  758. char *name;
  759. union {
  760. struct {
  761. uint8_t mfr_id;
  762. uint8_t dev_id;
  763. };
  764. uint8_t id[NAND_MAX_ID_LEN];
  765. };
  766. unsigned int pagesize;
  767. unsigned int chipsize;
  768. unsigned int erasesize;
  769. unsigned int options;
  770. uint16_t id_len;
  771. uint16_t oobsize;
  772. struct {
  773. uint16_t strength_ds;
  774. uint16_t step_ds;
  775. } ecc;
  776. int onfi_timing_mode_default;
  777. };
  778. /**
  779. * struct nand_manufacturers - NAND Flash Manufacturer ID Structure
  780. * @name: Manufacturer name
  781. * @id: manufacturer ID code of device.
  782. */
  783. struct nand_manufacturers {
  784. int id;
  785. char *name;
  786. };
  787. extern struct nand_flash_dev nand_flash_ids[];
  788. extern struct nand_manufacturers nand_manuf_ids[];
  789. extern int nand_scan_bbt(struct mtd_info *mtd, struct nand_bbt_descr *bd);
  790. extern int nand_default_bbt(struct mtd_info *mtd);
  791. extern int nand_markbad_bbt(struct mtd_info *mtd, loff_t offs);
  792. extern int nand_isreserved_bbt(struct mtd_info *mtd, loff_t offs);
  793. extern int nand_isbad_bbt(struct mtd_info *mtd, loff_t offs, int allowbbt);
  794. extern int nand_erase_nand(struct mtd_info *mtd, struct erase_info *instr,
  795. int allowbbt);
  796. extern int nand_do_read(struct mtd_info *mtd, loff_t from, size_t len,
  797. size_t *retlen, uint8_t *buf);
  798. /*
  799. * Constants for oob configuration
  800. */
  801. #define NAND_SMALL_BADBLOCK_POS 5
  802. #define NAND_LARGE_BADBLOCK_POS 0
  803. /**
  804. * struct platform_nand_chip - chip level device structure
  805. * @nr_chips: max. number of chips to scan for
  806. * @chip_offset: chip number offset
  807. * @nr_partitions: number of partitions pointed to by partitions (or zero)
  808. * @partitions: mtd partition list
  809. * @chip_delay: R/B delay value in us
  810. * @options: Option flags, e.g. 16bit buswidth
  811. * @bbt_options: BBT option flags, e.g. NAND_BBT_USE_FLASH
  812. * @ecclayout: ECC layout info structure
  813. * @part_probe_types: NULL-terminated array of probe types
  814. */
  815. struct platform_nand_chip {
  816. int nr_chips;
  817. int chip_offset;
  818. int nr_partitions;
  819. struct mtd_partition *partitions;
  820. struct nand_ecclayout *ecclayout;
  821. int chip_delay;
  822. unsigned int options;
  823. unsigned int bbt_options;
  824. const char **part_probe_types;
  825. };
  826. /* Keep gcc happy */
  827. struct platform_device;
  828. /**
  829. * struct platform_nand_ctrl - controller level device structure
  830. * @probe: platform specific function to probe/setup hardware
  831. * @remove: platform specific function to remove/teardown hardware
  832. * @hwcontrol: platform specific hardware control structure
  833. * @dev_ready: platform specific function to read ready/busy pin
  834. * @select_chip: platform specific chip select function
  835. * @cmd_ctrl: platform specific function for controlling
  836. * ALE/CLE/nCE. Also used to write command and address
  837. * @write_buf: platform specific function for write buffer
  838. * @read_buf: platform specific function for read buffer
  839. * @read_byte: platform specific function to read one byte from chip
  840. * @priv: private data to transport driver specific settings
  841. *
  842. * All fields are optional and depend on the hardware driver requirements
  843. */
  844. struct platform_nand_ctrl {
  845. int (*probe)(struct platform_device *pdev);
  846. void (*remove)(struct platform_device *pdev);
  847. void (*hwcontrol)(struct mtd_info *mtd, int cmd);
  848. int (*dev_ready)(struct mtd_info *mtd);
  849. void (*select_chip)(struct mtd_info *mtd, int chip);
  850. void (*cmd_ctrl)(struct mtd_info *mtd, int dat, unsigned int ctrl);
  851. void (*write_buf)(struct mtd_info *mtd, const uint8_t *buf, int len);
  852. void (*read_buf)(struct mtd_info *mtd, uint8_t *buf, int len);
  853. unsigned char (*read_byte)(struct mtd_info *mtd);
  854. void *priv;
  855. };
  856. /**
  857. * struct platform_nand_data - container structure for platform-specific data
  858. * @chip: chip level chip structure
  859. * @ctrl: controller level device structure
  860. */
  861. struct platform_nand_data {
  862. struct platform_nand_chip chip;
  863. struct platform_nand_ctrl ctrl;
  864. };
  865. /* Some helpers to access the data structures */
  866. static inline
  867. struct platform_nand_chip *get_platform_nandchip(struct mtd_info *mtd)
  868. {
  869. struct nand_chip *chip = mtd->priv;
  870. return chip->priv;
  871. }
  872. #ifdef CONFIG_SYS_NAND_ONFI_DETECTION
  873. /* return the supported features. */
  874. static inline int onfi_feature(struct nand_chip *chip)
  875. {
  876. return chip->onfi_version ? le16_to_cpu(chip->onfi_params.features) : 0;
  877. }
  878. /* return the supported asynchronous timing mode. */
  879. static inline int onfi_get_async_timing_mode(struct nand_chip *chip)
  880. {
  881. if (!chip->onfi_version)
  882. return ONFI_TIMING_MODE_UNKNOWN;
  883. return le16_to_cpu(chip->onfi_params.async_timing_mode);
  884. }
  885. /* return the supported synchronous timing mode. */
  886. static inline int onfi_get_sync_timing_mode(struct nand_chip *chip)
  887. {
  888. if (!chip->onfi_version)
  889. return ONFI_TIMING_MODE_UNKNOWN;
  890. return le16_to_cpu(chip->onfi_params.src_sync_timing_mode);
  891. }
  892. #endif
  893. /*
  894. * Check if it is a SLC nand.
  895. * The !nand_is_slc() can be used to check the MLC/TLC nand chips.
  896. * We do not distinguish the MLC and TLC now.
  897. */
  898. static inline bool nand_is_slc(struct nand_chip *chip)
  899. {
  900. return chip->bits_per_cell == 1;
  901. }
  902. /**
  903. * Check if the opcode's address should be sent only on the lower 8 bits
  904. * @command: opcode to check
  905. */
  906. static inline int nand_opcode_8bits(unsigned int command)
  907. {
  908. switch (command) {
  909. case NAND_CMD_READID:
  910. case NAND_CMD_PARAM:
  911. case NAND_CMD_GET_FEATURES:
  912. case NAND_CMD_SET_FEATURES:
  913. return 1;
  914. default:
  915. break;
  916. }
  917. return 0;
  918. }
  919. /* return the supported JEDEC features. */
  920. static inline int jedec_feature(struct nand_chip *chip)
  921. {
  922. return chip->jedec_version ? le16_to_cpu(chip->jedec_params.features)
  923. : 0;
  924. }
  925. /* Standard NAND functions from nand_base.c */
  926. void nand_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len);
  927. void nand_write_buf16(struct mtd_info *mtd, const uint8_t *buf, int len);
  928. void nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len);
  929. void nand_read_buf16(struct mtd_info *mtd, uint8_t *buf, int len);
  930. uint8_t nand_read_byte(struct mtd_info *mtd);
  931. /*
  932. * struct nand_sdr_timings - SDR NAND chip timings
  933. *
  934. * This struct defines the timing requirements of a SDR NAND chip.
  935. * These informations can be found in every NAND datasheets and the timings
  936. * meaning are described in the ONFI specifications:
  937. * www.onfi.org/~/media/ONFI/specs/onfi_3_1_spec.pdf (chapter 4.15 Timing
  938. * Parameters)
  939. *
  940. * All these timings are expressed in picoseconds.
  941. */
  942. struct nand_sdr_timings {
  943. u32 tALH_min;
  944. u32 tADL_min;
  945. u32 tALS_min;
  946. u32 tAR_min;
  947. u32 tCEA_max;
  948. u32 tCEH_min;
  949. u32 tCH_min;
  950. u32 tCHZ_max;
  951. u32 tCLH_min;
  952. u32 tCLR_min;
  953. u32 tCLS_min;
  954. u32 tCOH_min;
  955. u32 tCS_min;
  956. u32 tDH_min;
  957. u32 tDS_min;
  958. u32 tFEAT_max;
  959. u32 tIR_min;
  960. u32 tITC_max;
  961. u32 tRC_min;
  962. u32 tREA_max;
  963. u32 tREH_min;
  964. u32 tRHOH_min;
  965. u32 tRHW_min;
  966. u32 tRHZ_max;
  967. u32 tRLOH_min;
  968. u32 tRP_min;
  969. u32 tRR_min;
  970. u64 tRST_max;
  971. u32 tWB_max;
  972. u32 tWC_min;
  973. u32 tWH_min;
  974. u32 tWHR_min;
  975. u32 tWP_min;
  976. u32 tWW_min;
  977. };
  978. /* get timing characteristics from ONFI timing mode. */
  979. const struct nand_sdr_timings *onfi_async_timing_mode_to_sdr_timings(int mode);
  980. #endif /* __LINUX_MTD_NAND_H */