vf610_nfc.c 20 KB

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  1. /*
  2. * Copyright 2009-2015 Freescale Semiconductor, Inc. and others
  3. *
  4. * Description: MPC5125, VF610, MCF54418 and Kinetis K70 Nand driver.
  5. * Ported to U-Boot by Stefan Agner
  6. * Based on RFC driver posted on Kernel Mailing list by Bill Pringlemeir
  7. * Jason ported to M54418TWR and MVFA5.
  8. * Authors: Stefan Agner <stefan.agner@toradex.com>
  9. * Bill Pringlemeir <bpringlemeir@nbsps.com>
  10. * Shaohui Xie <b21989@freescale.com>
  11. * Jason Jin <Jason.jin@freescale.com>
  12. *
  13. * Based on original driver mpc5121_nfc.c.
  14. *
  15. * SPDX-License-Identifier: GPL-2.0+
  16. *
  17. * Limitations:
  18. * - Untested on MPC5125 and M54418.
  19. * - DMA and pipelining not used.
  20. * - 2K pages or less.
  21. * - HW ECC: Only 2K page with 64+ OOB.
  22. * - HW ECC: Only 24 and 32-bit error correction implemented.
  23. */
  24. #include <common.h>
  25. #include <malloc.h>
  26. #include <linux/mtd/mtd.h>
  27. #include <linux/mtd/nand.h>
  28. #include <linux/mtd/partitions.h>
  29. #include <nand.h>
  30. #include <errno.h>
  31. #include <asm/io.h>
  32. /* Register Offsets */
  33. #define NFC_FLASH_CMD1 0x3F00
  34. #define NFC_FLASH_CMD2 0x3F04
  35. #define NFC_COL_ADDR 0x3F08
  36. #define NFC_ROW_ADDR 0x3F0c
  37. #define NFC_ROW_ADDR_INC 0x3F14
  38. #define NFC_FLASH_STATUS1 0x3F18
  39. #define NFC_FLASH_STATUS2 0x3F1c
  40. #define NFC_CACHE_SWAP 0x3F28
  41. #define NFC_SECTOR_SIZE 0x3F2c
  42. #define NFC_FLASH_CONFIG 0x3F30
  43. #define NFC_IRQ_STATUS 0x3F38
  44. /* Addresses for NFC MAIN RAM BUFFER areas */
  45. #define NFC_MAIN_AREA(n) ((n) * 0x1000)
  46. #define PAGE_2K 0x0800
  47. #define OOB_64 0x0040
  48. #define OOB_MAX 0x0100
  49. /*
  50. * NFC_CMD2[CODE] values. See section:
  51. * - 31.4.7 Flash Command Code Description, Vybrid manual
  52. * - 23.8.6 Flash Command Sequencer, MPC5125 manual
  53. *
  54. * Briefly these are bitmasks of controller cycles.
  55. */
  56. #define READ_PAGE_CMD_CODE 0x7EE0
  57. #define READ_ONFI_PARAM_CMD_CODE 0x4860
  58. #define PROGRAM_PAGE_CMD_CODE 0x7FC0
  59. #define ERASE_CMD_CODE 0x4EC0
  60. #define READ_ID_CMD_CODE 0x4804
  61. #define RESET_CMD_CODE 0x4040
  62. #define STATUS_READ_CMD_CODE 0x4068
  63. /* NFC ECC mode define */
  64. #define ECC_BYPASS 0
  65. #define ECC_45_BYTE 6
  66. #define ECC_60_BYTE 7
  67. /*** Register Mask and bit definitions */
  68. /* NFC_FLASH_CMD1 Field */
  69. #define CMD_BYTE2_MASK 0xFF000000
  70. #define CMD_BYTE2_SHIFT 24
  71. /* NFC_FLASH_CM2 Field */
  72. #define CMD_BYTE1_MASK 0xFF000000
  73. #define CMD_BYTE1_SHIFT 24
  74. #define CMD_CODE_MASK 0x00FFFF00
  75. #define CMD_CODE_SHIFT 8
  76. #define BUFNO_MASK 0x00000006
  77. #define BUFNO_SHIFT 1
  78. #define START_BIT (1<<0)
  79. /* NFC_COL_ADDR Field */
  80. #define COL_ADDR_MASK 0x0000FFFF
  81. #define COL_ADDR_SHIFT 0
  82. /* NFC_ROW_ADDR Field */
  83. #define ROW_ADDR_MASK 0x00FFFFFF
  84. #define ROW_ADDR_SHIFT 0
  85. #define ROW_ADDR_CHIP_SEL_RB_MASK 0xF0000000
  86. #define ROW_ADDR_CHIP_SEL_RB_SHIFT 28
  87. #define ROW_ADDR_CHIP_SEL_MASK 0x0F000000
  88. #define ROW_ADDR_CHIP_SEL_SHIFT 24
  89. /* NFC_FLASH_STATUS2 Field */
  90. #define STATUS_BYTE1_MASK 0x000000FF
  91. /* NFC_FLASH_CONFIG Field */
  92. #define CONFIG_ECC_SRAM_ADDR_MASK 0x7FC00000
  93. #define CONFIG_ECC_SRAM_ADDR_SHIFT 22
  94. #define CONFIG_ECC_SRAM_REQ_BIT (1<<21)
  95. #define CONFIG_DMA_REQ_BIT (1<<20)
  96. #define CONFIG_ECC_MODE_MASK 0x000E0000
  97. #define CONFIG_ECC_MODE_SHIFT 17
  98. #define CONFIG_FAST_FLASH_BIT (1<<16)
  99. #define CONFIG_16BIT (1<<7)
  100. #define CONFIG_BOOT_MODE_BIT (1<<6)
  101. #define CONFIG_ADDR_AUTO_INCR_BIT (1<<5)
  102. #define CONFIG_BUFNO_AUTO_INCR_BIT (1<<4)
  103. #define CONFIG_PAGE_CNT_MASK 0xF
  104. #define CONFIG_PAGE_CNT_SHIFT 0
  105. /* NFC_IRQ_STATUS Field */
  106. #define IDLE_IRQ_BIT (1<<29)
  107. #define IDLE_EN_BIT (1<<20)
  108. #define CMD_DONE_CLEAR_BIT (1<<18)
  109. #define IDLE_CLEAR_BIT (1<<17)
  110. #define NFC_TIMEOUT (1000)
  111. /*
  112. * ECC status - seems to consume 8 bytes (double word). The documented
  113. * status byte is located in the lowest byte of the second word (which is
  114. * the 4th or 7th byte depending on endianness).
  115. * Calculate an offset to store the ECC status at the end of the buffer.
  116. */
  117. #define ECC_SRAM_ADDR (PAGE_2K + OOB_MAX - 8)
  118. #define ECC_STATUS 0x4
  119. #define ECC_STATUS_MASK 0x80
  120. #define ECC_STATUS_ERR_COUNT 0x3F
  121. enum vf610_nfc_alt_buf {
  122. ALT_BUF_DATA = 0,
  123. ALT_BUF_ID = 1,
  124. ALT_BUF_STAT = 2,
  125. ALT_BUF_ONFI = 3,
  126. };
  127. struct vf610_nfc {
  128. struct mtd_info *mtd;
  129. struct nand_chip chip;
  130. void __iomem *regs;
  131. uint buf_offset;
  132. int write_sz;
  133. /* Status and ID are in alternate locations. */
  134. enum vf610_nfc_alt_buf alt_buf;
  135. };
  136. #define mtd_to_nfc(_mtd) nand_get_controller_data(mtd_to_nand(_mtd))
  137. #if defined(CONFIG_SYS_NAND_VF610_NFC_45_ECC_BYTES)
  138. #define ECC_HW_MODE ECC_45_BYTE
  139. static struct nand_ecclayout vf610_nfc_ecc = {
  140. .eccbytes = 45,
  141. .eccpos = {19, 20, 21, 22, 23,
  142. 24, 25, 26, 27, 28, 29, 30, 31,
  143. 32, 33, 34, 35, 36, 37, 38, 39,
  144. 40, 41, 42, 43, 44, 45, 46, 47,
  145. 48, 49, 50, 51, 52, 53, 54, 55,
  146. 56, 57, 58, 59, 60, 61, 62, 63},
  147. .oobfree = {
  148. {.offset = 2,
  149. .length = 17} }
  150. };
  151. #elif defined(CONFIG_SYS_NAND_VF610_NFC_60_ECC_BYTES)
  152. #define ECC_HW_MODE ECC_60_BYTE
  153. static struct nand_ecclayout vf610_nfc_ecc = {
  154. .eccbytes = 60,
  155. .eccpos = { 4, 5, 6, 7, 8, 9, 10, 11,
  156. 12, 13, 14, 15, 16, 17, 18, 19,
  157. 20, 21, 22, 23, 24, 25, 26, 27,
  158. 28, 29, 30, 31, 32, 33, 34, 35,
  159. 36, 37, 38, 39, 40, 41, 42, 43,
  160. 44, 45, 46, 47, 48, 49, 50, 51,
  161. 52, 53, 54, 55, 56, 57, 58, 59,
  162. 60, 61, 62, 63 },
  163. .oobfree = {
  164. {.offset = 2,
  165. .length = 2} }
  166. };
  167. #endif
  168. static inline u32 vf610_nfc_read(struct mtd_info *mtd, uint reg)
  169. {
  170. struct vf610_nfc *nfc = mtd_to_nfc(mtd);
  171. return readl(nfc->regs + reg);
  172. }
  173. static inline void vf610_nfc_write(struct mtd_info *mtd, uint reg, u32 val)
  174. {
  175. struct vf610_nfc *nfc = mtd_to_nfc(mtd);
  176. writel(val, nfc->regs + reg);
  177. }
  178. static inline void vf610_nfc_set(struct mtd_info *mtd, uint reg, u32 bits)
  179. {
  180. vf610_nfc_write(mtd, reg, vf610_nfc_read(mtd, reg) | bits);
  181. }
  182. static inline void vf610_nfc_clear(struct mtd_info *mtd, uint reg, u32 bits)
  183. {
  184. vf610_nfc_write(mtd, reg, vf610_nfc_read(mtd, reg) & ~bits);
  185. }
  186. static inline void vf610_nfc_set_field(struct mtd_info *mtd, u32 reg,
  187. u32 mask, u32 shift, u32 val)
  188. {
  189. vf610_nfc_write(mtd, reg,
  190. (vf610_nfc_read(mtd, reg) & (~mask)) | val << shift);
  191. }
  192. static inline void vf610_nfc_memcpy(void *dst, const void *src, size_t n)
  193. {
  194. /*
  195. * Use this accessor for the internal SRAM buffers. On the ARM
  196. * Freescale Vybrid SoC it's known that the driver can treat
  197. * the SRAM buffer as if it's memory. Other platform might need
  198. * to treat the buffers differently.
  199. *
  200. * For the time being, use memcpy
  201. */
  202. memcpy(dst, src, n);
  203. }
  204. /* Clear flags for upcoming command */
  205. static inline void vf610_nfc_clear_status(void __iomem *regbase)
  206. {
  207. void __iomem *reg = regbase + NFC_IRQ_STATUS;
  208. u32 tmp = __raw_readl(reg);
  209. tmp |= CMD_DONE_CLEAR_BIT | IDLE_CLEAR_BIT;
  210. __raw_writel(tmp, reg);
  211. }
  212. /* Wait for complete operation */
  213. static void vf610_nfc_done(struct mtd_info *mtd)
  214. {
  215. struct vf610_nfc *nfc = mtd_to_nfc(mtd);
  216. uint start;
  217. /*
  218. * Barrier is needed after this write. This write need
  219. * to be done before reading the next register the first
  220. * time.
  221. * vf610_nfc_set implicates such a barrier by using writel
  222. * to write to the register.
  223. */
  224. vf610_nfc_set(mtd, NFC_FLASH_CMD2, START_BIT);
  225. start = get_timer(0);
  226. while (!(vf610_nfc_read(mtd, NFC_IRQ_STATUS) & IDLE_IRQ_BIT)) {
  227. if (get_timer(start) > NFC_TIMEOUT) {
  228. printf("Timeout while waiting for IDLE.\n");
  229. return;
  230. }
  231. }
  232. vf610_nfc_clear_status(nfc->regs);
  233. }
  234. static u8 vf610_nfc_get_id(struct mtd_info *mtd, int col)
  235. {
  236. u32 flash_id;
  237. if (col < 4) {
  238. flash_id = vf610_nfc_read(mtd, NFC_FLASH_STATUS1);
  239. flash_id >>= (3 - col) * 8;
  240. } else {
  241. flash_id = vf610_nfc_read(mtd, NFC_FLASH_STATUS2);
  242. flash_id >>= 24;
  243. }
  244. return flash_id & 0xff;
  245. }
  246. static u8 vf610_nfc_get_status(struct mtd_info *mtd)
  247. {
  248. return vf610_nfc_read(mtd, NFC_FLASH_STATUS2) & STATUS_BYTE1_MASK;
  249. }
  250. /* Single command */
  251. static void vf610_nfc_send_command(void __iomem *regbase, u32 cmd_byte1,
  252. u32 cmd_code)
  253. {
  254. void __iomem *reg = regbase + NFC_FLASH_CMD2;
  255. u32 tmp;
  256. vf610_nfc_clear_status(regbase);
  257. tmp = __raw_readl(reg);
  258. tmp &= ~(CMD_BYTE1_MASK | CMD_CODE_MASK | BUFNO_MASK);
  259. tmp |= cmd_byte1 << CMD_BYTE1_SHIFT;
  260. tmp |= cmd_code << CMD_CODE_SHIFT;
  261. __raw_writel(tmp, reg);
  262. }
  263. /* Two commands */
  264. static void vf610_nfc_send_commands(void __iomem *regbase, u32 cmd_byte1,
  265. u32 cmd_byte2, u32 cmd_code)
  266. {
  267. void __iomem *reg = regbase + NFC_FLASH_CMD1;
  268. u32 tmp;
  269. vf610_nfc_send_command(regbase, cmd_byte1, cmd_code);
  270. tmp = __raw_readl(reg);
  271. tmp &= ~CMD_BYTE2_MASK;
  272. tmp |= cmd_byte2 << CMD_BYTE2_SHIFT;
  273. __raw_writel(tmp, reg);
  274. }
  275. static void vf610_nfc_addr_cycle(struct mtd_info *mtd, int column, int page)
  276. {
  277. if (column != -1) {
  278. struct vf610_nfc *nfc = mtd_to_nfc(mtd);
  279. if (nfc->chip.options & NAND_BUSWIDTH_16)
  280. column = column / 2;
  281. vf610_nfc_set_field(mtd, NFC_COL_ADDR, COL_ADDR_MASK,
  282. COL_ADDR_SHIFT, column);
  283. }
  284. if (page != -1)
  285. vf610_nfc_set_field(mtd, NFC_ROW_ADDR, ROW_ADDR_MASK,
  286. ROW_ADDR_SHIFT, page);
  287. }
  288. static inline void vf610_nfc_ecc_mode(struct mtd_info *mtd, int ecc_mode)
  289. {
  290. vf610_nfc_set_field(mtd, NFC_FLASH_CONFIG,
  291. CONFIG_ECC_MODE_MASK,
  292. CONFIG_ECC_MODE_SHIFT, ecc_mode);
  293. }
  294. static inline void vf610_nfc_transfer_size(void __iomem *regbase, int size)
  295. {
  296. __raw_writel(size, regbase + NFC_SECTOR_SIZE);
  297. }
  298. /* Send command to NAND chip */
  299. static void vf610_nfc_command(struct mtd_info *mtd, unsigned command,
  300. int column, int page)
  301. {
  302. struct vf610_nfc *nfc = mtd_to_nfc(mtd);
  303. int trfr_sz = nfc->chip.options & NAND_BUSWIDTH_16 ? 1 : 0;
  304. nfc->buf_offset = max(column, 0);
  305. nfc->alt_buf = ALT_BUF_DATA;
  306. switch (command) {
  307. case NAND_CMD_SEQIN:
  308. /* Use valid column/page from preread... */
  309. vf610_nfc_addr_cycle(mtd, column, page);
  310. nfc->buf_offset = 0;
  311. /*
  312. * SEQIN => data => PAGEPROG sequence is done by the controller
  313. * hence we do not need to issue the command here...
  314. */
  315. return;
  316. case NAND_CMD_PAGEPROG:
  317. trfr_sz += nfc->write_sz;
  318. vf610_nfc_ecc_mode(mtd, ECC_HW_MODE);
  319. vf610_nfc_transfer_size(nfc->regs, trfr_sz);
  320. vf610_nfc_send_commands(nfc->regs, NAND_CMD_SEQIN,
  321. command, PROGRAM_PAGE_CMD_CODE);
  322. break;
  323. case NAND_CMD_RESET:
  324. vf610_nfc_transfer_size(nfc->regs, 0);
  325. vf610_nfc_send_command(nfc->regs, command, RESET_CMD_CODE);
  326. break;
  327. case NAND_CMD_READOOB:
  328. trfr_sz += mtd->oobsize;
  329. column = mtd->writesize;
  330. vf610_nfc_transfer_size(nfc->regs, trfr_sz);
  331. vf610_nfc_send_commands(nfc->regs, NAND_CMD_READ0,
  332. NAND_CMD_READSTART, READ_PAGE_CMD_CODE);
  333. vf610_nfc_addr_cycle(mtd, column, page);
  334. vf610_nfc_ecc_mode(mtd, ECC_BYPASS);
  335. break;
  336. case NAND_CMD_READ0:
  337. trfr_sz += mtd->writesize + mtd->oobsize;
  338. vf610_nfc_transfer_size(nfc->regs, trfr_sz);
  339. vf610_nfc_ecc_mode(mtd, ECC_HW_MODE);
  340. vf610_nfc_send_commands(nfc->regs, NAND_CMD_READ0,
  341. NAND_CMD_READSTART, READ_PAGE_CMD_CODE);
  342. vf610_nfc_addr_cycle(mtd, column, page);
  343. break;
  344. case NAND_CMD_PARAM:
  345. nfc->alt_buf = ALT_BUF_ONFI;
  346. trfr_sz = 3 * sizeof(struct nand_onfi_params);
  347. vf610_nfc_transfer_size(nfc->regs, trfr_sz);
  348. vf610_nfc_send_command(nfc->regs, NAND_CMD_PARAM,
  349. READ_ONFI_PARAM_CMD_CODE);
  350. vf610_nfc_set_field(mtd, NFC_ROW_ADDR, ROW_ADDR_MASK,
  351. ROW_ADDR_SHIFT, column);
  352. vf610_nfc_ecc_mode(mtd, ECC_BYPASS);
  353. break;
  354. case NAND_CMD_ERASE1:
  355. vf610_nfc_transfer_size(nfc->regs, 0);
  356. vf610_nfc_send_commands(nfc->regs, command,
  357. NAND_CMD_ERASE2, ERASE_CMD_CODE);
  358. vf610_nfc_addr_cycle(mtd, column, page);
  359. break;
  360. case NAND_CMD_READID:
  361. nfc->alt_buf = ALT_BUF_ID;
  362. nfc->buf_offset = 0;
  363. vf610_nfc_transfer_size(nfc->regs, 0);
  364. vf610_nfc_send_command(nfc->regs, command, READ_ID_CMD_CODE);
  365. vf610_nfc_set_field(mtd, NFC_ROW_ADDR, ROW_ADDR_MASK,
  366. ROW_ADDR_SHIFT, column);
  367. break;
  368. case NAND_CMD_STATUS:
  369. nfc->alt_buf = ALT_BUF_STAT;
  370. vf610_nfc_transfer_size(nfc->regs, 0);
  371. vf610_nfc_send_command(nfc->regs, command, STATUS_READ_CMD_CODE);
  372. break;
  373. default:
  374. return;
  375. }
  376. vf610_nfc_done(mtd);
  377. nfc->write_sz = 0;
  378. }
  379. /* Read data from NFC buffers */
  380. static void vf610_nfc_read_buf(struct mtd_info *mtd, u_char *buf, int len)
  381. {
  382. struct vf610_nfc *nfc = mtd_to_nfc(mtd);
  383. uint c = nfc->buf_offset;
  384. /* Alternate buffers are only supported through read_byte */
  385. if (nfc->alt_buf)
  386. return;
  387. vf610_nfc_memcpy(buf, nfc->regs + NFC_MAIN_AREA(0) + c, len);
  388. nfc->buf_offset += len;
  389. }
  390. /* Write data to NFC buffers */
  391. static void vf610_nfc_write_buf(struct mtd_info *mtd, const uint8_t *buf,
  392. int len)
  393. {
  394. struct vf610_nfc *nfc = mtd_to_nfc(mtd);
  395. uint c = nfc->buf_offset;
  396. uint l;
  397. l = min_t(uint, len, mtd->writesize + mtd->oobsize - c);
  398. vf610_nfc_memcpy(nfc->regs + NFC_MAIN_AREA(0) + c, buf, l);
  399. nfc->write_sz += l;
  400. nfc->buf_offset += l;
  401. }
  402. /* Read byte from NFC buffers */
  403. static uint8_t vf610_nfc_read_byte(struct mtd_info *mtd)
  404. {
  405. struct vf610_nfc *nfc = mtd_to_nfc(mtd);
  406. u8 tmp;
  407. uint c = nfc->buf_offset;
  408. switch (nfc->alt_buf) {
  409. case ALT_BUF_ID:
  410. tmp = vf610_nfc_get_id(mtd, c);
  411. break;
  412. case ALT_BUF_STAT:
  413. tmp = vf610_nfc_get_status(mtd);
  414. break;
  415. #ifdef __LITTLE_ENDIAN
  416. case ALT_BUF_ONFI:
  417. /* Reverse byte since the controller uses big endianness */
  418. c = nfc->buf_offset ^ 0x3;
  419. /* fall-through */
  420. #endif
  421. default:
  422. tmp = *((u8 *)(nfc->regs + NFC_MAIN_AREA(0) + c));
  423. break;
  424. }
  425. nfc->buf_offset++;
  426. return tmp;
  427. }
  428. /* Read word from NFC buffers */
  429. static u16 vf610_nfc_read_word(struct mtd_info *mtd)
  430. {
  431. u16 tmp;
  432. vf610_nfc_read_buf(mtd, (u_char *)&tmp, sizeof(tmp));
  433. return tmp;
  434. }
  435. /* If not provided, upper layers apply a fixed delay. */
  436. static int vf610_nfc_dev_ready(struct mtd_info *mtd)
  437. {
  438. /* NFC handles R/B internally; always ready. */
  439. return 1;
  440. }
  441. /*
  442. * This function supports Vybrid only (MPC5125 would have full RB and four CS)
  443. */
  444. static void vf610_nfc_select_chip(struct mtd_info *mtd, int chip)
  445. {
  446. #ifdef CONFIG_VF610
  447. u32 tmp = vf610_nfc_read(mtd, NFC_ROW_ADDR);
  448. tmp &= ~(ROW_ADDR_CHIP_SEL_RB_MASK | ROW_ADDR_CHIP_SEL_MASK);
  449. if (chip >= 0) {
  450. tmp |= 1 << ROW_ADDR_CHIP_SEL_RB_SHIFT;
  451. tmp |= (1 << chip) << ROW_ADDR_CHIP_SEL_SHIFT;
  452. }
  453. vf610_nfc_write(mtd, NFC_ROW_ADDR, tmp);
  454. #endif
  455. }
  456. /* Count the number of 0's in buff upto max_bits */
  457. static inline int count_written_bits(uint8_t *buff, int size, int max_bits)
  458. {
  459. uint32_t *buff32 = (uint32_t *)buff;
  460. int k, written_bits = 0;
  461. for (k = 0; k < (size / 4); k++) {
  462. written_bits += hweight32(~buff32[k]);
  463. if (written_bits > max_bits)
  464. break;
  465. }
  466. return written_bits;
  467. }
  468. static inline int vf610_nfc_correct_data(struct mtd_info *mtd, uint8_t *dat,
  469. uint8_t *oob, int page)
  470. {
  471. struct vf610_nfc *nfc = mtd_to_nfc(mtd);
  472. u32 ecc_status_off = NFC_MAIN_AREA(0) + ECC_SRAM_ADDR + ECC_STATUS;
  473. u8 ecc_status;
  474. u8 ecc_count;
  475. int flips;
  476. int flips_threshold = nfc->chip.ecc.strength / 2;
  477. ecc_status = vf610_nfc_read(mtd, ecc_status_off) & 0xff;
  478. ecc_count = ecc_status & ECC_STATUS_ERR_COUNT;
  479. if (!(ecc_status & ECC_STATUS_MASK))
  480. return ecc_count;
  481. /* Read OOB without ECC unit enabled */
  482. vf610_nfc_command(mtd, NAND_CMD_READOOB, 0, page);
  483. vf610_nfc_read_buf(mtd, oob, mtd->oobsize);
  484. /*
  485. * On an erased page, bit count (including OOB) should be zero or
  486. * at least less then half of the ECC strength.
  487. */
  488. flips = count_written_bits(dat, nfc->chip.ecc.size, flips_threshold);
  489. flips += count_written_bits(oob, mtd->oobsize, flips_threshold);
  490. if (unlikely(flips > flips_threshold))
  491. return -EINVAL;
  492. /* Erased page. */
  493. memset(dat, 0xff, nfc->chip.ecc.size);
  494. memset(oob, 0xff, mtd->oobsize);
  495. return flips;
  496. }
  497. static int vf610_nfc_read_page(struct mtd_info *mtd, struct nand_chip *chip,
  498. uint8_t *buf, int oob_required, int page)
  499. {
  500. int eccsize = chip->ecc.size;
  501. int stat;
  502. vf610_nfc_read_buf(mtd, buf, eccsize);
  503. if (oob_required)
  504. vf610_nfc_read_buf(mtd, chip->oob_poi, mtd->oobsize);
  505. stat = vf610_nfc_correct_data(mtd, buf, chip->oob_poi, page);
  506. if (stat < 0) {
  507. mtd->ecc_stats.failed++;
  508. return 0;
  509. } else {
  510. mtd->ecc_stats.corrected += stat;
  511. return stat;
  512. }
  513. }
  514. /*
  515. * ECC will be calculated automatically
  516. */
  517. static int vf610_nfc_write_page(struct mtd_info *mtd, struct nand_chip *chip,
  518. const uint8_t *buf, int oob_required)
  519. {
  520. struct vf610_nfc *nfc = mtd_to_nfc(mtd);
  521. vf610_nfc_write_buf(mtd, buf, mtd->writesize);
  522. if (oob_required)
  523. vf610_nfc_write_buf(mtd, chip->oob_poi, mtd->oobsize);
  524. /* Always write whole page including OOB due to HW ECC */
  525. nfc->write_sz = mtd->writesize + mtd->oobsize;
  526. return 0;
  527. }
  528. struct vf610_nfc_config {
  529. int hardware_ecc;
  530. int width;
  531. int flash_bbt;
  532. };
  533. static int vf610_nfc_nand_init(int devnum, void __iomem *addr)
  534. {
  535. struct mtd_info *mtd;
  536. struct nand_chip *chip;
  537. struct vf610_nfc *nfc;
  538. int err = 0;
  539. struct vf610_nfc_config cfg = {
  540. .hardware_ecc = 1,
  541. #ifdef CONFIG_SYS_NAND_BUSWIDTH_16BIT
  542. .width = 16,
  543. #else
  544. .width = 8,
  545. #endif
  546. .flash_bbt = 1,
  547. };
  548. nfc = malloc(sizeof(*nfc));
  549. if (!nfc) {
  550. printf(KERN_ERR "%s: Memory exhausted!\n", __func__);
  551. return -ENOMEM;
  552. }
  553. chip = &nfc->chip;
  554. nfc->regs = addr;
  555. mtd = nand_to_mtd(chip);
  556. nand_set_controller_data(chip, nfc);
  557. if (cfg.width == 16)
  558. chip->options |= NAND_BUSWIDTH_16;
  559. chip->dev_ready = vf610_nfc_dev_ready;
  560. chip->cmdfunc = vf610_nfc_command;
  561. chip->read_byte = vf610_nfc_read_byte;
  562. chip->read_word = vf610_nfc_read_word;
  563. chip->read_buf = vf610_nfc_read_buf;
  564. chip->write_buf = vf610_nfc_write_buf;
  565. chip->select_chip = vf610_nfc_select_chip;
  566. chip->options |= NAND_NO_SUBPAGE_WRITE;
  567. chip->ecc.size = PAGE_2K;
  568. /* Set configuration register. */
  569. vf610_nfc_clear(mtd, NFC_FLASH_CONFIG, CONFIG_16BIT);
  570. vf610_nfc_clear(mtd, NFC_FLASH_CONFIG, CONFIG_ADDR_AUTO_INCR_BIT);
  571. vf610_nfc_clear(mtd, NFC_FLASH_CONFIG, CONFIG_BUFNO_AUTO_INCR_BIT);
  572. vf610_nfc_clear(mtd, NFC_FLASH_CONFIG, CONFIG_BOOT_MODE_BIT);
  573. vf610_nfc_clear(mtd, NFC_FLASH_CONFIG, CONFIG_DMA_REQ_BIT);
  574. vf610_nfc_set(mtd, NFC_FLASH_CONFIG, CONFIG_FAST_FLASH_BIT);
  575. /* Disable virtual pages, only one elementary transfer unit */
  576. vf610_nfc_set_field(mtd, NFC_FLASH_CONFIG, CONFIG_PAGE_CNT_MASK,
  577. CONFIG_PAGE_CNT_SHIFT, 1);
  578. /* first scan to find the device and get the page size */
  579. if (nand_scan_ident(mtd, CONFIG_SYS_MAX_NAND_DEVICE, NULL)) {
  580. err = -ENXIO;
  581. goto error;
  582. }
  583. if (cfg.width == 16)
  584. vf610_nfc_set(mtd, NFC_FLASH_CONFIG, CONFIG_16BIT);
  585. /* Bad block options. */
  586. if (cfg.flash_bbt)
  587. chip->bbt_options = NAND_BBT_USE_FLASH | NAND_BBT_NO_OOB |
  588. NAND_BBT_CREATE;
  589. /* Single buffer only, max 256 OOB minus ECC status */
  590. if (mtd->writesize + mtd->oobsize > PAGE_2K + OOB_MAX - 8) {
  591. dev_err(nfc->dev, "Unsupported flash page size\n");
  592. err = -ENXIO;
  593. goto error;
  594. }
  595. if (cfg.hardware_ecc) {
  596. if (mtd->writesize != PAGE_2K && mtd->oobsize < 64) {
  597. dev_err(nfc->dev, "Unsupported flash with hwecc\n");
  598. err = -ENXIO;
  599. goto error;
  600. }
  601. if (chip->ecc.size != mtd->writesize) {
  602. dev_err(nfc->dev, "ecc size: %d\n", chip->ecc.size);
  603. dev_err(nfc->dev, "Step size needs to be page size\n");
  604. err = -ENXIO;
  605. goto error;
  606. }
  607. /* Current HW ECC layouts only use 64 bytes of OOB */
  608. if (mtd->oobsize > 64)
  609. mtd->oobsize = 64;
  610. /* propagate ecc.layout to mtd_info */
  611. mtd->ecclayout = chip->ecc.layout;
  612. chip->ecc.read_page = vf610_nfc_read_page;
  613. chip->ecc.write_page = vf610_nfc_write_page;
  614. chip->ecc.mode = NAND_ECC_HW;
  615. chip->ecc.size = PAGE_2K;
  616. chip->ecc.layout = &vf610_nfc_ecc;
  617. #if defined(CONFIG_SYS_NAND_VF610_NFC_45_ECC_BYTES)
  618. chip->ecc.strength = 24;
  619. chip->ecc.bytes = 45;
  620. #elif defined(CONFIG_SYS_NAND_VF610_NFC_60_ECC_BYTES)
  621. chip->ecc.strength = 32;
  622. chip->ecc.bytes = 60;
  623. #endif
  624. /* Set ECC_STATUS offset */
  625. vf610_nfc_set_field(mtd, NFC_FLASH_CONFIG,
  626. CONFIG_ECC_SRAM_ADDR_MASK,
  627. CONFIG_ECC_SRAM_ADDR_SHIFT,
  628. ECC_SRAM_ADDR >> 3);
  629. /* Enable ECC status in SRAM */
  630. vf610_nfc_set(mtd, NFC_FLASH_CONFIG, CONFIG_ECC_SRAM_REQ_BIT);
  631. }
  632. /* second phase scan */
  633. err = nand_scan_tail(mtd);
  634. if (err)
  635. return err;
  636. err = nand_register(devnum, mtd);
  637. if (err)
  638. return err;
  639. return 0;
  640. error:
  641. return err;
  642. }
  643. void board_nand_init(void)
  644. {
  645. int err = vf610_nfc_nand_init(0, (void __iomem *)CONFIG_SYS_NAND_BASE);
  646. if (err)
  647. printf("VF610 NAND init failed (err %d)\n", err);
  648. }