tegra_nand.c 25 KB

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  1. /*
  2. * Copyright (c) 2011 The Chromium OS Authors.
  3. * (C) Copyright 2011 NVIDIA Corporation <www.nvidia.com>
  4. * (C) Copyright 2006 Detlev Zundel, dzu@denx.de
  5. * (C) Copyright 2006 DENX Software Engineering
  6. *
  7. * SPDX-License-Identifier: GPL-2.0+
  8. */
  9. #include <common.h>
  10. #include <asm/io.h>
  11. #include <memalign.h>
  12. #include <nand.h>
  13. #include <asm/arch/clock.h>
  14. #include <asm/arch/funcmux.h>
  15. #include <asm/arch-tegra/clk_rst.h>
  16. #include <asm/errno.h>
  17. #include <asm/gpio.h>
  18. #include <fdtdec.h>
  19. #include <bouncebuf.h>
  20. #include "tegra_nand.h"
  21. DECLARE_GLOBAL_DATA_PTR;
  22. #define NAND_CMD_TIMEOUT_MS 10
  23. #define SKIPPED_SPARE_BYTES 4
  24. /* ECC bytes to be generated for tag data */
  25. #define TAG_ECC_BYTES 4
  26. /* 64 byte oob block info for large page (== 2KB) device
  27. *
  28. * OOB flash layout for Tegra with Reed-Solomon 4 symbol correct ECC:
  29. * Skipped bytes(4)
  30. * Main area Ecc(36)
  31. * Tag data(20)
  32. * Tag data Ecc(4)
  33. *
  34. * Yaffs2 will use 16 tag bytes.
  35. */
  36. static struct nand_ecclayout eccoob = {
  37. .eccbytes = 36,
  38. .eccpos = {
  39. 4, 5, 6, 7, 8, 9, 10, 11, 12,
  40. 13, 14, 15, 16, 17, 18, 19, 20, 21,
  41. 22, 23, 24, 25, 26, 27, 28, 29, 30,
  42. 31, 32, 33, 34, 35, 36, 37, 38, 39,
  43. },
  44. .oobavail = 20,
  45. .oobfree = {
  46. {
  47. .offset = 40,
  48. .length = 20,
  49. },
  50. }
  51. };
  52. enum {
  53. ECC_OK,
  54. ECC_TAG_ERROR = 1 << 0,
  55. ECC_DATA_ERROR = 1 << 1
  56. };
  57. /* Timing parameters */
  58. enum {
  59. FDT_NAND_MAX_TRP_TREA,
  60. FDT_NAND_TWB,
  61. FDT_NAND_MAX_TCR_TAR_TRR,
  62. FDT_NAND_TWHR,
  63. FDT_NAND_MAX_TCS_TCH_TALS_TALH,
  64. FDT_NAND_TWH,
  65. FDT_NAND_TWP,
  66. FDT_NAND_TRH,
  67. FDT_NAND_TADL,
  68. FDT_NAND_TIMING_COUNT
  69. };
  70. /* Information about an attached NAND chip */
  71. struct fdt_nand {
  72. struct nand_ctlr *reg;
  73. int enabled; /* 1 to enable, 0 to disable */
  74. struct gpio_desc wp_gpio; /* write-protect GPIO */
  75. s32 width; /* bit width, normally 8 */
  76. u32 timing[FDT_NAND_TIMING_COUNT];
  77. };
  78. struct nand_drv {
  79. struct nand_ctlr *reg;
  80. struct fdt_nand config;
  81. };
  82. static struct nand_drv nand_ctrl;
  83. static struct mtd_info *our_mtd;
  84. static struct nand_chip nand_chip[CONFIG_SYS_MAX_NAND_DEVICE];
  85. /**
  86. * Wait for command completion
  87. *
  88. * @param reg nand_ctlr structure
  89. * @return
  90. * 1 - Command completed
  91. * 0 - Timeout
  92. */
  93. static int nand_waitfor_cmd_completion(struct nand_ctlr *reg)
  94. {
  95. u32 reg_val;
  96. int running;
  97. int i;
  98. for (i = 0; i < NAND_CMD_TIMEOUT_MS * 1000; i++) {
  99. if ((readl(&reg->command) & CMD_GO) ||
  100. !(readl(&reg->status) & STATUS_RBSY0) ||
  101. !(readl(&reg->isr) & ISR_IS_CMD_DONE)) {
  102. udelay(1);
  103. continue;
  104. }
  105. reg_val = readl(&reg->dma_mst_ctrl);
  106. /*
  107. * If DMA_MST_CTRL_EN_A_ENABLE or DMA_MST_CTRL_EN_B_ENABLE
  108. * is set, that means DMA engine is running.
  109. *
  110. * Then we have to wait until DMA_MST_CTRL_IS_DMA_DONE
  111. * is cleared, indicating DMA transfer completion.
  112. */
  113. running = reg_val & (DMA_MST_CTRL_EN_A_ENABLE |
  114. DMA_MST_CTRL_EN_B_ENABLE);
  115. if (!running || (reg_val & DMA_MST_CTRL_IS_DMA_DONE))
  116. return 1;
  117. udelay(1);
  118. }
  119. return 0;
  120. }
  121. /**
  122. * Read one byte from the chip
  123. *
  124. * @param mtd MTD device structure
  125. * @return data byte
  126. *
  127. * Read function for 8bit bus-width
  128. */
  129. static uint8_t read_byte(struct mtd_info *mtd)
  130. {
  131. struct nand_chip *chip = mtd_to_nand(mtd);
  132. struct nand_drv *info;
  133. info = (struct nand_drv *)nand_get_controller_data(chip);
  134. writel(CMD_GO | CMD_PIO | CMD_RX | CMD_CE0 | CMD_A_VALID,
  135. &info->reg->command);
  136. if (!nand_waitfor_cmd_completion(info->reg))
  137. printf("Command timeout\n");
  138. return (uint8_t)readl(&info->reg->resp);
  139. }
  140. /**
  141. * Read len bytes from the chip into a buffer
  142. *
  143. * @param mtd MTD device structure
  144. * @param buf buffer to store data to
  145. * @param len number of bytes to read
  146. *
  147. * Read function for 8bit bus-width
  148. */
  149. static void read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
  150. {
  151. int i, s;
  152. unsigned int reg;
  153. struct nand_chip *chip = mtd_to_nand(mtd);
  154. struct nand_drv *info = (struct nand_drv *)nand_get_controller_data(chip);
  155. for (i = 0; i < len; i += 4) {
  156. s = (len - i) > 4 ? 4 : len - i;
  157. writel(CMD_PIO | CMD_RX | CMD_A_VALID | CMD_CE0 |
  158. ((s - 1) << CMD_TRANS_SIZE_SHIFT) | CMD_GO,
  159. &info->reg->command);
  160. if (!nand_waitfor_cmd_completion(info->reg))
  161. puts("Command timeout during read_buf\n");
  162. reg = readl(&info->reg->resp);
  163. memcpy(buf + i, &reg, s);
  164. }
  165. }
  166. /**
  167. * Check NAND status to see if it is ready or not
  168. *
  169. * @param mtd MTD device structure
  170. * @return
  171. * 1 - ready
  172. * 0 - not ready
  173. */
  174. static int nand_dev_ready(struct mtd_info *mtd)
  175. {
  176. struct nand_chip *chip = mtd_to_nand(mtd);
  177. int reg_val;
  178. struct nand_drv *info;
  179. info = (struct nand_drv *)nand_get_controller_data(chip);
  180. reg_val = readl(&info->reg->status);
  181. if (reg_val & STATUS_RBSY0)
  182. return 1;
  183. else
  184. return 0;
  185. }
  186. /* Dummy implementation: we don't support multiple chips */
  187. static void nand_select_chip(struct mtd_info *mtd, int chipnr)
  188. {
  189. switch (chipnr) {
  190. case -1:
  191. case 0:
  192. break;
  193. default:
  194. BUG();
  195. }
  196. }
  197. /**
  198. * Clear all interrupt status bits
  199. *
  200. * @param reg nand_ctlr structure
  201. */
  202. static void nand_clear_interrupt_status(struct nand_ctlr *reg)
  203. {
  204. u32 reg_val;
  205. /* Clear interrupt status */
  206. reg_val = readl(&reg->isr);
  207. writel(reg_val, &reg->isr);
  208. }
  209. /**
  210. * Send command to NAND device
  211. *
  212. * @param mtd MTD device structure
  213. * @param command the command to be sent
  214. * @param column the column address for this command, -1 if none
  215. * @param page_addr the page address for this command, -1 if none
  216. */
  217. static void nand_command(struct mtd_info *mtd, unsigned int command,
  218. int column, int page_addr)
  219. {
  220. struct nand_chip *chip = mtd_to_nand(mtd);
  221. struct nand_drv *info;
  222. info = (struct nand_drv *)nand_get_controller_data(chip);
  223. /*
  224. * Write out the command to the device.
  225. *
  226. * Only command NAND_CMD_RESET or NAND_CMD_READID will come
  227. * here before mtd->writesize is initialized.
  228. */
  229. /* Emulate NAND_CMD_READOOB */
  230. if (command == NAND_CMD_READOOB) {
  231. assert(mtd->writesize != 0);
  232. column += mtd->writesize;
  233. command = NAND_CMD_READ0;
  234. }
  235. /* Adjust columns for 16 bit bus-width */
  236. if (column != -1 && (chip->options & NAND_BUSWIDTH_16))
  237. column >>= 1;
  238. nand_clear_interrupt_status(info->reg);
  239. /* Stop DMA engine, clear DMA completion status */
  240. writel(DMA_MST_CTRL_EN_A_DISABLE
  241. | DMA_MST_CTRL_EN_B_DISABLE
  242. | DMA_MST_CTRL_IS_DMA_DONE,
  243. &info->reg->dma_mst_ctrl);
  244. /*
  245. * Program and erase have their own busy handlers
  246. * status and sequential in needs no delay
  247. */
  248. switch (command) {
  249. case NAND_CMD_READID:
  250. writel(NAND_CMD_READID, &info->reg->cmd_reg1);
  251. writel(column & 0xFF, &info->reg->addr_reg1);
  252. writel(CMD_GO | CMD_CLE | CMD_ALE | CMD_CE0,
  253. &info->reg->command);
  254. break;
  255. case NAND_CMD_PARAM:
  256. writel(NAND_CMD_PARAM, &info->reg->cmd_reg1);
  257. writel(column & 0xFF, &info->reg->addr_reg1);
  258. writel(CMD_GO | CMD_CLE | CMD_ALE | CMD_CE0,
  259. &info->reg->command);
  260. break;
  261. case NAND_CMD_READ0:
  262. writel(NAND_CMD_READ0, &info->reg->cmd_reg1);
  263. writel(NAND_CMD_READSTART, &info->reg->cmd_reg2);
  264. writel((page_addr << 16) | (column & 0xFFFF),
  265. &info->reg->addr_reg1);
  266. writel(page_addr >> 16, &info->reg->addr_reg2);
  267. return;
  268. case NAND_CMD_SEQIN:
  269. writel(NAND_CMD_SEQIN, &info->reg->cmd_reg1);
  270. writel(NAND_CMD_PAGEPROG, &info->reg->cmd_reg2);
  271. writel((page_addr << 16) | (column & 0xFFFF),
  272. &info->reg->addr_reg1);
  273. writel(page_addr >> 16,
  274. &info->reg->addr_reg2);
  275. return;
  276. case NAND_CMD_PAGEPROG:
  277. return;
  278. case NAND_CMD_ERASE1:
  279. writel(NAND_CMD_ERASE1, &info->reg->cmd_reg1);
  280. writel(NAND_CMD_ERASE2, &info->reg->cmd_reg2);
  281. writel(page_addr, &info->reg->addr_reg1);
  282. writel(CMD_GO | CMD_CLE | CMD_ALE |
  283. CMD_SEC_CMD | CMD_CE0 | CMD_ALE_BYTES3,
  284. &info->reg->command);
  285. break;
  286. case NAND_CMD_ERASE2:
  287. return;
  288. case NAND_CMD_STATUS:
  289. writel(NAND_CMD_STATUS, &info->reg->cmd_reg1);
  290. writel(CMD_GO | CMD_CLE | CMD_PIO | CMD_RX
  291. | ((1 - 0) << CMD_TRANS_SIZE_SHIFT)
  292. | CMD_CE0,
  293. &info->reg->command);
  294. break;
  295. case NAND_CMD_RESET:
  296. writel(NAND_CMD_RESET, &info->reg->cmd_reg1);
  297. writel(CMD_GO | CMD_CLE | CMD_CE0,
  298. &info->reg->command);
  299. break;
  300. case NAND_CMD_RNDOUT:
  301. default:
  302. printf("%s: Unsupported command %d\n", __func__, command);
  303. return;
  304. }
  305. if (!nand_waitfor_cmd_completion(info->reg))
  306. printf("Command 0x%02X timeout\n", command);
  307. }
  308. /**
  309. * Check whether the pointed buffer are all 0xff (blank).
  310. *
  311. * @param buf data buffer for blank check
  312. * @param len length of the buffer in byte
  313. * @return
  314. * 1 - blank
  315. * 0 - non-blank
  316. */
  317. static int blank_check(u8 *buf, int len)
  318. {
  319. int i;
  320. for (i = 0; i < len; i++)
  321. if (buf[i] != 0xFF)
  322. return 0;
  323. return 1;
  324. }
  325. /**
  326. * After a DMA transfer for read, we call this function to see whether there
  327. * is any uncorrectable error on the pointed data buffer or oob buffer.
  328. *
  329. * @param reg nand_ctlr structure
  330. * @param databuf data buffer
  331. * @param a_len data buffer length
  332. * @param oobbuf oob buffer
  333. * @param b_len oob buffer length
  334. * @return
  335. * ECC_OK - no ECC error or correctable ECC error
  336. * ECC_TAG_ERROR - uncorrectable tag ECC error
  337. * ECC_DATA_ERROR - uncorrectable data ECC error
  338. * ECC_DATA_ERROR + ECC_TAG_ERROR - uncorrectable data+tag ECC error
  339. */
  340. static int check_ecc_error(struct nand_ctlr *reg, u8 *databuf,
  341. int a_len, u8 *oobbuf, int b_len)
  342. {
  343. int return_val = ECC_OK;
  344. u32 reg_val;
  345. if (!(readl(&reg->isr) & ISR_IS_ECC_ERR))
  346. return ECC_OK;
  347. /*
  348. * Area A is used for the data block (databuf). Area B is used for
  349. * the spare block (oobbuf)
  350. */
  351. reg_val = readl(&reg->dec_status);
  352. if ((reg_val & DEC_STATUS_A_ECC_FAIL) && databuf) {
  353. reg_val = readl(&reg->bch_dec_status_buf);
  354. /*
  355. * If uncorrectable error occurs on data area, then see whether
  356. * they are all FF. If all are FF, it's a blank page.
  357. * Not error.
  358. */
  359. if ((reg_val & BCH_DEC_STATUS_FAIL_SEC_FLAG_MASK) &&
  360. !blank_check(databuf, a_len))
  361. return_val |= ECC_DATA_ERROR;
  362. }
  363. if ((reg_val & DEC_STATUS_B_ECC_FAIL) && oobbuf) {
  364. reg_val = readl(&reg->bch_dec_status_buf);
  365. /*
  366. * If uncorrectable error occurs on tag area, then see whether
  367. * they are all FF. If all are FF, it's a blank page.
  368. * Not error.
  369. */
  370. if ((reg_val & BCH_DEC_STATUS_FAIL_TAG_MASK) &&
  371. !blank_check(oobbuf, b_len))
  372. return_val |= ECC_TAG_ERROR;
  373. }
  374. return return_val;
  375. }
  376. /**
  377. * Set GO bit to send command to device
  378. *
  379. * @param reg nand_ctlr structure
  380. */
  381. static void start_command(struct nand_ctlr *reg)
  382. {
  383. u32 reg_val;
  384. reg_val = readl(&reg->command);
  385. reg_val |= CMD_GO;
  386. writel(reg_val, &reg->command);
  387. }
  388. /**
  389. * Clear command GO bit, DMA GO bit, and DMA completion status
  390. *
  391. * @param reg nand_ctlr structure
  392. */
  393. static void stop_command(struct nand_ctlr *reg)
  394. {
  395. /* Stop command */
  396. writel(0, &reg->command);
  397. /* Stop DMA engine and clear DMA completion status */
  398. writel(DMA_MST_CTRL_GO_DISABLE
  399. | DMA_MST_CTRL_IS_DMA_DONE,
  400. &reg->dma_mst_ctrl);
  401. }
  402. /**
  403. * Set up NAND bus width and page size
  404. *
  405. * @param info nand_info structure
  406. * @param *reg_val address of reg_val
  407. * @return 0 if ok, -1 on error
  408. */
  409. static int set_bus_width_page_size(struct fdt_nand *config,
  410. u32 *reg_val)
  411. {
  412. if (config->width == 8)
  413. *reg_val = CFG_BUS_WIDTH_8BIT;
  414. else if (config->width == 16)
  415. *reg_val = CFG_BUS_WIDTH_16BIT;
  416. else {
  417. debug("%s: Unsupported bus width %d\n", __func__,
  418. config->width);
  419. return -1;
  420. }
  421. if (our_mtd->writesize == 512)
  422. *reg_val |= CFG_PAGE_SIZE_512;
  423. else if (our_mtd->writesize == 2048)
  424. *reg_val |= CFG_PAGE_SIZE_2048;
  425. else if (our_mtd->writesize == 4096)
  426. *reg_val |= CFG_PAGE_SIZE_4096;
  427. else {
  428. debug("%s: Unsupported page size %d\n", __func__,
  429. our_mtd->writesize);
  430. return -1;
  431. }
  432. return 0;
  433. }
  434. /**
  435. * Page read/write function
  436. *
  437. * @param mtd mtd info structure
  438. * @param chip nand chip info structure
  439. * @param buf data buffer
  440. * @param page page number
  441. * @param with_ecc 1 to enable ECC, 0 to disable ECC
  442. * @param is_writing 0 for read, 1 for write
  443. * @return 0 when successfully completed
  444. * -EIO when command timeout
  445. */
  446. static int nand_rw_page(struct mtd_info *mtd, struct nand_chip *chip,
  447. uint8_t *buf, int page, int with_ecc, int is_writing)
  448. {
  449. u32 reg_val;
  450. int tag_size;
  451. struct nand_oobfree *free = chip->ecc.layout->oobfree;
  452. /* 4*128=512 (byte) is the value that our HW can support. */
  453. ALLOC_CACHE_ALIGN_BUFFER(u32, tag_buf, 128);
  454. char *tag_ptr;
  455. struct nand_drv *info;
  456. struct fdt_nand *config;
  457. unsigned int bbflags;
  458. struct bounce_buffer bbstate, bbstate_oob;
  459. if ((uintptr_t)buf & 0x03) {
  460. printf("buf %p has to be 4-byte aligned\n", buf);
  461. return -EINVAL;
  462. }
  463. info = (struct nand_drv *)nand_get_controller_data(chip);
  464. config = &info->config;
  465. if (set_bus_width_page_size(config, &reg_val))
  466. return -EINVAL;
  467. /* Need to be 4-byte aligned */
  468. tag_ptr = (char *)tag_buf;
  469. stop_command(info->reg);
  470. if (is_writing)
  471. bbflags = GEN_BB_READ;
  472. else
  473. bbflags = GEN_BB_WRITE;
  474. bounce_buffer_start(&bbstate, (void *)buf, 1 << chip->page_shift,
  475. bbflags);
  476. writel((1 << chip->page_shift) - 1, &info->reg->dma_cfg_a);
  477. writel(virt_to_phys(bbstate.bounce_buffer), &info->reg->data_block_ptr);
  478. /* Set ECC selection, configure ECC settings */
  479. if (with_ecc) {
  480. if (is_writing)
  481. memcpy(tag_ptr, chip->oob_poi + free->offset,
  482. chip->ecc.layout->oobavail + TAG_ECC_BYTES);
  483. tag_size = chip->ecc.layout->oobavail + TAG_ECC_BYTES;
  484. reg_val |= (CFG_SKIP_SPARE_SEL_4
  485. | CFG_SKIP_SPARE_ENABLE
  486. | CFG_HW_ECC_CORRECTION_ENABLE
  487. | CFG_ECC_EN_TAG_DISABLE
  488. | CFG_HW_ECC_SEL_RS
  489. | CFG_HW_ECC_ENABLE
  490. | CFG_TVAL4
  491. | (tag_size - 1));
  492. if (!is_writing)
  493. tag_size += SKIPPED_SPARE_BYTES;
  494. bounce_buffer_start(&bbstate_oob, (void *)tag_ptr, tag_size,
  495. bbflags);
  496. } else {
  497. tag_size = mtd->oobsize;
  498. reg_val |= (CFG_SKIP_SPARE_DISABLE
  499. | CFG_HW_ECC_CORRECTION_DISABLE
  500. | CFG_ECC_EN_TAG_DISABLE
  501. | CFG_HW_ECC_DISABLE
  502. | (tag_size - 1));
  503. bounce_buffer_start(&bbstate_oob, (void *)chip->oob_poi,
  504. tag_size, bbflags);
  505. }
  506. writel(reg_val, &info->reg->config);
  507. writel(virt_to_phys(bbstate_oob.bounce_buffer), &info->reg->tag_ptr);
  508. writel(BCH_CONFIG_BCH_ECC_DISABLE, &info->reg->bch_config);
  509. writel(tag_size - 1, &info->reg->dma_cfg_b);
  510. nand_clear_interrupt_status(info->reg);
  511. reg_val = CMD_CLE | CMD_ALE
  512. | CMD_SEC_CMD
  513. | (CMD_ALE_BYTES5 << CMD_ALE_BYTE_SIZE_SHIFT)
  514. | CMD_A_VALID
  515. | CMD_B_VALID
  516. | (CMD_TRANS_SIZE_PAGE << CMD_TRANS_SIZE_SHIFT)
  517. | CMD_CE0;
  518. if (!is_writing)
  519. reg_val |= (CMD_AFT_DAT_DISABLE | CMD_RX);
  520. else
  521. reg_val |= (CMD_AFT_DAT_ENABLE | CMD_TX);
  522. writel(reg_val, &info->reg->command);
  523. /* Setup DMA engine */
  524. reg_val = DMA_MST_CTRL_GO_ENABLE
  525. | DMA_MST_CTRL_BURST_8WORDS
  526. | DMA_MST_CTRL_EN_A_ENABLE
  527. | DMA_MST_CTRL_EN_B_ENABLE;
  528. if (!is_writing)
  529. reg_val |= DMA_MST_CTRL_DIR_READ;
  530. else
  531. reg_val |= DMA_MST_CTRL_DIR_WRITE;
  532. writel(reg_val, &info->reg->dma_mst_ctrl);
  533. start_command(info->reg);
  534. if (!nand_waitfor_cmd_completion(info->reg)) {
  535. if (!is_writing)
  536. printf("Read Page 0x%X timeout ", page);
  537. else
  538. printf("Write Page 0x%X timeout ", page);
  539. if (with_ecc)
  540. printf("with ECC");
  541. else
  542. printf("without ECC");
  543. printf("\n");
  544. return -EIO;
  545. }
  546. bounce_buffer_stop(&bbstate_oob);
  547. bounce_buffer_stop(&bbstate);
  548. if (with_ecc && !is_writing) {
  549. memcpy(chip->oob_poi, tag_ptr,
  550. SKIPPED_SPARE_BYTES);
  551. memcpy(chip->oob_poi + free->offset,
  552. tag_ptr + SKIPPED_SPARE_BYTES,
  553. chip->ecc.layout->oobavail);
  554. reg_val = (u32)check_ecc_error(info->reg, (u8 *)buf,
  555. 1 << chip->page_shift,
  556. (u8 *)(tag_ptr + SKIPPED_SPARE_BYTES),
  557. chip->ecc.layout->oobavail);
  558. if (reg_val & ECC_TAG_ERROR)
  559. printf("Read Page 0x%X tag ECC error\n", page);
  560. if (reg_val & ECC_DATA_ERROR)
  561. printf("Read Page 0x%X data ECC error\n",
  562. page);
  563. if (reg_val & (ECC_DATA_ERROR | ECC_TAG_ERROR))
  564. return -EIO;
  565. }
  566. return 0;
  567. }
  568. /**
  569. * Hardware ecc based page read function
  570. *
  571. * @param mtd mtd info structure
  572. * @param chip nand chip info structure
  573. * @param buf buffer to store read data
  574. * @param page page number to read
  575. * @return 0 when successfully completed
  576. * -EIO when command timeout
  577. */
  578. static int nand_read_page_hwecc(struct mtd_info *mtd,
  579. struct nand_chip *chip, uint8_t *buf, int oob_required, int page)
  580. {
  581. return nand_rw_page(mtd, chip, buf, page, 1, 0);
  582. }
  583. /**
  584. * Hardware ecc based page write function
  585. *
  586. * @param mtd mtd info structure
  587. * @param chip nand chip info structure
  588. * @param buf data buffer
  589. */
  590. static int nand_write_page_hwecc(struct mtd_info *mtd,
  591. struct nand_chip *chip, const uint8_t *buf, int oob_required)
  592. {
  593. int page;
  594. struct nand_drv *info;
  595. info = (struct nand_drv *)nand_get_controller_data(chip);
  596. page = (readl(&info->reg->addr_reg1) >> 16) |
  597. (readl(&info->reg->addr_reg2) << 16);
  598. nand_rw_page(mtd, chip, (uint8_t *)buf, page, 1, 1);
  599. return 0;
  600. }
  601. /**
  602. * Read raw page data without ecc
  603. *
  604. * @param mtd mtd info structure
  605. * @param chip nand chip info structure
  606. * @param buf buffer to store read data
  607. * @param page page number to read
  608. * @return 0 when successfully completed
  609. * -EINVAL when chip->oob_poi is not double-word aligned
  610. * -EIO when command timeout
  611. */
  612. static int nand_read_page_raw(struct mtd_info *mtd,
  613. struct nand_chip *chip, uint8_t *buf, int oob_required, int page)
  614. {
  615. return nand_rw_page(mtd, chip, buf, page, 0, 0);
  616. }
  617. /**
  618. * Raw page write function
  619. *
  620. * @param mtd mtd info structure
  621. * @param chip nand chip info structure
  622. * @param buf data buffer
  623. */
  624. static int nand_write_page_raw(struct mtd_info *mtd,
  625. struct nand_chip *chip, const uint8_t *buf, int oob_required)
  626. {
  627. int page;
  628. struct nand_drv *info;
  629. info = (struct nand_drv *)nand_get_controller_data(chip);
  630. page = (readl(&info->reg->addr_reg1) >> 16) |
  631. (readl(&info->reg->addr_reg2) << 16);
  632. nand_rw_page(mtd, chip, (uint8_t *)buf, page, 0, 1);
  633. return 0;
  634. }
  635. /**
  636. * OOB data read/write function
  637. *
  638. * @param mtd mtd info structure
  639. * @param chip nand chip info structure
  640. * @param page page number to read
  641. * @param with_ecc 1 to enable ECC, 0 to disable ECC
  642. * @param is_writing 0 for read, 1 for write
  643. * @return 0 when successfully completed
  644. * -EINVAL when chip->oob_poi is not double-word aligned
  645. * -EIO when command timeout
  646. */
  647. static int nand_rw_oob(struct mtd_info *mtd, struct nand_chip *chip,
  648. int page, int with_ecc, int is_writing)
  649. {
  650. u32 reg_val;
  651. int tag_size;
  652. struct nand_oobfree *free = chip->ecc.layout->oobfree;
  653. struct nand_drv *info;
  654. unsigned int bbflags;
  655. struct bounce_buffer bbstate_oob;
  656. if (((int)chip->oob_poi) & 0x03)
  657. return -EINVAL;
  658. info = (struct nand_drv *)nand_get_controller_data(chip);
  659. if (set_bus_width_page_size(&info->config, &reg_val))
  660. return -EINVAL;
  661. stop_command(info->reg);
  662. /* Set ECC selection */
  663. tag_size = mtd->oobsize;
  664. if (with_ecc)
  665. reg_val |= CFG_ECC_EN_TAG_ENABLE;
  666. else
  667. reg_val |= (CFG_ECC_EN_TAG_DISABLE);
  668. reg_val |= ((tag_size - 1) |
  669. CFG_SKIP_SPARE_DISABLE |
  670. CFG_HW_ECC_CORRECTION_DISABLE |
  671. CFG_HW_ECC_DISABLE);
  672. writel(reg_val, &info->reg->config);
  673. if (is_writing && with_ecc)
  674. tag_size -= TAG_ECC_BYTES;
  675. if (is_writing)
  676. bbflags = GEN_BB_READ;
  677. else
  678. bbflags = GEN_BB_WRITE;
  679. bounce_buffer_start(&bbstate_oob, (void *)chip->oob_poi, tag_size,
  680. bbflags);
  681. writel(virt_to_phys(bbstate_oob.bounce_buffer), &info->reg->tag_ptr);
  682. writel(BCH_CONFIG_BCH_ECC_DISABLE, &info->reg->bch_config);
  683. writel(tag_size - 1, &info->reg->dma_cfg_b);
  684. nand_clear_interrupt_status(info->reg);
  685. reg_val = CMD_CLE | CMD_ALE
  686. | CMD_SEC_CMD
  687. | (CMD_ALE_BYTES5 << CMD_ALE_BYTE_SIZE_SHIFT)
  688. | CMD_B_VALID
  689. | CMD_CE0;
  690. if (!is_writing)
  691. reg_val |= (CMD_AFT_DAT_DISABLE | CMD_RX);
  692. else
  693. reg_val |= (CMD_AFT_DAT_ENABLE | CMD_TX);
  694. writel(reg_val, &info->reg->command);
  695. /* Setup DMA engine */
  696. reg_val = DMA_MST_CTRL_GO_ENABLE
  697. | DMA_MST_CTRL_BURST_8WORDS
  698. | DMA_MST_CTRL_EN_B_ENABLE;
  699. if (!is_writing)
  700. reg_val |= DMA_MST_CTRL_DIR_READ;
  701. else
  702. reg_val |= DMA_MST_CTRL_DIR_WRITE;
  703. writel(reg_val, &info->reg->dma_mst_ctrl);
  704. start_command(info->reg);
  705. if (!nand_waitfor_cmd_completion(info->reg)) {
  706. if (!is_writing)
  707. printf("Read OOB of Page 0x%X timeout\n", page);
  708. else
  709. printf("Write OOB of Page 0x%X timeout\n", page);
  710. return -EIO;
  711. }
  712. bounce_buffer_stop(&bbstate_oob);
  713. if (with_ecc && !is_writing) {
  714. reg_val = (u32)check_ecc_error(info->reg, 0, 0,
  715. (u8 *)(chip->oob_poi + free->offset),
  716. chip->ecc.layout->oobavail);
  717. if (reg_val & ECC_TAG_ERROR)
  718. printf("Read OOB of Page 0x%X tag ECC error\n", page);
  719. }
  720. return 0;
  721. }
  722. /**
  723. * OOB data read function
  724. *
  725. * @param mtd mtd info structure
  726. * @param chip nand chip info structure
  727. * @param page page number to read
  728. */
  729. static int nand_read_oob(struct mtd_info *mtd, struct nand_chip *chip,
  730. int page)
  731. {
  732. chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page);
  733. nand_rw_oob(mtd, chip, page, 0, 0);
  734. return 0;
  735. }
  736. /**
  737. * OOB data write function
  738. *
  739. * @param mtd mtd info structure
  740. * @param chip nand chip info structure
  741. * @param page page number to write
  742. * @return 0 when successfully completed
  743. * -EINVAL when chip->oob_poi is not double-word aligned
  744. * -EIO when command timeout
  745. */
  746. static int nand_write_oob(struct mtd_info *mtd, struct nand_chip *chip,
  747. int page)
  748. {
  749. chip->cmdfunc(mtd, NAND_CMD_SEQIN, mtd->writesize, page);
  750. return nand_rw_oob(mtd, chip, page, 0, 1);
  751. }
  752. /**
  753. * Set up NAND memory timings according to the provided parameters
  754. *
  755. * @param timing Timing parameters
  756. * @param reg NAND controller register address
  757. */
  758. static void setup_timing(unsigned timing[FDT_NAND_TIMING_COUNT],
  759. struct nand_ctlr *reg)
  760. {
  761. u32 reg_val, clk_rate, clk_period, time_val;
  762. clk_rate = (u32)clock_get_periph_rate(PERIPH_ID_NDFLASH,
  763. CLOCK_ID_PERIPH) / 1000000;
  764. clk_period = 1000 / clk_rate;
  765. reg_val = ((timing[FDT_NAND_MAX_TRP_TREA] / clk_period) <<
  766. TIMING_TRP_RESP_CNT_SHIFT) & TIMING_TRP_RESP_CNT_MASK;
  767. reg_val |= ((timing[FDT_NAND_TWB] / clk_period) <<
  768. TIMING_TWB_CNT_SHIFT) & TIMING_TWB_CNT_MASK;
  769. time_val = timing[FDT_NAND_MAX_TCR_TAR_TRR] / clk_period;
  770. if (time_val > 2)
  771. reg_val |= ((time_val - 2) << TIMING_TCR_TAR_TRR_CNT_SHIFT) &
  772. TIMING_TCR_TAR_TRR_CNT_MASK;
  773. reg_val |= ((timing[FDT_NAND_TWHR] / clk_period) <<
  774. TIMING_TWHR_CNT_SHIFT) & TIMING_TWHR_CNT_MASK;
  775. time_val = timing[FDT_NAND_MAX_TCS_TCH_TALS_TALH] / clk_period;
  776. if (time_val > 1)
  777. reg_val |= ((time_val - 1) << TIMING_TCS_CNT_SHIFT) &
  778. TIMING_TCS_CNT_MASK;
  779. reg_val |= ((timing[FDT_NAND_TWH] / clk_period) <<
  780. TIMING_TWH_CNT_SHIFT) & TIMING_TWH_CNT_MASK;
  781. reg_val |= ((timing[FDT_NAND_TWP] / clk_period) <<
  782. TIMING_TWP_CNT_SHIFT) & TIMING_TWP_CNT_MASK;
  783. reg_val |= ((timing[FDT_NAND_TRH] / clk_period) <<
  784. TIMING_TRH_CNT_SHIFT) & TIMING_TRH_CNT_MASK;
  785. reg_val |= ((timing[FDT_NAND_MAX_TRP_TREA] / clk_period) <<
  786. TIMING_TRP_CNT_SHIFT) & TIMING_TRP_CNT_MASK;
  787. writel(reg_val, &reg->timing);
  788. reg_val = 0;
  789. time_val = timing[FDT_NAND_TADL] / clk_period;
  790. if (time_val > 2)
  791. reg_val = (time_val - 2) & TIMING2_TADL_CNT_MASK;
  792. writel(reg_val, &reg->timing2);
  793. }
  794. /**
  795. * Decode NAND parameters from the device tree
  796. *
  797. * @param blob Device tree blob
  798. * @param node Node containing "nand-flash" compatble node
  799. * @return 0 if ok, -ve on error (FDT_ERR_...)
  800. */
  801. static int fdt_decode_nand(const void *blob, int node, struct fdt_nand *config)
  802. {
  803. int err;
  804. config->reg = (struct nand_ctlr *)fdtdec_get_addr(blob, node, "reg");
  805. config->enabled = fdtdec_get_is_enabled(blob, node);
  806. config->width = fdtdec_get_int(blob, node, "nvidia,nand-width", 8);
  807. err = gpio_request_by_name_nodev(blob, node, "nvidia,wp-gpios", 0,
  808. &config->wp_gpio, GPIOD_IS_OUT);
  809. if (err)
  810. return err;
  811. err = fdtdec_get_int_array(blob, node, "nvidia,timing",
  812. config->timing, FDT_NAND_TIMING_COUNT);
  813. if (err < 0)
  814. return err;
  815. /* Now look up the controller and decode that */
  816. node = fdt_next_node(blob, node, NULL);
  817. if (node < 0)
  818. return node;
  819. return 0;
  820. }
  821. /**
  822. * Board-specific NAND initialization
  823. *
  824. * @param nand nand chip info structure
  825. * @return 0, after initialized, -1 on error
  826. */
  827. int tegra_nand_init(struct nand_chip *nand, int devnum)
  828. {
  829. struct nand_drv *info = &nand_ctrl;
  830. struct fdt_nand *config = &info->config;
  831. int node, ret;
  832. node = fdtdec_next_compatible(gd->fdt_blob, 0,
  833. COMPAT_NVIDIA_TEGRA20_NAND);
  834. if (node < 0)
  835. return -1;
  836. if (fdt_decode_nand(gd->fdt_blob, node, config)) {
  837. printf("Could not decode nand-flash in device tree\n");
  838. return -1;
  839. }
  840. if (!config->enabled)
  841. return -1;
  842. info->reg = config->reg;
  843. nand->ecc.mode = NAND_ECC_HW;
  844. nand->ecc.layout = &eccoob;
  845. nand->options = LP_OPTIONS;
  846. nand->cmdfunc = nand_command;
  847. nand->read_byte = read_byte;
  848. nand->read_buf = read_buf;
  849. nand->ecc.read_page = nand_read_page_hwecc;
  850. nand->ecc.write_page = nand_write_page_hwecc;
  851. nand->ecc.read_page_raw = nand_read_page_raw;
  852. nand->ecc.write_page_raw = nand_write_page_raw;
  853. nand->ecc.read_oob = nand_read_oob;
  854. nand->ecc.write_oob = nand_write_oob;
  855. nand->ecc.strength = 1;
  856. nand->select_chip = nand_select_chip;
  857. nand->dev_ready = nand_dev_ready;
  858. nand_set_controller_data(nand, &nand_ctrl);
  859. /* Disable subpage writes as we do not provide ecc->hwctl */
  860. nand->options |= NAND_NO_SUBPAGE_WRITE;
  861. /* Adjust controller clock rate */
  862. clock_start_periph_pll(PERIPH_ID_NDFLASH, CLOCK_ID_PERIPH, 52000000);
  863. /* Adjust timing for NAND device */
  864. setup_timing(config->timing, info->reg);
  865. dm_gpio_set_value(&config->wp_gpio, 1);
  866. our_mtd = nand_to_mtd(nand);
  867. ret = nand_scan_ident(our_mtd, CONFIG_SYS_NAND_MAX_CHIPS, NULL);
  868. if (ret)
  869. return ret;
  870. nand->ecc.size = our_mtd->writesize;
  871. nand->ecc.bytes = our_mtd->oobsize;
  872. ret = nand_scan_tail(our_mtd);
  873. if (ret)
  874. return ret;
  875. ret = nand_register(devnum, our_mtd);
  876. if (ret)
  877. return ret;
  878. return 0;
  879. }
  880. void board_nand_init(void)
  881. {
  882. struct nand_chip *nand = &nand_chip[0];
  883. if (tegra_nand_init(nand, 0))
  884. puts("Tegra NAND init failed\n");
  885. }