s3c2410_nand.c 4.4 KB

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  1. /*
  2. * (C) Copyright 2006 OpenMoko, Inc.
  3. * Author: Harald Welte <laforge@openmoko.org>
  4. *
  5. * SPDX-License-Identifier: GPL-2.0+
  6. */
  7. #include <common.h>
  8. #include <nand.h>
  9. #include <asm/arch/s3c24x0_cpu.h>
  10. #include <asm/io.h>
  11. #define S3C2410_NFCONF_EN (1<<15)
  12. #define S3C2410_NFCONF_512BYTE (1<<14)
  13. #define S3C2410_NFCONF_4STEP (1<<13)
  14. #define S3C2410_NFCONF_INITECC (1<<12)
  15. #define S3C2410_NFCONF_nFCE (1<<11)
  16. #define S3C2410_NFCONF_TACLS(x) ((x)<<8)
  17. #define S3C2410_NFCONF_TWRPH0(x) ((x)<<4)
  18. #define S3C2410_NFCONF_TWRPH1(x) ((x)<<0)
  19. #define S3C2410_ADDR_NALE 4
  20. #define S3C2410_ADDR_NCLE 8
  21. #ifdef CONFIG_NAND_SPL
  22. /* in the early stage of NAND flash booting, printf() is not available */
  23. #define printf(fmt, args...)
  24. static void nand_read_buf(struct mtd_info *mtd, u_char *buf, int len)
  25. {
  26. int i;
  27. struct nand_chip *this = mtd_to_nand(mtd);
  28. for (i = 0; i < len; i++)
  29. buf[i] = readb(this->IO_ADDR_R);
  30. }
  31. #endif
  32. static void s3c24x0_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl)
  33. {
  34. struct nand_chip *chip = mtd_to_nand(mtd);
  35. struct s3c24x0_nand *nand = s3c24x0_get_base_nand();
  36. debug("hwcontrol(): 0x%02x 0x%02x\n", cmd, ctrl);
  37. if (ctrl & NAND_CTRL_CHANGE) {
  38. ulong IO_ADDR_W = (ulong)nand;
  39. if (!(ctrl & NAND_CLE))
  40. IO_ADDR_W |= S3C2410_ADDR_NCLE;
  41. if (!(ctrl & NAND_ALE))
  42. IO_ADDR_W |= S3C2410_ADDR_NALE;
  43. chip->IO_ADDR_W = (void *)IO_ADDR_W;
  44. if (ctrl & NAND_NCE)
  45. writel(readl(&nand->nfconf) & ~S3C2410_NFCONF_nFCE,
  46. &nand->nfconf);
  47. else
  48. writel(readl(&nand->nfconf) | S3C2410_NFCONF_nFCE,
  49. &nand->nfconf);
  50. }
  51. if (cmd != NAND_CMD_NONE)
  52. writeb(cmd, chip->IO_ADDR_W);
  53. }
  54. static int s3c24x0_dev_ready(struct mtd_info *mtd)
  55. {
  56. struct s3c24x0_nand *nand = s3c24x0_get_base_nand();
  57. debug("dev_ready\n");
  58. return readl(&nand->nfstat) & 0x01;
  59. }
  60. #ifdef CONFIG_S3C2410_NAND_HWECC
  61. void s3c24x0_nand_enable_hwecc(struct mtd_info *mtd, int mode)
  62. {
  63. struct s3c24x0_nand *nand = s3c24x0_get_base_nand();
  64. debug("s3c24x0_nand_enable_hwecc(%p, %d)\n", mtd, mode);
  65. writel(readl(&nand->nfconf) | S3C2410_NFCONF_INITECC, &nand->nfconf);
  66. }
  67. static int s3c24x0_nand_calculate_ecc(struct mtd_info *mtd, const u_char *dat,
  68. u_char *ecc_code)
  69. {
  70. struct s3c24x0_nand *nand = s3c24x0_get_base_nand();
  71. ecc_code[0] = readb(&nand->nfecc);
  72. ecc_code[1] = readb(&nand->nfecc + 1);
  73. ecc_code[2] = readb(&nand->nfecc + 2);
  74. debug("s3c24x0_nand_calculate_hwecc(%p,): 0x%02x 0x%02x 0x%02x\n",
  75. mtd , ecc_code[0], ecc_code[1], ecc_code[2]);
  76. return 0;
  77. }
  78. static int s3c24x0_nand_correct_data(struct mtd_info *mtd, u_char *dat,
  79. u_char *read_ecc, u_char *calc_ecc)
  80. {
  81. if (read_ecc[0] == calc_ecc[0] &&
  82. read_ecc[1] == calc_ecc[1] &&
  83. read_ecc[2] == calc_ecc[2])
  84. return 0;
  85. printf("s3c24x0_nand_correct_data: not implemented\n");
  86. return -1;
  87. }
  88. #endif
  89. int board_nand_init(struct nand_chip *nand)
  90. {
  91. u_int32_t cfg;
  92. u_int8_t tacls, twrph0, twrph1;
  93. struct s3c24x0_clock_power *clk_power = s3c24x0_get_base_clock_power();
  94. struct s3c24x0_nand *nand_reg = s3c24x0_get_base_nand();
  95. debug("board_nand_init()\n");
  96. writel(readl(&clk_power->clkcon) | (1 << 4), &clk_power->clkcon);
  97. /* initialize hardware */
  98. #if defined(CONFIG_S3C24XX_CUSTOM_NAND_TIMING)
  99. tacls = CONFIG_S3C24XX_TACLS;
  100. twrph0 = CONFIG_S3C24XX_TWRPH0;
  101. twrph1 = CONFIG_S3C24XX_TWRPH1;
  102. #else
  103. tacls = 4;
  104. twrph0 = 8;
  105. twrph1 = 8;
  106. #endif
  107. cfg = S3C2410_NFCONF_EN;
  108. cfg |= S3C2410_NFCONF_TACLS(tacls - 1);
  109. cfg |= S3C2410_NFCONF_TWRPH0(twrph0 - 1);
  110. cfg |= S3C2410_NFCONF_TWRPH1(twrph1 - 1);
  111. writel(cfg, &nand_reg->nfconf);
  112. /* initialize nand_chip data structure */
  113. nand->IO_ADDR_R = (void *)&nand_reg->nfdata;
  114. nand->IO_ADDR_W = (void *)&nand_reg->nfdata;
  115. nand->select_chip = NULL;
  116. /* read_buf and write_buf are default */
  117. /* read_byte and write_byte are default */
  118. #ifdef CONFIG_NAND_SPL
  119. nand->read_buf = nand_read_buf;
  120. #endif
  121. /* hwcontrol always must be implemented */
  122. nand->cmd_ctrl = s3c24x0_hwcontrol;
  123. nand->dev_ready = s3c24x0_dev_ready;
  124. #ifdef CONFIG_S3C2410_NAND_HWECC
  125. nand->ecc.hwctl = s3c24x0_nand_enable_hwecc;
  126. nand->ecc.calculate = s3c24x0_nand_calculate_ecc;
  127. nand->ecc.correct = s3c24x0_nand_correct_data;
  128. nand->ecc.mode = NAND_ECC_HW;
  129. nand->ecc.size = CONFIG_SYS_NAND_ECCSIZE;
  130. nand->ecc.bytes = CONFIG_SYS_NAND_ECCBYTES;
  131. nand->ecc.strength = 1;
  132. #else
  133. nand->ecc.mode = NAND_ECC_SOFT;
  134. #endif
  135. #ifdef CONFIG_S3C2410_NAND_BBT
  136. nand->bbt_options |= NAND_BBT_USE_FLASH;
  137. #endif
  138. debug("end of nand_init\n");
  139. return 0;
  140. }