pxa3xx_nand.c 40 KB

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  1. /*
  2. * drivers/mtd/nand/pxa3xx_nand.c
  3. *
  4. * Copyright © 2005 Intel Corporation
  5. * Copyright © 2006 Marvell International Ltd.
  6. *
  7. * SPDX-License-Identifier: GPL-2.0
  8. */
  9. #include <common.h>
  10. #include <malloc.h>
  11. #include <nand.h>
  12. #include <asm/errno.h>
  13. #include <asm/io.h>
  14. #include <asm/arch/cpu.h>
  15. #include <linux/mtd/mtd.h>
  16. #include <linux/mtd/nand.h>
  17. #include <linux/types.h>
  18. #include "pxa3xx_nand.h"
  19. #define TIMEOUT_DRAIN_FIFO 5 /* in ms */
  20. #define CHIP_DELAY_TIMEOUT 200
  21. #define NAND_STOP_DELAY 40
  22. #define PAGE_CHUNK_SIZE (2048)
  23. /*
  24. * Define a buffer size for the initial command that detects the flash device:
  25. * STATUS, READID and PARAM. The largest of these is the PARAM command,
  26. * needing 256 bytes.
  27. */
  28. #define INIT_BUFFER_SIZE 256
  29. /* registers and bit definitions */
  30. #define NDCR (0x00) /* Control register */
  31. #define NDTR0CS0 (0x04) /* Timing Parameter 0 for CS0 */
  32. #define NDTR1CS0 (0x0C) /* Timing Parameter 1 for CS0 */
  33. #define NDSR (0x14) /* Status Register */
  34. #define NDPCR (0x18) /* Page Count Register */
  35. #define NDBDR0 (0x1C) /* Bad Block Register 0 */
  36. #define NDBDR1 (0x20) /* Bad Block Register 1 */
  37. #define NDECCCTRL (0x28) /* ECC control */
  38. #define NDDB (0x40) /* Data Buffer */
  39. #define NDCB0 (0x48) /* Command Buffer0 */
  40. #define NDCB1 (0x4C) /* Command Buffer1 */
  41. #define NDCB2 (0x50) /* Command Buffer2 */
  42. #define NDCR_SPARE_EN (0x1 << 31)
  43. #define NDCR_ECC_EN (0x1 << 30)
  44. #define NDCR_DMA_EN (0x1 << 29)
  45. #define NDCR_ND_RUN (0x1 << 28)
  46. #define NDCR_DWIDTH_C (0x1 << 27)
  47. #define NDCR_DWIDTH_M (0x1 << 26)
  48. #define NDCR_PAGE_SZ (0x1 << 24)
  49. #define NDCR_NCSX (0x1 << 23)
  50. #define NDCR_ND_MODE (0x3 << 21)
  51. #define NDCR_NAND_MODE (0x0)
  52. #define NDCR_CLR_PG_CNT (0x1 << 20)
  53. #define NDCR_STOP_ON_UNCOR (0x1 << 19)
  54. #define NDCR_RD_ID_CNT_MASK (0x7 << 16)
  55. #define NDCR_RD_ID_CNT(x) (((x) << 16) & NDCR_RD_ID_CNT_MASK)
  56. #define NDCR_RA_START (0x1 << 15)
  57. #define NDCR_PG_PER_BLK (0x1 << 14)
  58. #define NDCR_ND_ARB_EN (0x1 << 12)
  59. #define NDCR_INT_MASK (0xFFF)
  60. #define NDSR_MASK (0xfff)
  61. #define NDSR_ERR_CNT_OFF (16)
  62. #define NDSR_ERR_CNT_MASK (0x1f)
  63. #define NDSR_ERR_CNT(sr) ((sr >> NDSR_ERR_CNT_OFF) & NDSR_ERR_CNT_MASK)
  64. #define NDSR_RDY (0x1 << 12)
  65. #define NDSR_FLASH_RDY (0x1 << 11)
  66. #define NDSR_CS0_PAGED (0x1 << 10)
  67. #define NDSR_CS1_PAGED (0x1 << 9)
  68. #define NDSR_CS0_CMDD (0x1 << 8)
  69. #define NDSR_CS1_CMDD (0x1 << 7)
  70. #define NDSR_CS0_BBD (0x1 << 6)
  71. #define NDSR_CS1_BBD (0x1 << 5)
  72. #define NDSR_UNCORERR (0x1 << 4)
  73. #define NDSR_CORERR (0x1 << 3)
  74. #define NDSR_WRDREQ (0x1 << 2)
  75. #define NDSR_RDDREQ (0x1 << 1)
  76. #define NDSR_WRCMDREQ (0x1)
  77. #define NDCB0_LEN_OVRD (0x1 << 28)
  78. #define NDCB0_ST_ROW_EN (0x1 << 26)
  79. #define NDCB0_AUTO_RS (0x1 << 25)
  80. #define NDCB0_CSEL (0x1 << 24)
  81. #define NDCB0_EXT_CMD_TYPE_MASK (0x7 << 29)
  82. #define NDCB0_EXT_CMD_TYPE(x) (((x) << 29) & NDCB0_EXT_CMD_TYPE_MASK)
  83. #define NDCB0_CMD_TYPE_MASK (0x7 << 21)
  84. #define NDCB0_CMD_TYPE(x) (((x) << 21) & NDCB0_CMD_TYPE_MASK)
  85. #define NDCB0_NC (0x1 << 20)
  86. #define NDCB0_DBC (0x1 << 19)
  87. #define NDCB0_ADDR_CYC_MASK (0x7 << 16)
  88. #define NDCB0_ADDR_CYC(x) (((x) << 16) & NDCB0_ADDR_CYC_MASK)
  89. #define NDCB0_CMD2_MASK (0xff << 8)
  90. #define NDCB0_CMD1_MASK (0xff)
  91. #define NDCB0_ADDR_CYC_SHIFT (16)
  92. #define EXT_CMD_TYPE_DISPATCH 6 /* Command dispatch */
  93. #define EXT_CMD_TYPE_NAKED_RW 5 /* Naked read or Naked write */
  94. #define EXT_CMD_TYPE_READ 4 /* Read */
  95. #define EXT_CMD_TYPE_DISP_WR 4 /* Command dispatch with write */
  96. #define EXT_CMD_TYPE_FINAL 3 /* Final command */
  97. #define EXT_CMD_TYPE_LAST_RW 1 /* Last naked read/write */
  98. #define EXT_CMD_TYPE_MONO 0 /* Monolithic read/write */
  99. /* macros for registers read/write */
  100. #define nand_writel(info, off, val) \
  101. writel((val), (info)->mmio_base + (off))
  102. #define nand_readl(info, off) \
  103. readl((info)->mmio_base + (off))
  104. /* error code and state */
  105. enum {
  106. ERR_NONE = 0,
  107. ERR_DMABUSERR = -1,
  108. ERR_SENDCMD = -2,
  109. ERR_UNCORERR = -3,
  110. ERR_BBERR = -4,
  111. ERR_CORERR = -5,
  112. };
  113. enum {
  114. STATE_IDLE = 0,
  115. STATE_PREPARED,
  116. STATE_CMD_HANDLE,
  117. STATE_DMA_READING,
  118. STATE_DMA_WRITING,
  119. STATE_DMA_DONE,
  120. STATE_PIO_READING,
  121. STATE_PIO_WRITING,
  122. STATE_CMD_DONE,
  123. STATE_READY,
  124. };
  125. enum pxa3xx_nand_variant {
  126. PXA3XX_NAND_VARIANT_PXA,
  127. PXA3XX_NAND_VARIANT_ARMADA370,
  128. };
  129. struct pxa3xx_nand_host {
  130. struct nand_chip chip;
  131. struct mtd_info *mtd;
  132. void *info_data;
  133. /* page size of attached chip */
  134. int use_ecc;
  135. int cs;
  136. /* calculated from pxa3xx_nand_flash data */
  137. unsigned int col_addr_cycles;
  138. unsigned int row_addr_cycles;
  139. size_t read_id_bytes;
  140. };
  141. struct pxa3xx_nand_info {
  142. struct nand_hw_control controller;
  143. struct pxa3xx_nand_platform_data *pdata;
  144. struct clk *clk;
  145. void __iomem *mmio_base;
  146. unsigned long mmio_phys;
  147. int cmd_complete, dev_ready;
  148. unsigned int buf_start;
  149. unsigned int buf_count;
  150. unsigned int buf_size;
  151. unsigned int data_buff_pos;
  152. unsigned int oob_buff_pos;
  153. unsigned char *data_buff;
  154. unsigned char *oob_buff;
  155. struct pxa3xx_nand_host *host[NUM_CHIP_SELECT];
  156. unsigned int state;
  157. /*
  158. * This driver supports NFCv1 (as found in PXA SoC)
  159. * and NFCv2 (as found in Armada 370/XP SoC).
  160. */
  161. enum pxa3xx_nand_variant variant;
  162. int cs;
  163. int use_ecc; /* use HW ECC ? */
  164. int ecc_bch; /* using BCH ECC? */
  165. int use_spare; /* use spare ? */
  166. int need_wait;
  167. unsigned int data_size; /* data to be read from FIFO */
  168. unsigned int chunk_size; /* split commands chunk size */
  169. unsigned int oob_size;
  170. unsigned int spare_size;
  171. unsigned int ecc_size;
  172. unsigned int ecc_err_cnt;
  173. unsigned int max_bitflips;
  174. int retcode;
  175. /* cached register value */
  176. uint32_t reg_ndcr;
  177. uint32_t ndtr0cs0;
  178. uint32_t ndtr1cs0;
  179. /* generated NDCBx register values */
  180. uint32_t ndcb0;
  181. uint32_t ndcb1;
  182. uint32_t ndcb2;
  183. uint32_t ndcb3;
  184. };
  185. static struct pxa3xx_nand_timing timing[] = {
  186. { 40, 80, 60, 100, 80, 100, 90000, 400, 40, },
  187. { 10, 0, 20, 40, 30, 40, 11123, 110, 10, },
  188. { 10, 25, 15, 25, 15, 30, 25000, 60, 10, },
  189. { 10, 35, 15, 25, 15, 25, 25000, 60, 10, },
  190. };
  191. static struct pxa3xx_nand_flash builtin_flash_types[] = {
  192. { 0x46ec, 16, 16, &timing[1] },
  193. { 0xdaec, 8, 8, &timing[1] },
  194. { 0xd7ec, 8, 8, &timing[1] },
  195. { 0xa12c, 8, 8, &timing[2] },
  196. { 0xb12c, 16, 16, &timing[2] },
  197. { 0xdc2c, 8, 8, &timing[2] },
  198. { 0xcc2c, 16, 16, &timing[2] },
  199. { 0xba20, 16, 16, &timing[3] },
  200. };
  201. static u8 bbt_pattern[] = {'M', 'V', 'B', 'b', 't', '0' };
  202. static u8 bbt_mirror_pattern[] = {'1', 't', 'b', 'B', 'V', 'M' };
  203. static struct nand_bbt_descr bbt_main_descr = {
  204. .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE
  205. | NAND_BBT_2BIT | NAND_BBT_VERSION,
  206. .offs = 8,
  207. .len = 6,
  208. .veroffs = 14,
  209. .maxblocks = 8, /* Last 8 blocks in each chip */
  210. .pattern = bbt_pattern
  211. };
  212. static struct nand_bbt_descr bbt_mirror_descr = {
  213. .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE
  214. | NAND_BBT_2BIT | NAND_BBT_VERSION,
  215. .offs = 8,
  216. .len = 6,
  217. .veroffs = 14,
  218. .maxblocks = 8, /* Last 8 blocks in each chip */
  219. .pattern = bbt_mirror_pattern
  220. };
  221. static struct nand_ecclayout ecc_layout_2KB_bch4bit = {
  222. .eccbytes = 32,
  223. .eccpos = {
  224. 32, 33, 34, 35, 36, 37, 38, 39,
  225. 40, 41, 42, 43, 44, 45, 46, 47,
  226. 48, 49, 50, 51, 52, 53, 54, 55,
  227. 56, 57, 58, 59, 60, 61, 62, 63},
  228. .oobfree = { {2, 30} }
  229. };
  230. static struct nand_ecclayout ecc_layout_4KB_bch4bit = {
  231. .eccbytes = 64,
  232. .eccpos = {
  233. 32, 33, 34, 35, 36, 37, 38, 39,
  234. 40, 41, 42, 43, 44, 45, 46, 47,
  235. 48, 49, 50, 51, 52, 53, 54, 55,
  236. 56, 57, 58, 59, 60, 61, 62, 63,
  237. 96, 97, 98, 99, 100, 101, 102, 103,
  238. 104, 105, 106, 107, 108, 109, 110, 111,
  239. 112, 113, 114, 115, 116, 117, 118, 119,
  240. 120, 121, 122, 123, 124, 125, 126, 127},
  241. /* Bootrom looks in bytes 0 & 5 for bad blocks */
  242. .oobfree = { {6, 26}, { 64, 32} }
  243. };
  244. static struct nand_ecclayout ecc_layout_4KB_bch8bit = {
  245. .eccbytes = 128,
  246. .eccpos = {
  247. 32, 33, 34, 35, 36, 37, 38, 39,
  248. 40, 41, 42, 43, 44, 45, 46, 47,
  249. 48, 49, 50, 51, 52, 53, 54, 55,
  250. 56, 57, 58, 59, 60, 61, 62, 63},
  251. .oobfree = { }
  252. };
  253. #define NDTR0_tCH(c) (min((c), 7) << 19)
  254. #define NDTR0_tCS(c) (min((c), 7) << 16)
  255. #define NDTR0_tWH(c) (min((c), 7) << 11)
  256. #define NDTR0_tWP(c) (min((c), 7) << 8)
  257. #define NDTR0_tRH(c) (min((c), 7) << 3)
  258. #define NDTR0_tRP(c) (min((c), 7) << 0)
  259. #define NDTR1_tR(c) (min((c), 65535) << 16)
  260. #define NDTR1_tWHR(c) (min((c), 15) << 4)
  261. #define NDTR1_tAR(c) (min((c), 15) << 0)
  262. /* convert nano-seconds to nand flash controller clock cycles */
  263. #define ns2cycle(ns, clk) (int)((ns) * (clk / 1000000) / 1000)
  264. static enum pxa3xx_nand_variant pxa3xx_nand_get_variant(void)
  265. {
  266. /* We only support the Armada 370/XP/38x for now */
  267. return PXA3XX_NAND_VARIANT_ARMADA370;
  268. }
  269. static void pxa3xx_nand_set_timing(struct pxa3xx_nand_host *host,
  270. const struct pxa3xx_nand_timing *t)
  271. {
  272. struct pxa3xx_nand_info *info = host->info_data;
  273. unsigned long nand_clk = mvebu_get_nand_clock();
  274. uint32_t ndtr0, ndtr1;
  275. ndtr0 = NDTR0_tCH(ns2cycle(t->tCH, nand_clk)) |
  276. NDTR0_tCS(ns2cycle(t->tCS, nand_clk)) |
  277. NDTR0_tWH(ns2cycle(t->tWH, nand_clk)) |
  278. NDTR0_tWP(ns2cycle(t->tWP, nand_clk)) |
  279. NDTR0_tRH(ns2cycle(t->tRH, nand_clk)) |
  280. NDTR0_tRP(ns2cycle(t->tRP, nand_clk));
  281. ndtr1 = NDTR1_tR(ns2cycle(t->tR, nand_clk)) |
  282. NDTR1_tWHR(ns2cycle(t->tWHR, nand_clk)) |
  283. NDTR1_tAR(ns2cycle(t->tAR, nand_clk));
  284. info->ndtr0cs0 = ndtr0;
  285. info->ndtr1cs0 = ndtr1;
  286. nand_writel(info, NDTR0CS0, ndtr0);
  287. nand_writel(info, NDTR1CS0, ndtr1);
  288. }
  289. static void pxa3xx_nand_set_sdr_timing(struct pxa3xx_nand_host *host,
  290. const struct nand_sdr_timings *t)
  291. {
  292. struct pxa3xx_nand_info *info = host->info_data;
  293. struct nand_chip *chip = &host->chip;
  294. unsigned long nand_clk = mvebu_get_nand_clock();
  295. uint32_t ndtr0, ndtr1;
  296. u32 tCH_min = DIV_ROUND_UP(t->tCH_min, 1000);
  297. u32 tCS_min = DIV_ROUND_UP(t->tCS_min, 1000);
  298. u32 tWH_min = DIV_ROUND_UP(t->tWH_min, 1000);
  299. u32 tWP_min = DIV_ROUND_UP(t->tWC_min - tWH_min, 1000);
  300. u32 tREH_min = DIV_ROUND_UP(t->tREH_min, 1000);
  301. u32 tRP_min = DIV_ROUND_UP(t->tRC_min - tREH_min, 1000);
  302. u32 tR = chip->chip_delay * 1000;
  303. u32 tWHR_min = DIV_ROUND_UP(t->tWHR_min, 1000);
  304. u32 tAR_min = DIV_ROUND_UP(t->tAR_min, 1000);
  305. /* fallback to a default value if tR = 0 */
  306. if (!tR)
  307. tR = 20000;
  308. ndtr0 = NDTR0_tCH(ns2cycle(tCH_min, nand_clk)) |
  309. NDTR0_tCS(ns2cycle(tCS_min, nand_clk)) |
  310. NDTR0_tWH(ns2cycle(tWH_min, nand_clk)) |
  311. NDTR0_tWP(ns2cycle(tWP_min, nand_clk)) |
  312. NDTR0_tRH(ns2cycle(tREH_min, nand_clk)) |
  313. NDTR0_tRP(ns2cycle(tRP_min, nand_clk));
  314. ndtr1 = NDTR1_tR(ns2cycle(tR, nand_clk)) |
  315. NDTR1_tWHR(ns2cycle(tWHR_min, nand_clk)) |
  316. NDTR1_tAR(ns2cycle(tAR_min, nand_clk));
  317. info->ndtr0cs0 = ndtr0;
  318. info->ndtr1cs0 = ndtr1;
  319. nand_writel(info, NDTR0CS0, ndtr0);
  320. nand_writel(info, NDTR1CS0, ndtr1);
  321. }
  322. static int pxa3xx_nand_init_timings(struct pxa3xx_nand_host *host)
  323. {
  324. const struct nand_sdr_timings *timings;
  325. struct nand_chip *chip = &host->chip;
  326. struct pxa3xx_nand_info *info = host->info_data;
  327. const struct pxa3xx_nand_flash *f = NULL;
  328. int mode, id, ntypes, i;
  329. mode = onfi_get_async_timing_mode(chip);
  330. if (mode == ONFI_TIMING_MODE_UNKNOWN) {
  331. ntypes = ARRAY_SIZE(builtin_flash_types);
  332. chip->cmdfunc(host->mtd, NAND_CMD_READID, 0x00, -1);
  333. id = chip->read_byte(host->mtd);
  334. id |= chip->read_byte(host->mtd) << 0x8;
  335. for (i = 0; i < ntypes; i++) {
  336. f = &builtin_flash_types[i];
  337. if (f->chip_id == id)
  338. break;
  339. }
  340. if (i == ntypes) {
  341. dev_err(&info->pdev->dev, "Error: timings not found\n");
  342. return -EINVAL;
  343. }
  344. pxa3xx_nand_set_timing(host, f->timing);
  345. if (f->flash_width == 16) {
  346. info->reg_ndcr |= NDCR_DWIDTH_M;
  347. chip->options |= NAND_BUSWIDTH_16;
  348. }
  349. info->reg_ndcr |= (f->dfc_width == 16) ? NDCR_DWIDTH_C : 0;
  350. } else {
  351. mode = fls(mode) - 1;
  352. if (mode < 0)
  353. mode = 0;
  354. timings = onfi_async_timing_mode_to_sdr_timings(mode);
  355. if (IS_ERR(timings))
  356. return PTR_ERR(timings);
  357. pxa3xx_nand_set_sdr_timing(host, timings);
  358. }
  359. return 0;
  360. }
  361. /*
  362. * Set the data and OOB size, depending on the selected
  363. * spare and ECC configuration.
  364. * Only applicable to READ0, READOOB and PAGEPROG commands.
  365. */
  366. static void pxa3xx_set_datasize(struct pxa3xx_nand_info *info,
  367. struct mtd_info *mtd)
  368. {
  369. int oob_enable = info->reg_ndcr & NDCR_SPARE_EN;
  370. info->data_size = mtd->writesize;
  371. if (!oob_enable)
  372. return;
  373. info->oob_size = info->spare_size;
  374. if (!info->use_ecc)
  375. info->oob_size += info->ecc_size;
  376. }
  377. /**
  378. * NOTE: it is a must to set ND_RUN first, then write
  379. * command buffer, otherwise, it does not work.
  380. * We enable all the interrupt at the same time, and
  381. * let pxa3xx_nand_irq to handle all logic.
  382. */
  383. static void pxa3xx_nand_start(struct pxa3xx_nand_info *info)
  384. {
  385. uint32_t ndcr;
  386. ndcr = info->reg_ndcr;
  387. if (info->use_ecc) {
  388. ndcr |= NDCR_ECC_EN;
  389. if (info->ecc_bch)
  390. nand_writel(info, NDECCCTRL, 0x1);
  391. } else {
  392. ndcr &= ~NDCR_ECC_EN;
  393. if (info->ecc_bch)
  394. nand_writel(info, NDECCCTRL, 0x0);
  395. }
  396. ndcr &= ~NDCR_DMA_EN;
  397. if (info->use_spare)
  398. ndcr |= NDCR_SPARE_EN;
  399. else
  400. ndcr &= ~NDCR_SPARE_EN;
  401. ndcr |= NDCR_ND_RUN;
  402. /* clear status bits and run */
  403. nand_writel(info, NDCR, 0);
  404. nand_writel(info, NDSR, NDSR_MASK);
  405. nand_writel(info, NDCR, ndcr);
  406. }
  407. static void disable_int(struct pxa3xx_nand_info *info, uint32_t int_mask)
  408. {
  409. uint32_t ndcr;
  410. ndcr = nand_readl(info, NDCR);
  411. nand_writel(info, NDCR, ndcr | int_mask);
  412. }
  413. static void drain_fifo(struct pxa3xx_nand_info *info, void *data, int len)
  414. {
  415. if (info->ecc_bch) {
  416. u32 ts;
  417. /*
  418. * According to the datasheet, when reading from NDDB
  419. * with BCH enabled, after each 32 bytes reads, we
  420. * have to make sure that the NDSR.RDDREQ bit is set.
  421. *
  422. * Drain the FIFO 8 32 bits reads at a time, and skip
  423. * the polling on the last read.
  424. */
  425. while (len > 8) {
  426. readsl(info->mmio_base + NDDB, data, 8);
  427. ts = get_timer(0);
  428. while (!(nand_readl(info, NDSR) & NDSR_RDDREQ)) {
  429. if (get_timer(ts) > TIMEOUT_DRAIN_FIFO) {
  430. dev_err(&info->pdev->dev,
  431. "Timeout on RDDREQ while draining the FIFO\n");
  432. return;
  433. }
  434. }
  435. data += 32;
  436. len -= 8;
  437. }
  438. }
  439. readsl(info->mmio_base + NDDB, data, len);
  440. }
  441. static void handle_data_pio(struct pxa3xx_nand_info *info)
  442. {
  443. unsigned int do_bytes = min(info->data_size, info->chunk_size);
  444. switch (info->state) {
  445. case STATE_PIO_WRITING:
  446. writesl(info->mmio_base + NDDB,
  447. info->data_buff + info->data_buff_pos,
  448. DIV_ROUND_UP(do_bytes, 4));
  449. if (info->oob_size > 0)
  450. writesl(info->mmio_base + NDDB,
  451. info->oob_buff + info->oob_buff_pos,
  452. DIV_ROUND_UP(info->oob_size, 4));
  453. break;
  454. case STATE_PIO_READING:
  455. drain_fifo(info,
  456. info->data_buff + info->data_buff_pos,
  457. DIV_ROUND_UP(do_bytes, 4));
  458. if (info->oob_size > 0)
  459. drain_fifo(info,
  460. info->oob_buff + info->oob_buff_pos,
  461. DIV_ROUND_UP(info->oob_size, 4));
  462. break;
  463. default:
  464. dev_err(&info->pdev->dev, "%s: invalid state %d\n", __func__,
  465. info->state);
  466. BUG();
  467. }
  468. /* Update buffer pointers for multi-page read/write */
  469. info->data_buff_pos += do_bytes;
  470. info->oob_buff_pos += info->oob_size;
  471. info->data_size -= do_bytes;
  472. }
  473. static void pxa3xx_nand_irq_thread(struct pxa3xx_nand_info *info)
  474. {
  475. handle_data_pio(info);
  476. info->state = STATE_CMD_DONE;
  477. nand_writel(info, NDSR, NDSR_WRDREQ | NDSR_RDDREQ);
  478. }
  479. static irqreturn_t pxa3xx_nand_irq(struct pxa3xx_nand_info *info)
  480. {
  481. unsigned int status, is_completed = 0, is_ready = 0;
  482. unsigned int ready, cmd_done;
  483. irqreturn_t ret = IRQ_HANDLED;
  484. if (info->cs == 0) {
  485. ready = NDSR_FLASH_RDY;
  486. cmd_done = NDSR_CS0_CMDD;
  487. } else {
  488. ready = NDSR_RDY;
  489. cmd_done = NDSR_CS1_CMDD;
  490. }
  491. status = nand_readl(info, NDSR);
  492. if (status & NDSR_UNCORERR)
  493. info->retcode = ERR_UNCORERR;
  494. if (status & NDSR_CORERR) {
  495. info->retcode = ERR_CORERR;
  496. if (info->variant == PXA3XX_NAND_VARIANT_ARMADA370 &&
  497. info->ecc_bch)
  498. info->ecc_err_cnt = NDSR_ERR_CNT(status);
  499. else
  500. info->ecc_err_cnt = 1;
  501. /*
  502. * Each chunk composing a page is corrected independently,
  503. * and we need to store maximum number of corrected bitflips
  504. * to return it to the MTD layer in ecc.read_page().
  505. */
  506. info->max_bitflips = max_t(unsigned int,
  507. info->max_bitflips,
  508. info->ecc_err_cnt);
  509. }
  510. if (status & (NDSR_RDDREQ | NDSR_WRDREQ)) {
  511. info->state = (status & NDSR_RDDREQ) ?
  512. STATE_PIO_READING : STATE_PIO_WRITING;
  513. /* Call the IRQ thread in U-Boot directly */
  514. pxa3xx_nand_irq_thread(info);
  515. return 0;
  516. }
  517. if (status & cmd_done) {
  518. info->state = STATE_CMD_DONE;
  519. is_completed = 1;
  520. }
  521. if (status & ready) {
  522. info->state = STATE_READY;
  523. is_ready = 1;
  524. }
  525. if (status & NDSR_WRCMDREQ) {
  526. nand_writel(info, NDSR, NDSR_WRCMDREQ);
  527. status &= ~NDSR_WRCMDREQ;
  528. info->state = STATE_CMD_HANDLE;
  529. /*
  530. * Command buffer registers NDCB{0-2} (and optionally NDCB3)
  531. * must be loaded by writing directly either 12 or 16
  532. * bytes directly to NDCB0, four bytes at a time.
  533. *
  534. * Direct write access to NDCB1, NDCB2 and NDCB3 is ignored
  535. * but each NDCBx register can be read.
  536. */
  537. nand_writel(info, NDCB0, info->ndcb0);
  538. nand_writel(info, NDCB0, info->ndcb1);
  539. nand_writel(info, NDCB0, info->ndcb2);
  540. /* NDCB3 register is available in NFCv2 (Armada 370/XP SoC) */
  541. if (info->variant == PXA3XX_NAND_VARIANT_ARMADA370)
  542. nand_writel(info, NDCB0, info->ndcb3);
  543. }
  544. /* clear NDSR to let the controller exit the IRQ */
  545. nand_writel(info, NDSR, status);
  546. if (is_completed)
  547. info->cmd_complete = 1;
  548. if (is_ready)
  549. info->dev_ready = 1;
  550. return ret;
  551. }
  552. static inline int is_buf_blank(uint8_t *buf, size_t len)
  553. {
  554. for (; len > 0; len--)
  555. if (*buf++ != 0xff)
  556. return 0;
  557. return 1;
  558. }
  559. static void set_command_address(struct pxa3xx_nand_info *info,
  560. unsigned int page_size, uint16_t column, int page_addr)
  561. {
  562. /* small page addr setting */
  563. if (page_size < PAGE_CHUNK_SIZE) {
  564. info->ndcb1 = ((page_addr & 0xFFFFFF) << 8)
  565. | (column & 0xFF);
  566. info->ndcb2 = 0;
  567. } else {
  568. info->ndcb1 = ((page_addr & 0xFFFF) << 16)
  569. | (column & 0xFFFF);
  570. if (page_addr & 0xFF0000)
  571. info->ndcb2 = (page_addr & 0xFF0000) >> 16;
  572. else
  573. info->ndcb2 = 0;
  574. }
  575. }
  576. static void prepare_start_command(struct pxa3xx_nand_info *info, int command)
  577. {
  578. struct pxa3xx_nand_host *host = info->host[info->cs];
  579. struct mtd_info *mtd = host->mtd;
  580. /* reset data and oob column point to handle data */
  581. info->buf_start = 0;
  582. info->buf_count = 0;
  583. info->oob_size = 0;
  584. info->data_buff_pos = 0;
  585. info->oob_buff_pos = 0;
  586. info->use_ecc = 0;
  587. info->use_spare = 1;
  588. info->retcode = ERR_NONE;
  589. info->ecc_err_cnt = 0;
  590. info->ndcb3 = 0;
  591. info->need_wait = 0;
  592. switch (command) {
  593. case NAND_CMD_READ0:
  594. case NAND_CMD_PAGEPROG:
  595. info->use_ecc = 1;
  596. case NAND_CMD_READOOB:
  597. pxa3xx_set_datasize(info, mtd);
  598. break;
  599. case NAND_CMD_PARAM:
  600. info->use_spare = 0;
  601. break;
  602. default:
  603. info->ndcb1 = 0;
  604. info->ndcb2 = 0;
  605. break;
  606. }
  607. /*
  608. * If we are about to issue a read command, or about to set
  609. * the write address, then clean the data buffer.
  610. */
  611. if (command == NAND_CMD_READ0 ||
  612. command == NAND_CMD_READOOB ||
  613. command == NAND_CMD_SEQIN) {
  614. info->buf_count = mtd->writesize + mtd->oobsize;
  615. memset(info->data_buff, 0xFF, info->buf_count);
  616. }
  617. }
  618. static int prepare_set_command(struct pxa3xx_nand_info *info, int command,
  619. int ext_cmd_type, uint16_t column, int page_addr)
  620. {
  621. int addr_cycle, exec_cmd;
  622. struct pxa3xx_nand_host *host;
  623. struct mtd_info *mtd;
  624. host = info->host[info->cs];
  625. mtd = host->mtd;
  626. addr_cycle = 0;
  627. exec_cmd = 1;
  628. if (info->cs != 0)
  629. info->ndcb0 = NDCB0_CSEL;
  630. else
  631. info->ndcb0 = 0;
  632. if (command == NAND_CMD_SEQIN)
  633. exec_cmd = 0;
  634. addr_cycle = NDCB0_ADDR_CYC(host->row_addr_cycles
  635. + host->col_addr_cycles);
  636. switch (command) {
  637. case NAND_CMD_READOOB:
  638. case NAND_CMD_READ0:
  639. info->buf_start = column;
  640. info->ndcb0 |= NDCB0_CMD_TYPE(0)
  641. | addr_cycle
  642. | NAND_CMD_READ0;
  643. if (command == NAND_CMD_READOOB)
  644. info->buf_start += mtd->writesize;
  645. /*
  646. * Multiple page read needs an 'extended command type' field,
  647. * which is either naked-read or last-read according to the
  648. * state.
  649. */
  650. if (mtd->writesize == PAGE_CHUNK_SIZE) {
  651. info->ndcb0 |= NDCB0_DBC | (NAND_CMD_READSTART << 8);
  652. } else if (mtd->writesize > PAGE_CHUNK_SIZE) {
  653. info->ndcb0 |= NDCB0_DBC | (NAND_CMD_READSTART << 8)
  654. | NDCB0_LEN_OVRD
  655. | NDCB0_EXT_CMD_TYPE(ext_cmd_type);
  656. info->ndcb3 = info->chunk_size +
  657. info->oob_size;
  658. }
  659. set_command_address(info, mtd->writesize, column, page_addr);
  660. break;
  661. case NAND_CMD_SEQIN:
  662. info->buf_start = column;
  663. set_command_address(info, mtd->writesize, 0, page_addr);
  664. /*
  665. * Multiple page programming needs to execute the initial
  666. * SEQIN command that sets the page address.
  667. */
  668. if (mtd->writesize > PAGE_CHUNK_SIZE) {
  669. info->ndcb0 |= NDCB0_CMD_TYPE(0x1)
  670. | NDCB0_EXT_CMD_TYPE(ext_cmd_type)
  671. | addr_cycle
  672. | command;
  673. /* No data transfer in this case */
  674. info->data_size = 0;
  675. exec_cmd = 1;
  676. }
  677. break;
  678. case NAND_CMD_PAGEPROG:
  679. if (is_buf_blank(info->data_buff,
  680. (mtd->writesize + mtd->oobsize))) {
  681. exec_cmd = 0;
  682. break;
  683. }
  684. /* Second command setting for large pages */
  685. if (mtd->writesize > PAGE_CHUNK_SIZE) {
  686. /*
  687. * Multiple page write uses the 'extended command'
  688. * field. This can be used to issue a command dispatch
  689. * or a naked-write depending on the current stage.
  690. */
  691. info->ndcb0 |= NDCB0_CMD_TYPE(0x1)
  692. | NDCB0_LEN_OVRD
  693. | NDCB0_EXT_CMD_TYPE(ext_cmd_type);
  694. info->ndcb3 = info->chunk_size +
  695. info->oob_size;
  696. /*
  697. * This is the command dispatch that completes a chunked
  698. * page program operation.
  699. */
  700. if (info->data_size == 0) {
  701. info->ndcb0 = NDCB0_CMD_TYPE(0x1)
  702. | NDCB0_EXT_CMD_TYPE(ext_cmd_type)
  703. | command;
  704. info->ndcb1 = 0;
  705. info->ndcb2 = 0;
  706. info->ndcb3 = 0;
  707. }
  708. } else {
  709. info->ndcb0 |= NDCB0_CMD_TYPE(0x1)
  710. | NDCB0_AUTO_RS
  711. | NDCB0_ST_ROW_EN
  712. | NDCB0_DBC
  713. | (NAND_CMD_PAGEPROG << 8)
  714. | NAND_CMD_SEQIN
  715. | addr_cycle;
  716. }
  717. break;
  718. case NAND_CMD_PARAM:
  719. info->buf_count = 256;
  720. info->ndcb0 |= NDCB0_CMD_TYPE(0)
  721. | NDCB0_ADDR_CYC(1)
  722. | NDCB0_LEN_OVRD
  723. | command;
  724. info->ndcb1 = (column & 0xFF);
  725. info->ndcb3 = 256;
  726. info->data_size = 256;
  727. break;
  728. case NAND_CMD_READID:
  729. info->buf_count = host->read_id_bytes;
  730. info->ndcb0 |= NDCB0_CMD_TYPE(3)
  731. | NDCB0_ADDR_CYC(1)
  732. | command;
  733. info->ndcb1 = (column & 0xFF);
  734. info->data_size = 8;
  735. break;
  736. case NAND_CMD_STATUS:
  737. info->buf_count = 1;
  738. info->ndcb0 |= NDCB0_CMD_TYPE(4)
  739. | NDCB0_ADDR_CYC(1)
  740. | command;
  741. info->data_size = 8;
  742. break;
  743. case NAND_CMD_ERASE1:
  744. info->ndcb0 |= NDCB0_CMD_TYPE(2)
  745. | NDCB0_AUTO_RS
  746. | NDCB0_ADDR_CYC(3)
  747. | NDCB0_DBC
  748. | (NAND_CMD_ERASE2 << 8)
  749. | NAND_CMD_ERASE1;
  750. info->ndcb1 = page_addr;
  751. info->ndcb2 = 0;
  752. break;
  753. case NAND_CMD_RESET:
  754. info->ndcb0 |= NDCB0_CMD_TYPE(5)
  755. | command;
  756. break;
  757. case NAND_CMD_ERASE2:
  758. exec_cmd = 0;
  759. break;
  760. default:
  761. exec_cmd = 0;
  762. dev_err(&info->pdev->dev, "non-supported command %x\n",
  763. command);
  764. break;
  765. }
  766. return exec_cmd;
  767. }
  768. static void nand_cmdfunc(struct mtd_info *mtd, unsigned command,
  769. int column, int page_addr)
  770. {
  771. struct nand_chip *chip = mtd_to_nand(mtd);
  772. struct pxa3xx_nand_host *host = nand_get_controller_data(chip);
  773. struct pxa3xx_nand_info *info = host->info_data;
  774. int exec_cmd;
  775. /*
  776. * if this is a x16 device ,then convert the input
  777. * "byte" address into a "word" address appropriate
  778. * for indexing a word-oriented device
  779. */
  780. if (info->reg_ndcr & NDCR_DWIDTH_M)
  781. column /= 2;
  782. /*
  783. * There may be different NAND chip hooked to
  784. * different chip select, so check whether
  785. * chip select has been changed, if yes, reset the timing
  786. */
  787. if (info->cs != host->cs) {
  788. info->cs = host->cs;
  789. nand_writel(info, NDTR0CS0, info->ndtr0cs0);
  790. nand_writel(info, NDTR1CS0, info->ndtr1cs0);
  791. }
  792. prepare_start_command(info, command);
  793. info->state = STATE_PREPARED;
  794. exec_cmd = prepare_set_command(info, command, 0, column, page_addr);
  795. if (exec_cmd) {
  796. u32 ts;
  797. info->cmd_complete = 0;
  798. info->dev_ready = 0;
  799. info->need_wait = 1;
  800. pxa3xx_nand_start(info);
  801. ts = get_timer(0);
  802. while (1) {
  803. u32 status;
  804. status = nand_readl(info, NDSR);
  805. if (status)
  806. pxa3xx_nand_irq(info);
  807. if (info->cmd_complete)
  808. break;
  809. if (get_timer(ts) > CHIP_DELAY_TIMEOUT) {
  810. dev_err(&info->pdev->dev, "Wait timeout!!!\n");
  811. return;
  812. }
  813. }
  814. }
  815. info->state = STATE_IDLE;
  816. }
  817. static void nand_cmdfunc_extended(struct mtd_info *mtd,
  818. const unsigned command,
  819. int column, int page_addr)
  820. {
  821. struct nand_chip *chip = mtd_to_nand(mtd);
  822. struct pxa3xx_nand_host *host = nand_get_controller_data(chip);
  823. struct pxa3xx_nand_info *info = host->info_data;
  824. int exec_cmd, ext_cmd_type;
  825. /*
  826. * if this is a x16 device then convert the input
  827. * "byte" address into a "word" address appropriate
  828. * for indexing a word-oriented device
  829. */
  830. if (info->reg_ndcr & NDCR_DWIDTH_M)
  831. column /= 2;
  832. /*
  833. * There may be different NAND chip hooked to
  834. * different chip select, so check whether
  835. * chip select has been changed, if yes, reset the timing
  836. */
  837. if (info->cs != host->cs) {
  838. info->cs = host->cs;
  839. nand_writel(info, NDTR0CS0, info->ndtr0cs0);
  840. nand_writel(info, NDTR1CS0, info->ndtr1cs0);
  841. }
  842. /* Select the extended command for the first command */
  843. switch (command) {
  844. case NAND_CMD_READ0:
  845. case NAND_CMD_READOOB:
  846. ext_cmd_type = EXT_CMD_TYPE_MONO;
  847. break;
  848. case NAND_CMD_SEQIN:
  849. ext_cmd_type = EXT_CMD_TYPE_DISPATCH;
  850. break;
  851. case NAND_CMD_PAGEPROG:
  852. ext_cmd_type = EXT_CMD_TYPE_NAKED_RW;
  853. break;
  854. default:
  855. ext_cmd_type = 0;
  856. break;
  857. }
  858. prepare_start_command(info, command);
  859. /*
  860. * Prepare the "is ready" completion before starting a command
  861. * transaction sequence. If the command is not executed the
  862. * completion will be completed, see below.
  863. *
  864. * We can do that inside the loop because the command variable
  865. * is invariant and thus so is the exec_cmd.
  866. */
  867. info->need_wait = 1;
  868. info->dev_ready = 0;
  869. do {
  870. u32 ts;
  871. info->state = STATE_PREPARED;
  872. exec_cmd = prepare_set_command(info, command, ext_cmd_type,
  873. column, page_addr);
  874. if (!exec_cmd) {
  875. info->need_wait = 0;
  876. info->dev_ready = 1;
  877. break;
  878. }
  879. info->cmd_complete = 0;
  880. pxa3xx_nand_start(info);
  881. ts = get_timer(0);
  882. while (1) {
  883. u32 status;
  884. status = nand_readl(info, NDSR);
  885. if (status)
  886. pxa3xx_nand_irq(info);
  887. if (info->cmd_complete)
  888. break;
  889. if (get_timer(ts) > CHIP_DELAY_TIMEOUT) {
  890. dev_err(&info->pdev->dev, "Wait timeout!!!\n");
  891. return;
  892. }
  893. }
  894. /* Check if the sequence is complete */
  895. if (info->data_size == 0 && command != NAND_CMD_PAGEPROG)
  896. break;
  897. /*
  898. * After a splitted program command sequence has issued
  899. * the command dispatch, the command sequence is complete.
  900. */
  901. if (info->data_size == 0 &&
  902. command == NAND_CMD_PAGEPROG &&
  903. ext_cmd_type == EXT_CMD_TYPE_DISPATCH)
  904. break;
  905. if (command == NAND_CMD_READ0 || command == NAND_CMD_READOOB) {
  906. /* Last read: issue a 'last naked read' */
  907. if (info->data_size == info->chunk_size)
  908. ext_cmd_type = EXT_CMD_TYPE_LAST_RW;
  909. else
  910. ext_cmd_type = EXT_CMD_TYPE_NAKED_RW;
  911. /*
  912. * If a splitted program command has no more data to transfer,
  913. * the command dispatch must be issued to complete.
  914. */
  915. } else if (command == NAND_CMD_PAGEPROG &&
  916. info->data_size == 0) {
  917. ext_cmd_type = EXT_CMD_TYPE_DISPATCH;
  918. }
  919. } while (1);
  920. info->state = STATE_IDLE;
  921. }
  922. static int pxa3xx_nand_write_page_hwecc(struct mtd_info *mtd,
  923. struct nand_chip *chip, const uint8_t *buf, int oob_required)
  924. {
  925. chip->write_buf(mtd, buf, mtd->writesize);
  926. chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
  927. return 0;
  928. }
  929. static int pxa3xx_nand_read_page_hwecc(struct mtd_info *mtd,
  930. struct nand_chip *chip, uint8_t *buf, int oob_required,
  931. int page)
  932. {
  933. struct pxa3xx_nand_host *host = nand_get_controller_data(chip);
  934. struct pxa3xx_nand_info *info = host->info_data;
  935. chip->read_buf(mtd, buf, mtd->writesize);
  936. chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
  937. if (info->retcode == ERR_CORERR && info->use_ecc) {
  938. mtd->ecc_stats.corrected += info->ecc_err_cnt;
  939. } else if (info->retcode == ERR_UNCORERR) {
  940. /*
  941. * for blank page (all 0xff), HW will calculate its ECC as
  942. * 0, which is different from the ECC information within
  943. * OOB, ignore such uncorrectable errors
  944. */
  945. if (is_buf_blank(buf, mtd->writesize))
  946. info->retcode = ERR_NONE;
  947. else
  948. mtd->ecc_stats.failed++;
  949. }
  950. return info->max_bitflips;
  951. }
  952. static uint8_t pxa3xx_nand_read_byte(struct mtd_info *mtd)
  953. {
  954. struct nand_chip *chip = mtd_to_nand(mtd);
  955. struct pxa3xx_nand_host *host = nand_get_controller_data(chip);
  956. struct pxa3xx_nand_info *info = host->info_data;
  957. char retval = 0xFF;
  958. if (info->buf_start < info->buf_count)
  959. /* Has just send a new command? */
  960. retval = info->data_buff[info->buf_start++];
  961. return retval;
  962. }
  963. static u16 pxa3xx_nand_read_word(struct mtd_info *mtd)
  964. {
  965. struct nand_chip *chip = mtd_to_nand(mtd);
  966. struct pxa3xx_nand_host *host = nand_get_controller_data(chip);
  967. struct pxa3xx_nand_info *info = host->info_data;
  968. u16 retval = 0xFFFF;
  969. if (!(info->buf_start & 0x01) && info->buf_start < info->buf_count) {
  970. retval = *((u16 *)(info->data_buff+info->buf_start));
  971. info->buf_start += 2;
  972. }
  973. return retval;
  974. }
  975. static void pxa3xx_nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
  976. {
  977. struct nand_chip *chip = mtd_to_nand(mtd);
  978. struct pxa3xx_nand_host *host = nand_get_controller_data(chip);
  979. struct pxa3xx_nand_info *info = host->info_data;
  980. int real_len = min_t(size_t, len, info->buf_count - info->buf_start);
  981. memcpy(buf, info->data_buff + info->buf_start, real_len);
  982. info->buf_start += real_len;
  983. }
  984. static void pxa3xx_nand_write_buf(struct mtd_info *mtd,
  985. const uint8_t *buf, int len)
  986. {
  987. struct nand_chip *chip = mtd_to_nand(mtd);
  988. struct pxa3xx_nand_host *host = nand_get_controller_data(chip);
  989. struct pxa3xx_nand_info *info = host->info_data;
  990. int real_len = min_t(size_t, len, info->buf_count - info->buf_start);
  991. memcpy(info->data_buff + info->buf_start, buf, real_len);
  992. info->buf_start += real_len;
  993. }
  994. static void pxa3xx_nand_select_chip(struct mtd_info *mtd, int chip)
  995. {
  996. return;
  997. }
  998. static int pxa3xx_nand_waitfunc(struct mtd_info *mtd, struct nand_chip *this)
  999. {
  1000. struct nand_chip *chip = mtd_to_nand(mtd);
  1001. struct pxa3xx_nand_host *host = nand_get_controller_data(chip);
  1002. struct pxa3xx_nand_info *info = host->info_data;
  1003. if (info->need_wait) {
  1004. u32 ts;
  1005. info->need_wait = 0;
  1006. ts = get_timer(0);
  1007. while (1) {
  1008. u32 status;
  1009. status = nand_readl(info, NDSR);
  1010. if (status)
  1011. pxa3xx_nand_irq(info);
  1012. if (info->dev_ready)
  1013. break;
  1014. if (get_timer(ts) > CHIP_DELAY_TIMEOUT) {
  1015. dev_err(&info->pdev->dev, "Ready timeout!!!\n");
  1016. return NAND_STATUS_FAIL;
  1017. }
  1018. }
  1019. }
  1020. /* pxa3xx_nand_send_command has waited for command complete */
  1021. if (this->state == FL_WRITING || this->state == FL_ERASING) {
  1022. if (info->retcode == ERR_NONE)
  1023. return 0;
  1024. else
  1025. return NAND_STATUS_FAIL;
  1026. }
  1027. return NAND_STATUS_READY;
  1028. }
  1029. static int pxa3xx_nand_config_flash(struct pxa3xx_nand_info *info)
  1030. {
  1031. struct pxa3xx_nand_host *host = info->host[info->cs];
  1032. struct mtd_info *mtd = host->mtd;
  1033. struct nand_chip *chip = mtd_to_nand(mtd);
  1034. info->reg_ndcr |= (host->col_addr_cycles == 2) ? NDCR_RA_START : 0;
  1035. info->reg_ndcr |= (chip->page_shift == 6) ? NDCR_PG_PER_BLK : 0;
  1036. info->reg_ndcr |= (mtd->writesize == 2048) ? NDCR_PAGE_SZ : 0;
  1037. return 0;
  1038. }
  1039. static int pxa3xx_nand_detect_config(struct pxa3xx_nand_info *info)
  1040. {
  1041. /*
  1042. * We set 0 by hard coding here, for we don't support keep_config
  1043. * when there is more than one chip attached to the controller
  1044. */
  1045. struct pxa3xx_nand_host *host = info->host[0];
  1046. uint32_t ndcr = nand_readl(info, NDCR);
  1047. if (ndcr & NDCR_PAGE_SZ) {
  1048. /* Controller's FIFO size */
  1049. info->chunk_size = 2048;
  1050. host->read_id_bytes = 4;
  1051. } else {
  1052. info->chunk_size = 512;
  1053. host->read_id_bytes = 2;
  1054. }
  1055. /* Set an initial chunk size */
  1056. info->reg_ndcr = ndcr & ~NDCR_INT_MASK;
  1057. info->ndtr0cs0 = nand_readl(info, NDTR0CS0);
  1058. info->ndtr1cs0 = nand_readl(info, NDTR1CS0);
  1059. return 0;
  1060. }
  1061. static int pxa3xx_nand_init_buff(struct pxa3xx_nand_info *info)
  1062. {
  1063. info->data_buff = kmalloc(info->buf_size, GFP_KERNEL);
  1064. if (info->data_buff == NULL)
  1065. return -ENOMEM;
  1066. return 0;
  1067. }
  1068. static int pxa3xx_nand_sensing(struct pxa3xx_nand_host *host)
  1069. {
  1070. struct pxa3xx_nand_info *info = host->info_data;
  1071. struct pxa3xx_nand_platform_data *pdata = info->pdata;
  1072. struct mtd_info *mtd;
  1073. struct nand_chip *chip;
  1074. const struct nand_sdr_timings *timings;
  1075. int ret;
  1076. mtd = info->host[info->cs]->mtd;
  1077. chip = mtd_to_nand(mtd);
  1078. /* configure default flash values */
  1079. info->reg_ndcr = 0x0; /* enable all interrupts */
  1080. info->reg_ndcr |= (pdata->enable_arbiter) ? NDCR_ND_ARB_EN : 0;
  1081. info->reg_ndcr |= NDCR_RD_ID_CNT(host->read_id_bytes);
  1082. info->reg_ndcr |= NDCR_SPARE_EN; /* enable spare by default */
  1083. /* use the common timing to make a try */
  1084. timings = onfi_async_timing_mode_to_sdr_timings(0);
  1085. if (IS_ERR(timings))
  1086. return PTR_ERR(timings);
  1087. pxa3xx_nand_set_sdr_timing(host, timings);
  1088. chip->cmdfunc(mtd, NAND_CMD_RESET, 0, 0);
  1089. ret = chip->waitfunc(mtd, chip);
  1090. if (ret & NAND_STATUS_FAIL)
  1091. return -ENODEV;
  1092. return 0;
  1093. }
  1094. static int pxa_ecc_init(struct pxa3xx_nand_info *info,
  1095. struct nand_ecc_ctrl *ecc,
  1096. int strength, int ecc_stepsize, int page_size)
  1097. {
  1098. if (strength == 1 && ecc_stepsize == 512 && page_size == 2048) {
  1099. info->chunk_size = 2048;
  1100. info->spare_size = 40;
  1101. info->ecc_size = 24;
  1102. ecc->mode = NAND_ECC_HW;
  1103. ecc->size = 512;
  1104. ecc->strength = 1;
  1105. } else if (strength == 1 && ecc_stepsize == 512 && page_size == 512) {
  1106. info->chunk_size = 512;
  1107. info->spare_size = 8;
  1108. info->ecc_size = 8;
  1109. ecc->mode = NAND_ECC_HW;
  1110. ecc->size = 512;
  1111. ecc->strength = 1;
  1112. /*
  1113. * Required ECC: 4-bit correction per 512 bytes
  1114. * Select: 16-bit correction per 2048 bytes
  1115. */
  1116. } else if (strength == 4 && ecc_stepsize == 512 && page_size == 2048) {
  1117. info->ecc_bch = 1;
  1118. info->chunk_size = 2048;
  1119. info->spare_size = 32;
  1120. info->ecc_size = 32;
  1121. ecc->mode = NAND_ECC_HW;
  1122. ecc->size = info->chunk_size;
  1123. ecc->layout = &ecc_layout_2KB_bch4bit;
  1124. ecc->strength = 16;
  1125. } else if (strength == 4 && ecc_stepsize == 512 && page_size == 4096) {
  1126. info->ecc_bch = 1;
  1127. info->chunk_size = 2048;
  1128. info->spare_size = 32;
  1129. info->ecc_size = 32;
  1130. ecc->mode = NAND_ECC_HW;
  1131. ecc->size = info->chunk_size;
  1132. ecc->layout = &ecc_layout_4KB_bch4bit;
  1133. ecc->strength = 16;
  1134. /*
  1135. * Required ECC: 8-bit correction per 512 bytes
  1136. * Select: 16-bit correction per 1024 bytes
  1137. */
  1138. } else if (strength == 8 && ecc_stepsize == 512 && page_size == 4096) {
  1139. info->ecc_bch = 1;
  1140. info->chunk_size = 1024;
  1141. info->spare_size = 0;
  1142. info->ecc_size = 32;
  1143. ecc->mode = NAND_ECC_HW;
  1144. ecc->size = info->chunk_size;
  1145. ecc->layout = &ecc_layout_4KB_bch8bit;
  1146. ecc->strength = 16;
  1147. } else {
  1148. dev_err(&info->pdev->dev,
  1149. "ECC strength %d at page size %d is not supported\n",
  1150. strength, page_size);
  1151. return -ENODEV;
  1152. }
  1153. return 0;
  1154. }
  1155. static int pxa3xx_nand_scan(struct mtd_info *mtd)
  1156. {
  1157. struct nand_chip *chip = mtd_to_nand(mtd);
  1158. struct pxa3xx_nand_host *host = nand_get_controller_data(chip);
  1159. struct pxa3xx_nand_info *info = host->info_data;
  1160. struct pxa3xx_nand_platform_data *pdata = info->pdata;
  1161. int ret;
  1162. uint16_t ecc_strength, ecc_step;
  1163. if (pdata->keep_config && !pxa3xx_nand_detect_config(info))
  1164. goto KEEP_CONFIG;
  1165. /* Set a default chunk size */
  1166. info->chunk_size = 512;
  1167. ret = pxa3xx_nand_sensing(host);
  1168. if (ret) {
  1169. dev_info(&info->pdev->dev, "There is no chip on cs %d!\n",
  1170. info->cs);
  1171. return ret;
  1172. }
  1173. KEEP_CONFIG:
  1174. /* Device detection must be done with ECC disabled */
  1175. if (info->variant == PXA3XX_NAND_VARIANT_ARMADA370)
  1176. nand_writel(info, NDECCCTRL, 0x0);
  1177. if (nand_scan_ident(mtd, 1, NULL))
  1178. return -ENODEV;
  1179. if (!pdata->keep_config) {
  1180. ret = pxa3xx_nand_init_timings(host);
  1181. if (ret) {
  1182. dev_err(&info->pdev->dev,
  1183. "Failed to set timings: %d\n", ret);
  1184. return ret;
  1185. }
  1186. }
  1187. ret = pxa3xx_nand_config_flash(info);
  1188. if (ret)
  1189. return ret;
  1190. #ifdef CONFIG_SYS_NAND_USE_FLASH_BBT
  1191. /*
  1192. * We'll use a bad block table stored in-flash and don't
  1193. * allow writing the bad block marker to the flash.
  1194. */
  1195. chip->bbt_options |= NAND_BBT_USE_FLASH | NAND_BBT_NO_OOB_BBM;
  1196. chip->bbt_td = &bbt_main_descr;
  1197. chip->bbt_md = &bbt_mirror_descr;
  1198. #endif
  1199. /*
  1200. * If the page size is bigger than the FIFO size, let's check
  1201. * we are given the right variant and then switch to the extended
  1202. * (aka splitted) command handling,
  1203. */
  1204. if (mtd->writesize > PAGE_CHUNK_SIZE) {
  1205. if (info->variant == PXA3XX_NAND_VARIANT_ARMADA370) {
  1206. chip->cmdfunc = nand_cmdfunc_extended;
  1207. } else {
  1208. dev_err(&info->pdev->dev,
  1209. "unsupported page size on this variant\n");
  1210. return -ENODEV;
  1211. }
  1212. }
  1213. if (pdata->ecc_strength && pdata->ecc_step_size) {
  1214. ecc_strength = pdata->ecc_strength;
  1215. ecc_step = pdata->ecc_step_size;
  1216. } else {
  1217. ecc_strength = chip->ecc_strength_ds;
  1218. ecc_step = chip->ecc_step_ds;
  1219. }
  1220. /* Set default ECC strength requirements on non-ONFI devices */
  1221. if (ecc_strength < 1 && ecc_step < 1) {
  1222. ecc_strength = 1;
  1223. ecc_step = 512;
  1224. }
  1225. ret = pxa_ecc_init(info, &chip->ecc, ecc_strength,
  1226. ecc_step, mtd->writesize);
  1227. if (ret)
  1228. return ret;
  1229. /* calculate addressing information */
  1230. if (mtd->writesize >= 2048)
  1231. host->col_addr_cycles = 2;
  1232. else
  1233. host->col_addr_cycles = 1;
  1234. /* release the initial buffer */
  1235. kfree(info->data_buff);
  1236. /* allocate the real data + oob buffer */
  1237. info->buf_size = mtd->writesize + mtd->oobsize;
  1238. ret = pxa3xx_nand_init_buff(info);
  1239. if (ret)
  1240. return ret;
  1241. info->oob_buff = info->data_buff + mtd->writesize;
  1242. if ((mtd->size >> chip->page_shift) > 65536)
  1243. host->row_addr_cycles = 3;
  1244. else
  1245. host->row_addr_cycles = 2;
  1246. return nand_scan_tail(mtd);
  1247. }
  1248. static int alloc_nand_resource(struct pxa3xx_nand_info *info)
  1249. {
  1250. struct pxa3xx_nand_platform_data *pdata;
  1251. struct pxa3xx_nand_host *host;
  1252. struct nand_chip *chip = NULL;
  1253. struct mtd_info *mtd;
  1254. int ret, cs;
  1255. pdata = info->pdata;
  1256. if (pdata->num_cs <= 0)
  1257. return -ENODEV;
  1258. info->variant = pxa3xx_nand_get_variant();
  1259. for (cs = 0; cs < pdata->num_cs; cs++) {
  1260. chip = (struct nand_chip *)
  1261. ((u8 *)&info[1] + sizeof(*host) * cs);
  1262. mtd = nand_to_mtd(chip);
  1263. host = (struct pxa3xx_nand_host *)chip;
  1264. info->host[cs] = host;
  1265. host->mtd = mtd;
  1266. host->cs = cs;
  1267. host->info_data = info;
  1268. host->read_id_bytes = 4;
  1269. mtd->owner = THIS_MODULE;
  1270. chip->ecc.read_page = pxa3xx_nand_read_page_hwecc;
  1271. chip->ecc.write_page = pxa3xx_nand_write_page_hwecc;
  1272. chip->controller = &info->controller;
  1273. chip->waitfunc = pxa3xx_nand_waitfunc;
  1274. chip->select_chip = pxa3xx_nand_select_chip;
  1275. chip->read_word = pxa3xx_nand_read_word;
  1276. chip->read_byte = pxa3xx_nand_read_byte;
  1277. chip->read_buf = pxa3xx_nand_read_buf;
  1278. chip->write_buf = pxa3xx_nand_write_buf;
  1279. chip->options |= NAND_NO_SUBPAGE_WRITE;
  1280. chip->cmdfunc = nand_cmdfunc;
  1281. }
  1282. info->mmio_base = (void __iomem *)MVEBU_NAND_BASE;
  1283. /* Allocate a buffer to allow flash detection */
  1284. info->buf_size = INIT_BUFFER_SIZE;
  1285. info->data_buff = kmalloc(info->buf_size, GFP_KERNEL);
  1286. if (info->data_buff == NULL) {
  1287. ret = -ENOMEM;
  1288. goto fail_disable_clk;
  1289. }
  1290. /* initialize all interrupts to be disabled */
  1291. disable_int(info, NDSR_MASK);
  1292. return 0;
  1293. kfree(info->data_buff);
  1294. fail_disable_clk:
  1295. return ret;
  1296. }
  1297. static int pxa3xx_nand_probe_dt(struct pxa3xx_nand_info *info)
  1298. {
  1299. struct pxa3xx_nand_platform_data *pdata;
  1300. pdata = kzalloc(sizeof(*pdata), GFP_KERNEL);
  1301. if (!pdata)
  1302. return -ENOMEM;
  1303. pdata->enable_arbiter = 1;
  1304. pdata->num_cs = 1;
  1305. info->pdata = pdata;
  1306. return 0;
  1307. }
  1308. static int pxa3xx_nand_probe(struct pxa3xx_nand_info *info)
  1309. {
  1310. struct pxa3xx_nand_platform_data *pdata;
  1311. int ret, cs, probe_success;
  1312. ret = pxa3xx_nand_probe_dt(info);
  1313. if (ret)
  1314. return ret;
  1315. pdata = info->pdata;
  1316. ret = alloc_nand_resource(info);
  1317. if (ret) {
  1318. dev_err(&pdev->dev, "alloc nand resource failed\n");
  1319. return ret;
  1320. }
  1321. probe_success = 0;
  1322. for (cs = 0; cs < pdata->num_cs; cs++) {
  1323. struct mtd_info *mtd = info->host[cs]->mtd;
  1324. /*
  1325. * The mtd name matches the one used in 'mtdparts' kernel
  1326. * parameter. This name cannot be changed or otherwise
  1327. * user's mtd partitions configuration would get broken.
  1328. */
  1329. mtd->name = "pxa3xx_nand-0";
  1330. info->cs = cs;
  1331. ret = pxa3xx_nand_scan(mtd);
  1332. if (ret) {
  1333. dev_info(&pdev->dev, "failed to scan nand at cs %d\n",
  1334. cs);
  1335. continue;
  1336. }
  1337. if (nand_register(cs, mtd))
  1338. continue;
  1339. probe_success = 1;
  1340. }
  1341. if (!probe_success)
  1342. return -ENODEV;
  1343. return 0;
  1344. }
  1345. /*
  1346. * Main initialization routine
  1347. */
  1348. void board_nand_init(void)
  1349. {
  1350. struct pxa3xx_nand_info *info;
  1351. struct pxa3xx_nand_host *host;
  1352. int ret;
  1353. info = kzalloc(sizeof(*info) +
  1354. sizeof(*host) * CONFIG_SYS_MAX_NAND_DEVICE,
  1355. GFP_KERNEL);
  1356. if (!info)
  1357. return;
  1358. ret = pxa3xx_nand_probe(info);
  1359. if (ret)
  1360. return;
  1361. }