mxs_nand.c 33 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676677678679680681682683684685686687688689690691692693694695696697698699700701702703704705706707708709710711712713714715716717718719720721722723724725726727728729730731732733734735736737738739740741742743744745746747748749750751752753754755756757758759760761762763764765766767768769770771772773774775776777778779780781782783784785786787788789790791792793794795796797798799800801802803804805806807808809810811812813814815816817818819820821822823824825826827828829830831832833834835836837838839840841842843844845846847848849850851852853854855856857858859860861862863864865866867868869870871872873874875876877878879880881882883884885886887888889890891892893894895896897898899900901902903904905906907908909910911912913914915916917918919920921922923924925926927928929930931932933934935936937938939940941942943944945946947948949950951952953954955956957958959960961962963964965966967968969970971972973974975976977978979980981982983984985986987988989990991992993994995996997998999100010011002100310041005100610071008100910101011101210131014101510161017101810191020102110221023102410251026102710281029103010311032103310341035103610371038103910401041104210431044104510461047104810491050105110521053105410551056105710581059106010611062106310641065106610671068106910701071107210731074107510761077107810791080108110821083108410851086108710881089109010911092109310941095109610971098109911001101110211031104110511061107110811091110111111121113111411151116111711181119112011211122112311241125112611271128112911301131113211331134113511361137113811391140114111421143114411451146114711481149115011511152115311541155115611571158115911601161116211631164116511661167116811691170117111721173117411751176117711781179118011811182118311841185118611871188118911901191119211931194119511961197119811991200120112021203120412051206120712081209121012111212
  1. /*
  2. * Freescale i.MX28 NAND flash driver
  3. *
  4. * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
  5. * on behalf of DENX Software Engineering GmbH
  6. *
  7. * Based on code from LTIB:
  8. * Freescale GPMI NFC NAND Flash Driver
  9. *
  10. * Copyright (C) 2010 Freescale Semiconductor, Inc.
  11. * Copyright (C) 2008 Embedded Alley Solutions, Inc.
  12. *
  13. * SPDX-License-Identifier: GPL-2.0+
  14. */
  15. #include <common.h>
  16. #include <linux/mtd/mtd.h>
  17. #include <linux/mtd/nand.h>
  18. #include <linux/types.h>
  19. #include <malloc.h>
  20. #include <asm/errno.h>
  21. #include <asm/io.h>
  22. #include <asm/arch/clock.h>
  23. #include <asm/arch/imx-regs.h>
  24. #include <asm/imx-common/regs-bch.h>
  25. #include <asm/imx-common/regs-gpmi.h>
  26. #include <asm/arch/sys_proto.h>
  27. #include <asm/imx-common/dma.h>
  28. #define MXS_NAND_DMA_DESCRIPTOR_COUNT 4
  29. #define MXS_NAND_CHUNK_DATA_CHUNK_SIZE 512
  30. #if (defined(CONFIG_MX6) || defined(CONFIG_MX7))
  31. #define MXS_NAND_CHUNK_DATA_CHUNK_SIZE_SHIFT 2
  32. #else
  33. #define MXS_NAND_CHUNK_DATA_CHUNK_SIZE_SHIFT 0
  34. #endif
  35. #define MXS_NAND_METADATA_SIZE 10
  36. #define MXS_NAND_BITS_PER_ECC_LEVEL 13
  37. #define MXS_NAND_COMMAND_BUFFER_SIZE 32
  38. #define MXS_NAND_BCH_TIMEOUT 10000
  39. struct mxs_nand_info {
  40. int cur_chip;
  41. uint32_t cmd_queue_len;
  42. uint32_t data_buf_size;
  43. uint8_t *cmd_buf;
  44. uint8_t *data_buf;
  45. uint8_t *oob_buf;
  46. uint8_t marking_block_bad;
  47. uint8_t raw_oob_mode;
  48. /* Functions with altered behaviour */
  49. int (*hooked_read_oob)(struct mtd_info *mtd,
  50. loff_t from, struct mtd_oob_ops *ops);
  51. int (*hooked_write_oob)(struct mtd_info *mtd,
  52. loff_t to, struct mtd_oob_ops *ops);
  53. int (*hooked_block_markbad)(struct mtd_info *mtd,
  54. loff_t ofs);
  55. /* DMA descriptors */
  56. struct mxs_dma_desc **desc;
  57. uint32_t desc_index;
  58. };
  59. struct nand_ecclayout fake_ecc_layout;
  60. static int chunk_data_size = MXS_NAND_CHUNK_DATA_CHUNK_SIZE;
  61. static int galois_field = 13;
  62. /*
  63. * Cache management functions
  64. */
  65. #ifndef CONFIG_SYS_DCACHE_OFF
  66. static void mxs_nand_flush_data_buf(struct mxs_nand_info *info)
  67. {
  68. uint32_t addr = (uint32_t)info->data_buf;
  69. flush_dcache_range(addr, addr + info->data_buf_size);
  70. }
  71. static void mxs_nand_inval_data_buf(struct mxs_nand_info *info)
  72. {
  73. uint32_t addr = (uint32_t)info->data_buf;
  74. invalidate_dcache_range(addr, addr + info->data_buf_size);
  75. }
  76. static void mxs_nand_flush_cmd_buf(struct mxs_nand_info *info)
  77. {
  78. uint32_t addr = (uint32_t)info->cmd_buf;
  79. flush_dcache_range(addr, addr + MXS_NAND_COMMAND_BUFFER_SIZE);
  80. }
  81. #else
  82. static inline void mxs_nand_flush_data_buf(struct mxs_nand_info *info) {}
  83. static inline void mxs_nand_inval_data_buf(struct mxs_nand_info *info) {}
  84. static inline void mxs_nand_flush_cmd_buf(struct mxs_nand_info *info) {}
  85. #endif
  86. static struct mxs_dma_desc *mxs_nand_get_dma_desc(struct mxs_nand_info *info)
  87. {
  88. struct mxs_dma_desc *desc;
  89. if (info->desc_index >= MXS_NAND_DMA_DESCRIPTOR_COUNT) {
  90. printf("MXS NAND: Too many DMA descriptors requested\n");
  91. return NULL;
  92. }
  93. desc = info->desc[info->desc_index];
  94. info->desc_index++;
  95. return desc;
  96. }
  97. static void mxs_nand_return_dma_descs(struct mxs_nand_info *info)
  98. {
  99. int i;
  100. struct mxs_dma_desc *desc;
  101. for (i = 0; i < info->desc_index; i++) {
  102. desc = info->desc[i];
  103. memset(desc, 0, sizeof(struct mxs_dma_desc));
  104. desc->address = (dma_addr_t)desc;
  105. }
  106. info->desc_index = 0;
  107. }
  108. static uint32_t mxs_nand_ecc_chunk_cnt(uint32_t page_data_size)
  109. {
  110. return page_data_size / chunk_data_size;
  111. }
  112. static uint32_t mxs_nand_ecc_size_in_bits(uint32_t ecc_strength)
  113. {
  114. return ecc_strength * galois_field;
  115. }
  116. static uint32_t mxs_nand_aux_status_offset(void)
  117. {
  118. return (MXS_NAND_METADATA_SIZE + 0x3) & ~0x3;
  119. }
  120. static inline uint32_t mxs_nand_get_ecc_strength(uint32_t page_data_size,
  121. uint32_t page_oob_size)
  122. {
  123. int ecc_strength;
  124. int max_ecc_strength_supported;
  125. /* Refer to Chapter 17 for i.MX6DQ, Chapter 18 for i.MX6SX */
  126. if (is_cpu_type(MXC_CPU_MX6SX) || is_soc_type(MXC_SOC_MX7))
  127. max_ecc_strength_supported = 62;
  128. else
  129. max_ecc_strength_supported = 40;
  130. /*
  131. * Determine the ECC layout with the formula:
  132. * ECC bits per chunk = (total page spare data bits) /
  133. * (bits per ECC level) / (chunks per page)
  134. * where:
  135. * total page spare data bits =
  136. * (page oob size - meta data size) * (bits per byte)
  137. */
  138. ecc_strength = ((page_oob_size - MXS_NAND_METADATA_SIZE) * 8)
  139. / (galois_field *
  140. mxs_nand_ecc_chunk_cnt(page_data_size));
  141. return min(round_down(ecc_strength, 2), max_ecc_strength_supported);
  142. }
  143. static inline uint32_t mxs_nand_get_mark_offset(uint32_t page_data_size,
  144. uint32_t ecc_strength)
  145. {
  146. uint32_t chunk_data_size_in_bits;
  147. uint32_t chunk_ecc_size_in_bits;
  148. uint32_t chunk_total_size_in_bits;
  149. uint32_t block_mark_chunk_number;
  150. uint32_t block_mark_chunk_bit_offset;
  151. uint32_t block_mark_bit_offset;
  152. chunk_data_size_in_bits = chunk_data_size * 8;
  153. chunk_ecc_size_in_bits = mxs_nand_ecc_size_in_bits(ecc_strength);
  154. chunk_total_size_in_bits =
  155. chunk_data_size_in_bits + chunk_ecc_size_in_bits;
  156. /* Compute the bit offset of the block mark within the physical page. */
  157. block_mark_bit_offset = page_data_size * 8;
  158. /* Subtract the metadata bits. */
  159. block_mark_bit_offset -= MXS_NAND_METADATA_SIZE * 8;
  160. /*
  161. * Compute the chunk number (starting at zero) in which the block mark
  162. * appears.
  163. */
  164. block_mark_chunk_number =
  165. block_mark_bit_offset / chunk_total_size_in_bits;
  166. /*
  167. * Compute the bit offset of the block mark within its chunk, and
  168. * validate it.
  169. */
  170. block_mark_chunk_bit_offset = block_mark_bit_offset -
  171. (block_mark_chunk_number * chunk_total_size_in_bits);
  172. if (block_mark_chunk_bit_offset > chunk_data_size_in_bits)
  173. return 1;
  174. /*
  175. * Now that we know the chunk number in which the block mark appears,
  176. * we can subtract all the ECC bits that appear before it.
  177. */
  178. block_mark_bit_offset -=
  179. block_mark_chunk_number * chunk_ecc_size_in_bits;
  180. return block_mark_bit_offset;
  181. }
  182. static uint32_t mxs_nand_mark_byte_offset(struct mtd_info *mtd)
  183. {
  184. uint32_t ecc_strength;
  185. ecc_strength = mxs_nand_get_ecc_strength(mtd->writesize, mtd->oobsize);
  186. return mxs_nand_get_mark_offset(mtd->writesize, ecc_strength) >> 3;
  187. }
  188. static uint32_t mxs_nand_mark_bit_offset(struct mtd_info *mtd)
  189. {
  190. uint32_t ecc_strength;
  191. ecc_strength = mxs_nand_get_ecc_strength(mtd->writesize, mtd->oobsize);
  192. return mxs_nand_get_mark_offset(mtd->writesize, ecc_strength) & 0x7;
  193. }
  194. /*
  195. * Wait for BCH complete IRQ and clear the IRQ
  196. */
  197. static int mxs_nand_wait_for_bch_complete(void)
  198. {
  199. struct mxs_bch_regs *bch_regs = (struct mxs_bch_regs *)MXS_BCH_BASE;
  200. int timeout = MXS_NAND_BCH_TIMEOUT;
  201. int ret;
  202. ret = mxs_wait_mask_set(&bch_regs->hw_bch_ctrl_reg,
  203. BCH_CTRL_COMPLETE_IRQ, timeout);
  204. writel(BCH_CTRL_COMPLETE_IRQ, &bch_regs->hw_bch_ctrl_clr);
  205. return ret;
  206. }
  207. /*
  208. * This is the function that we install in the cmd_ctrl function pointer of the
  209. * owning struct nand_chip. The only functions in the reference implementation
  210. * that use these functions pointers are cmdfunc and select_chip.
  211. *
  212. * In this driver, we implement our own select_chip, so this function will only
  213. * be called by the reference implementation's cmdfunc. For this reason, we can
  214. * ignore the chip enable bit and concentrate only on sending bytes to the NAND
  215. * Flash.
  216. */
  217. static void mxs_nand_cmd_ctrl(struct mtd_info *mtd, int data, unsigned int ctrl)
  218. {
  219. struct nand_chip *nand = mtd_to_nand(mtd);
  220. struct mxs_nand_info *nand_info = nand_get_controller_data(nand);
  221. struct mxs_dma_desc *d;
  222. uint32_t channel = MXS_DMA_CHANNEL_AHB_APBH_GPMI0 + nand_info->cur_chip;
  223. int ret;
  224. /*
  225. * If this condition is true, something is _VERY_ wrong in MTD
  226. * subsystem!
  227. */
  228. if (nand_info->cmd_queue_len == MXS_NAND_COMMAND_BUFFER_SIZE) {
  229. printf("MXS NAND: Command queue too long\n");
  230. return;
  231. }
  232. /*
  233. * Every operation begins with a command byte and a series of zero or
  234. * more address bytes. These are distinguished by either the Address
  235. * Latch Enable (ALE) or Command Latch Enable (CLE) signals being
  236. * asserted. When MTD is ready to execute the command, it will
  237. * deasert both latch enables.
  238. *
  239. * Rather than run a separate DMA operation for every single byte, we
  240. * queue them up and run a single DMA operation for the entire series
  241. * of command and data bytes.
  242. */
  243. if (ctrl & (NAND_ALE | NAND_CLE)) {
  244. if (data != NAND_CMD_NONE)
  245. nand_info->cmd_buf[nand_info->cmd_queue_len++] = data;
  246. return;
  247. }
  248. /*
  249. * If control arrives here, MTD has deasserted both the ALE and CLE,
  250. * which means it's ready to run an operation. Check if we have any
  251. * bytes to send.
  252. */
  253. if (nand_info->cmd_queue_len == 0)
  254. return;
  255. /* Compile the DMA descriptor -- a descriptor that sends command. */
  256. d = mxs_nand_get_dma_desc(nand_info);
  257. d->cmd.data =
  258. MXS_DMA_DESC_COMMAND_DMA_READ | MXS_DMA_DESC_IRQ |
  259. MXS_DMA_DESC_CHAIN | MXS_DMA_DESC_DEC_SEM |
  260. MXS_DMA_DESC_WAIT4END | (3 << MXS_DMA_DESC_PIO_WORDS_OFFSET) |
  261. (nand_info->cmd_queue_len << MXS_DMA_DESC_BYTES_OFFSET);
  262. d->cmd.address = (dma_addr_t)nand_info->cmd_buf;
  263. d->cmd.pio_words[0] =
  264. GPMI_CTRL0_COMMAND_MODE_WRITE |
  265. GPMI_CTRL0_WORD_LENGTH |
  266. (nand_info->cur_chip << GPMI_CTRL0_CS_OFFSET) |
  267. GPMI_CTRL0_ADDRESS_NAND_CLE |
  268. GPMI_CTRL0_ADDRESS_INCREMENT |
  269. nand_info->cmd_queue_len;
  270. mxs_dma_desc_append(channel, d);
  271. /* Flush caches */
  272. mxs_nand_flush_cmd_buf(nand_info);
  273. /* Execute the DMA chain. */
  274. ret = mxs_dma_go(channel);
  275. if (ret)
  276. printf("MXS NAND: Error sending command\n");
  277. mxs_nand_return_dma_descs(nand_info);
  278. /* Reset the command queue. */
  279. nand_info->cmd_queue_len = 0;
  280. }
  281. /*
  282. * Test if the NAND flash is ready.
  283. */
  284. static int mxs_nand_device_ready(struct mtd_info *mtd)
  285. {
  286. struct nand_chip *chip = mtd_to_nand(mtd);
  287. struct mxs_nand_info *nand_info = nand_get_controller_data(chip);
  288. struct mxs_gpmi_regs *gpmi_regs =
  289. (struct mxs_gpmi_regs *)MXS_GPMI_BASE;
  290. uint32_t tmp;
  291. tmp = readl(&gpmi_regs->hw_gpmi_stat);
  292. tmp >>= (GPMI_STAT_READY_BUSY_OFFSET + nand_info->cur_chip);
  293. return tmp & 1;
  294. }
  295. /*
  296. * Select the NAND chip.
  297. */
  298. static void mxs_nand_select_chip(struct mtd_info *mtd, int chip)
  299. {
  300. struct nand_chip *nand = mtd_to_nand(mtd);
  301. struct mxs_nand_info *nand_info = nand_get_controller_data(nand);
  302. nand_info->cur_chip = chip;
  303. }
  304. /*
  305. * Handle block mark swapping.
  306. *
  307. * Note that, when this function is called, it doesn't know whether it's
  308. * swapping the block mark, or swapping it *back* -- but it doesn't matter
  309. * because the the operation is the same.
  310. */
  311. static void mxs_nand_swap_block_mark(struct mtd_info *mtd,
  312. uint8_t *data_buf, uint8_t *oob_buf)
  313. {
  314. uint32_t bit_offset;
  315. uint32_t buf_offset;
  316. uint32_t src;
  317. uint32_t dst;
  318. bit_offset = mxs_nand_mark_bit_offset(mtd);
  319. buf_offset = mxs_nand_mark_byte_offset(mtd);
  320. /*
  321. * Get the byte from the data area that overlays the block mark. Since
  322. * the ECC engine applies its own view to the bits in the page, the
  323. * physical block mark won't (in general) appear on a byte boundary in
  324. * the data.
  325. */
  326. src = data_buf[buf_offset] >> bit_offset;
  327. src |= data_buf[buf_offset + 1] << (8 - bit_offset);
  328. dst = oob_buf[0];
  329. oob_buf[0] = src;
  330. data_buf[buf_offset] &= ~(0xff << bit_offset);
  331. data_buf[buf_offset + 1] &= 0xff << bit_offset;
  332. data_buf[buf_offset] |= dst << bit_offset;
  333. data_buf[buf_offset + 1] |= dst >> (8 - bit_offset);
  334. }
  335. /*
  336. * Read data from NAND.
  337. */
  338. static void mxs_nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int length)
  339. {
  340. struct nand_chip *nand = mtd_to_nand(mtd);
  341. struct mxs_nand_info *nand_info = nand_get_controller_data(nand);
  342. struct mxs_dma_desc *d;
  343. uint32_t channel = MXS_DMA_CHANNEL_AHB_APBH_GPMI0 + nand_info->cur_chip;
  344. int ret;
  345. if (length > NAND_MAX_PAGESIZE) {
  346. printf("MXS NAND: DMA buffer too big\n");
  347. return;
  348. }
  349. if (!buf) {
  350. printf("MXS NAND: DMA buffer is NULL\n");
  351. return;
  352. }
  353. /* Compile the DMA descriptor - a descriptor that reads data. */
  354. d = mxs_nand_get_dma_desc(nand_info);
  355. d->cmd.data =
  356. MXS_DMA_DESC_COMMAND_DMA_WRITE | MXS_DMA_DESC_IRQ |
  357. MXS_DMA_DESC_DEC_SEM | MXS_DMA_DESC_WAIT4END |
  358. (1 << MXS_DMA_DESC_PIO_WORDS_OFFSET) |
  359. (length << MXS_DMA_DESC_BYTES_OFFSET);
  360. d->cmd.address = (dma_addr_t)nand_info->data_buf;
  361. d->cmd.pio_words[0] =
  362. GPMI_CTRL0_COMMAND_MODE_READ |
  363. GPMI_CTRL0_WORD_LENGTH |
  364. (nand_info->cur_chip << GPMI_CTRL0_CS_OFFSET) |
  365. GPMI_CTRL0_ADDRESS_NAND_DATA |
  366. length;
  367. mxs_dma_desc_append(channel, d);
  368. /*
  369. * A DMA descriptor that waits for the command to end and the chip to
  370. * become ready.
  371. *
  372. * I think we actually should *not* be waiting for the chip to become
  373. * ready because, after all, we don't care. I think the original code
  374. * did that and no one has re-thought it yet.
  375. */
  376. d = mxs_nand_get_dma_desc(nand_info);
  377. d->cmd.data =
  378. MXS_DMA_DESC_COMMAND_NO_DMAXFER | MXS_DMA_DESC_IRQ |
  379. MXS_DMA_DESC_NAND_WAIT_4_READY | MXS_DMA_DESC_DEC_SEM |
  380. MXS_DMA_DESC_WAIT4END | (1 << MXS_DMA_DESC_PIO_WORDS_OFFSET);
  381. d->cmd.address = 0;
  382. d->cmd.pio_words[0] =
  383. GPMI_CTRL0_COMMAND_MODE_WAIT_FOR_READY |
  384. GPMI_CTRL0_WORD_LENGTH |
  385. (nand_info->cur_chip << GPMI_CTRL0_CS_OFFSET) |
  386. GPMI_CTRL0_ADDRESS_NAND_DATA;
  387. mxs_dma_desc_append(channel, d);
  388. /* Invalidate caches */
  389. mxs_nand_inval_data_buf(nand_info);
  390. /* Execute the DMA chain. */
  391. ret = mxs_dma_go(channel);
  392. if (ret) {
  393. printf("MXS NAND: DMA read error\n");
  394. goto rtn;
  395. }
  396. /* Invalidate caches */
  397. mxs_nand_inval_data_buf(nand_info);
  398. memcpy(buf, nand_info->data_buf, length);
  399. rtn:
  400. mxs_nand_return_dma_descs(nand_info);
  401. }
  402. /*
  403. * Write data to NAND.
  404. */
  405. static void mxs_nand_write_buf(struct mtd_info *mtd, const uint8_t *buf,
  406. int length)
  407. {
  408. struct nand_chip *nand = mtd_to_nand(mtd);
  409. struct mxs_nand_info *nand_info = nand_get_controller_data(nand);
  410. struct mxs_dma_desc *d;
  411. uint32_t channel = MXS_DMA_CHANNEL_AHB_APBH_GPMI0 + nand_info->cur_chip;
  412. int ret;
  413. if (length > NAND_MAX_PAGESIZE) {
  414. printf("MXS NAND: DMA buffer too big\n");
  415. return;
  416. }
  417. if (!buf) {
  418. printf("MXS NAND: DMA buffer is NULL\n");
  419. return;
  420. }
  421. memcpy(nand_info->data_buf, buf, length);
  422. /* Compile the DMA descriptor - a descriptor that writes data. */
  423. d = mxs_nand_get_dma_desc(nand_info);
  424. d->cmd.data =
  425. MXS_DMA_DESC_COMMAND_DMA_READ | MXS_DMA_DESC_IRQ |
  426. MXS_DMA_DESC_DEC_SEM | MXS_DMA_DESC_WAIT4END |
  427. (1 << MXS_DMA_DESC_PIO_WORDS_OFFSET) |
  428. (length << MXS_DMA_DESC_BYTES_OFFSET);
  429. d->cmd.address = (dma_addr_t)nand_info->data_buf;
  430. d->cmd.pio_words[0] =
  431. GPMI_CTRL0_COMMAND_MODE_WRITE |
  432. GPMI_CTRL0_WORD_LENGTH |
  433. (nand_info->cur_chip << GPMI_CTRL0_CS_OFFSET) |
  434. GPMI_CTRL0_ADDRESS_NAND_DATA |
  435. length;
  436. mxs_dma_desc_append(channel, d);
  437. /* Flush caches */
  438. mxs_nand_flush_data_buf(nand_info);
  439. /* Execute the DMA chain. */
  440. ret = mxs_dma_go(channel);
  441. if (ret)
  442. printf("MXS NAND: DMA write error\n");
  443. mxs_nand_return_dma_descs(nand_info);
  444. }
  445. /*
  446. * Read a single byte from NAND.
  447. */
  448. static uint8_t mxs_nand_read_byte(struct mtd_info *mtd)
  449. {
  450. uint8_t buf;
  451. mxs_nand_read_buf(mtd, &buf, 1);
  452. return buf;
  453. }
  454. /*
  455. * Read a page from NAND.
  456. */
  457. static int mxs_nand_ecc_read_page(struct mtd_info *mtd, struct nand_chip *nand,
  458. uint8_t *buf, int oob_required,
  459. int page)
  460. {
  461. struct mxs_nand_info *nand_info = nand_get_controller_data(nand);
  462. struct mxs_dma_desc *d;
  463. uint32_t channel = MXS_DMA_CHANNEL_AHB_APBH_GPMI0 + nand_info->cur_chip;
  464. uint32_t corrected = 0, failed = 0;
  465. uint8_t *status;
  466. int i, ret;
  467. /* Compile the DMA descriptor - wait for ready. */
  468. d = mxs_nand_get_dma_desc(nand_info);
  469. d->cmd.data =
  470. MXS_DMA_DESC_COMMAND_NO_DMAXFER | MXS_DMA_DESC_CHAIN |
  471. MXS_DMA_DESC_NAND_WAIT_4_READY | MXS_DMA_DESC_WAIT4END |
  472. (1 << MXS_DMA_DESC_PIO_WORDS_OFFSET);
  473. d->cmd.address = 0;
  474. d->cmd.pio_words[0] =
  475. GPMI_CTRL0_COMMAND_MODE_WAIT_FOR_READY |
  476. GPMI_CTRL0_WORD_LENGTH |
  477. (nand_info->cur_chip << GPMI_CTRL0_CS_OFFSET) |
  478. GPMI_CTRL0_ADDRESS_NAND_DATA;
  479. mxs_dma_desc_append(channel, d);
  480. /* Compile the DMA descriptor - enable the BCH block and read. */
  481. d = mxs_nand_get_dma_desc(nand_info);
  482. d->cmd.data =
  483. MXS_DMA_DESC_COMMAND_NO_DMAXFER | MXS_DMA_DESC_CHAIN |
  484. MXS_DMA_DESC_WAIT4END | (6 << MXS_DMA_DESC_PIO_WORDS_OFFSET);
  485. d->cmd.address = 0;
  486. d->cmd.pio_words[0] =
  487. GPMI_CTRL0_COMMAND_MODE_READ |
  488. GPMI_CTRL0_WORD_LENGTH |
  489. (nand_info->cur_chip << GPMI_CTRL0_CS_OFFSET) |
  490. GPMI_CTRL0_ADDRESS_NAND_DATA |
  491. (mtd->writesize + mtd->oobsize);
  492. d->cmd.pio_words[1] = 0;
  493. d->cmd.pio_words[2] =
  494. GPMI_ECCCTRL_ENABLE_ECC |
  495. GPMI_ECCCTRL_ECC_CMD_DECODE |
  496. GPMI_ECCCTRL_BUFFER_MASK_BCH_PAGE;
  497. d->cmd.pio_words[3] = mtd->writesize + mtd->oobsize;
  498. d->cmd.pio_words[4] = (dma_addr_t)nand_info->data_buf;
  499. d->cmd.pio_words[5] = (dma_addr_t)nand_info->oob_buf;
  500. mxs_dma_desc_append(channel, d);
  501. /* Compile the DMA descriptor - disable the BCH block. */
  502. d = mxs_nand_get_dma_desc(nand_info);
  503. d->cmd.data =
  504. MXS_DMA_DESC_COMMAND_NO_DMAXFER | MXS_DMA_DESC_CHAIN |
  505. MXS_DMA_DESC_NAND_WAIT_4_READY | MXS_DMA_DESC_WAIT4END |
  506. (3 << MXS_DMA_DESC_PIO_WORDS_OFFSET);
  507. d->cmd.address = 0;
  508. d->cmd.pio_words[0] =
  509. GPMI_CTRL0_COMMAND_MODE_WAIT_FOR_READY |
  510. GPMI_CTRL0_WORD_LENGTH |
  511. (nand_info->cur_chip << GPMI_CTRL0_CS_OFFSET) |
  512. GPMI_CTRL0_ADDRESS_NAND_DATA |
  513. (mtd->writesize + mtd->oobsize);
  514. d->cmd.pio_words[1] = 0;
  515. d->cmd.pio_words[2] = 0;
  516. mxs_dma_desc_append(channel, d);
  517. /* Compile the DMA descriptor - deassert the NAND lock and interrupt. */
  518. d = mxs_nand_get_dma_desc(nand_info);
  519. d->cmd.data =
  520. MXS_DMA_DESC_COMMAND_NO_DMAXFER | MXS_DMA_DESC_IRQ |
  521. MXS_DMA_DESC_DEC_SEM;
  522. d->cmd.address = 0;
  523. mxs_dma_desc_append(channel, d);
  524. /* Invalidate caches */
  525. mxs_nand_inval_data_buf(nand_info);
  526. /* Execute the DMA chain. */
  527. ret = mxs_dma_go(channel);
  528. if (ret) {
  529. printf("MXS NAND: DMA read error\n");
  530. goto rtn;
  531. }
  532. ret = mxs_nand_wait_for_bch_complete();
  533. if (ret) {
  534. printf("MXS NAND: BCH read timeout\n");
  535. goto rtn;
  536. }
  537. /* Invalidate caches */
  538. mxs_nand_inval_data_buf(nand_info);
  539. /* Read DMA completed, now do the mark swapping. */
  540. mxs_nand_swap_block_mark(mtd, nand_info->data_buf, nand_info->oob_buf);
  541. /* Loop over status bytes, accumulating ECC status. */
  542. status = nand_info->oob_buf + mxs_nand_aux_status_offset();
  543. for (i = 0; i < mxs_nand_ecc_chunk_cnt(mtd->writesize); i++) {
  544. if (status[i] == 0x00)
  545. continue;
  546. if (status[i] == 0xff)
  547. continue;
  548. if (status[i] == 0xfe) {
  549. failed++;
  550. continue;
  551. }
  552. corrected += status[i];
  553. }
  554. /* Propagate ECC status to the owning MTD. */
  555. mtd->ecc_stats.failed += failed;
  556. mtd->ecc_stats.corrected += corrected;
  557. /*
  558. * It's time to deliver the OOB bytes. See mxs_nand_ecc_read_oob() for
  559. * details about our policy for delivering the OOB.
  560. *
  561. * We fill the caller's buffer with set bits, and then copy the block
  562. * mark to the caller's buffer. Note that, if block mark swapping was
  563. * necessary, it has already been done, so we can rely on the first
  564. * byte of the auxiliary buffer to contain the block mark.
  565. */
  566. memset(nand->oob_poi, 0xff, mtd->oobsize);
  567. nand->oob_poi[0] = nand_info->oob_buf[0];
  568. memcpy(buf, nand_info->data_buf, mtd->writesize);
  569. rtn:
  570. mxs_nand_return_dma_descs(nand_info);
  571. return ret;
  572. }
  573. /*
  574. * Write a page to NAND.
  575. */
  576. static int mxs_nand_ecc_write_page(struct mtd_info *mtd,
  577. struct nand_chip *nand, const uint8_t *buf,
  578. int oob_required)
  579. {
  580. struct mxs_nand_info *nand_info = nand_get_controller_data(nand);
  581. struct mxs_dma_desc *d;
  582. uint32_t channel = MXS_DMA_CHANNEL_AHB_APBH_GPMI0 + nand_info->cur_chip;
  583. int ret;
  584. memcpy(nand_info->data_buf, buf, mtd->writesize);
  585. memcpy(nand_info->oob_buf, nand->oob_poi, mtd->oobsize);
  586. /* Handle block mark swapping. */
  587. mxs_nand_swap_block_mark(mtd, nand_info->data_buf, nand_info->oob_buf);
  588. /* Compile the DMA descriptor - write data. */
  589. d = mxs_nand_get_dma_desc(nand_info);
  590. d->cmd.data =
  591. MXS_DMA_DESC_COMMAND_NO_DMAXFER | MXS_DMA_DESC_IRQ |
  592. MXS_DMA_DESC_DEC_SEM | MXS_DMA_DESC_WAIT4END |
  593. (6 << MXS_DMA_DESC_PIO_WORDS_OFFSET);
  594. d->cmd.address = 0;
  595. d->cmd.pio_words[0] =
  596. GPMI_CTRL0_COMMAND_MODE_WRITE |
  597. GPMI_CTRL0_WORD_LENGTH |
  598. (nand_info->cur_chip << GPMI_CTRL0_CS_OFFSET) |
  599. GPMI_CTRL0_ADDRESS_NAND_DATA;
  600. d->cmd.pio_words[1] = 0;
  601. d->cmd.pio_words[2] =
  602. GPMI_ECCCTRL_ENABLE_ECC |
  603. GPMI_ECCCTRL_ECC_CMD_ENCODE |
  604. GPMI_ECCCTRL_BUFFER_MASK_BCH_PAGE;
  605. d->cmd.pio_words[3] = (mtd->writesize + mtd->oobsize);
  606. d->cmd.pio_words[4] = (dma_addr_t)nand_info->data_buf;
  607. d->cmd.pio_words[5] = (dma_addr_t)nand_info->oob_buf;
  608. mxs_dma_desc_append(channel, d);
  609. /* Flush caches */
  610. mxs_nand_flush_data_buf(nand_info);
  611. /* Execute the DMA chain. */
  612. ret = mxs_dma_go(channel);
  613. if (ret) {
  614. printf("MXS NAND: DMA write error\n");
  615. goto rtn;
  616. }
  617. ret = mxs_nand_wait_for_bch_complete();
  618. if (ret) {
  619. printf("MXS NAND: BCH write timeout\n");
  620. goto rtn;
  621. }
  622. rtn:
  623. mxs_nand_return_dma_descs(nand_info);
  624. return 0;
  625. }
  626. /*
  627. * Read OOB from NAND.
  628. *
  629. * This function is a veneer that replaces the function originally installed by
  630. * the NAND Flash MTD code.
  631. */
  632. static int mxs_nand_hook_read_oob(struct mtd_info *mtd, loff_t from,
  633. struct mtd_oob_ops *ops)
  634. {
  635. struct nand_chip *chip = mtd_to_nand(mtd);
  636. struct mxs_nand_info *nand_info = nand_get_controller_data(chip);
  637. int ret;
  638. if (ops->mode == MTD_OPS_RAW)
  639. nand_info->raw_oob_mode = 1;
  640. else
  641. nand_info->raw_oob_mode = 0;
  642. ret = nand_info->hooked_read_oob(mtd, from, ops);
  643. nand_info->raw_oob_mode = 0;
  644. return ret;
  645. }
  646. /*
  647. * Write OOB to NAND.
  648. *
  649. * This function is a veneer that replaces the function originally installed by
  650. * the NAND Flash MTD code.
  651. */
  652. static int mxs_nand_hook_write_oob(struct mtd_info *mtd, loff_t to,
  653. struct mtd_oob_ops *ops)
  654. {
  655. struct nand_chip *chip = mtd_to_nand(mtd);
  656. struct mxs_nand_info *nand_info = nand_get_controller_data(chip);
  657. int ret;
  658. if (ops->mode == MTD_OPS_RAW)
  659. nand_info->raw_oob_mode = 1;
  660. else
  661. nand_info->raw_oob_mode = 0;
  662. ret = nand_info->hooked_write_oob(mtd, to, ops);
  663. nand_info->raw_oob_mode = 0;
  664. return ret;
  665. }
  666. /*
  667. * Mark a block bad in NAND.
  668. *
  669. * This function is a veneer that replaces the function originally installed by
  670. * the NAND Flash MTD code.
  671. */
  672. static int mxs_nand_hook_block_markbad(struct mtd_info *mtd, loff_t ofs)
  673. {
  674. struct nand_chip *chip = mtd_to_nand(mtd);
  675. struct mxs_nand_info *nand_info = nand_get_controller_data(chip);
  676. int ret;
  677. nand_info->marking_block_bad = 1;
  678. ret = nand_info->hooked_block_markbad(mtd, ofs);
  679. nand_info->marking_block_bad = 0;
  680. return ret;
  681. }
  682. /*
  683. * There are several places in this driver where we have to handle the OOB and
  684. * block marks. This is the function where things are the most complicated, so
  685. * this is where we try to explain it all. All the other places refer back to
  686. * here.
  687. *
  688. * These are the rules, in order of decreasing importance:
  689. *
  690. * 1) Nothing the caller does can be allowed to imperil the block mark, so all
  691. * write operations take measures to protect it.
  692. *
  693. * 2) In read operations, the first byte of the OOB we return must reflect the
  694. * true state of the block mark, no matter where that block mark appears in
  695. * the physical page.
  696. *
  697. * 3) ECC-based read operations return an OOB full of set bits (since we never
  698. * allow ECC-based writes to the OOB, it doesn't matter what ECC-based reads
  699. * return).
  700. *
  701. * 4) "Raw" read operations return a direct view of the physical bytes in the
  702. * page, using the conventional definition of which bytes are data and which
  703. * are OOB. This gives the caller a way to see the actual, physical bytes
  704. * in the page, without the distortions applied by our ECC engine.
  705. *
  706. * What we do for this specific read operation depends on whether we're doing
  707. * "raw" read, or an ECC-based read.
  708. *
  709. * It turns out that knowing whether we want an "ECC-based" or "raw" read is not
  710. * easy. When reading a page, for example, the NAND Flash MTD code calls our
  711. * ecc.read_page or ecc.read_page_raw function. Thus, the fact that MTD wants an
  712. * ECC-based or raw view of the page is implicit in which function it calls
  713. * (there is a similar pair of ECC-based/raw functions for writing).
  714. *
  715. * Since MTD assumes the OOB is not covered by ECC, there is no pair of
  716. * ECC-based/raw functions for reading or or writing the OOB. The fact that the
  717. * caller wants an ECC-based or raw view of the page is not propagated down to
  718. * this driver.
  719. *
  720. * Since our OOB *is* covered by ECC, we need this information. So, we hook the
  721. * ecc.read_oob and ecc.write_oob function pointers in the owning
  722. * struct mtd_info with our own functions. These hook functions set the
  723. * raw_oob_mode field so that, when control finally arrives here, we'll know
  724. * what to do.
  725. */
  726. static int mxs_nand_ecc_read_oob(struct mtd_info *mtd, struct nand_chip *nand,
  727. int page)
  728. {
  729. struct mxs_nand_info *nand_info = nand_get_controller_data(nand);
  730. /*
  731. * First, fill in the OOB buffer. If we're doing a raw read, we need to
  732. * get the bytes from the physical page. If we're not doing a raw read,
  733. * we need to fill the buffer with set bits.
  734. */
  735. if (nand_info->raw_oob_mode) {
  736. /*
  737. * If control arrives here, we're doing a "raw" read. Send the
  738. * command to read the conventional OOB and read it.
  739. */
  740. nand->cmdfunc(mtd, NAND_CMD_READ0, mtd->writesize, page);
  741. nand->read_buf(mtd, nand->oob_poi, mtd->oobsize);
  742. } else {
  743. /*
  744. * If control arrives here, we're not doing a "raw" read. Fill
  745. * the OOB buffer with set bits and correct the block mark.
  746. */
  747. memset(nand->oob_poi, 0xff, mtd->oobsize);
  748. nand->cmdfunc(mtd, NAND_CMD_READ0, mtd->writesize, page);
  749. mxs_nand_read_buf(mtd, nand->oob_poi, 1);
  750. }
  751. return 0;
  752. }
  753. /*
  754. * Write OOB data to NAND.
  755. */
  756. static int mxs_nand_ecc_write_oob(struct mtd_info *mtd, struct nand_chip *nand,
  757. int page)
  758. {
  759. struct mxs_nand_info *nand_info = nand_get_controller_data(nand);
  760. uint8_t block_mark = 0;
  761. /*
  762. * There are fundamental incompatibilities between the i.MX GPMI NFC and
  763. * the NAND Flash MTD model that make it essentially impossible to write
  764. * the out-of-band bytes.
  765. *
  766. * We permit *ONE* exception. If the *intent* of writing the OOB is to
  767. * mark a block bad, we can do that.
  768. */
  769. if (!nand_info->marking_block_bad) {
  770. printf("NXS NAND: Writing OOB isn't supported\n");
  771. return -EIO;
  772. }
  773. /* Write the block mark. */
  774. nand->cmdfunc(mtd, NAND_CMD_SEQIN, mtd->writesize, page);
  775. nand->write_buf(mtd, &block_mark, 1);
  776. nand->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
  777. /* Check if it worked. */
  778. if (nand->waitfunc(mtd, nand) & NAND_STATUS_FAIL)
  779. return -EIO;
  780. return 0;
  781. }
  782. /*
  783. * Claims all blocks are good.
  784. *
  785. * In principle, this function is *only* called when the NAND Flash MTD system
  786. * isn't allowed to keep an in-memory bad block table, so it is forced to ask
  787. * the driver for bad block information.
  788. *
  789. * In fact, we permit the NAND Flash MTD system to have an in-memory BBT, so
  790. * this function is *only* called when we take it away.
  791. *
  792. * Thus, this function is only called when we want *all* blocks to look good,
  793. * so it *always* return success.
  794. */
  795. static int mxs_nand_block_bad(struct mtd_info *mtd, loff_t ofs, int getchip)
  796. {
  797. return 0;
  798. }
  799. /*
  800. * Nominally, the purpose of this function is to look for or create the bad
  801. * block table. In fact, since the we call this function at the very end of
  802. * the initialization process started by nand_scan(), and we doesn't have a
  803. * more formal mechanism, we "hook" this function to continue init process.
  804. *
  805. * At this point, the physical NAND Flash chips have been identified and
  806. * counted, so we know the physical geometry. This enables us to make some
  807. * important configuration decisions.
  808. *
  809. * The return value of this function propogates directly back to this driver's
  810. * call to nand_scan(). Anything other than zero will cause this driver to
  811. * tear everything down and declare failure.
  812. */
  813. static int mxs_nand_scan_bbt(struct mtd_info *mtd)
  814. {
  815. struct nand_chip *nand = mtd_to_nand(mtd);
  816. struct mxs_nand_info *nand_info = nand_get_controller_data(nand);
  817. struct mxs_bch_regs *bch_regs = (struct mxs_bch_regs *)MXS_BCH_BASE;
  818. uint32_t tmp;
  819. if (mtd->oobsize > MXS_NAND_CHUNK_DATA_CHUNK_SIZE) {
  820. galois_field = 14;
  821. chunk_data_size = MXS_NAND_CHUNK_DATA_CHUNK_SIZE * 2;
  822. }
  823. if (mtd->oobsize > chunk_data_size) {
  824. printf("Not support the NAND chips whose oob size is larger then %d bytes!\n", chunk_data_size);
  825. return -EINVAL;
  826. }
  827. /* Configure BCH and set NFC geometry */
  828. mxs_reset_block(&bch_regs->hw_bch_ctrl_reg);
  829. /* Configure layout 0 */
  830. tmp = (mxs_nand_ecc_chunk_cnt(mtd->writesize) - 1)
  831. << BCH_FLASHLAYOUT0_NBLOCKS_OFFSET;
  832. tmp |= MXS_NAND_METADATA_SIZE << BCH_FLASHLAYOUT0_META_SIZE_OFFSET;
  833. tmp |= (mxs_nand_get_ecc_strength(mtd->writesize, mtd->oobsize) >> 1)
  834. << BCH_FLASHLAYOUT0_ECC0_OFFSET;
  835. tmp |= chunk_data_size >> MXS_NAND_CHUNK_DATA_CHUNK_SIZE_SHIFT;
  836. tmp |= (14 == galois_field ? 1 : 0) <<
  837. BCH_FLASHLAYOUT0_GF13_0_GF14_1_OFFSET;
  838. writel(tmp, &bch_regs->hw_bch_flash0layout0);
  839. tmp = (mtd->writesize + mtd->oobsize)
  840. << BCH_FLASHLAYOUT1_PAGE_SIZE_OFFSET;
  841. tmp |= (mxs_nand_get_ecc_strength(mtd->writesize, mtd->oobsize) >> 1)
  842. << BCH_FLASHLAYOUT1_ECCN_OFFSET;
  843. tmp |= chunk_data_size >> MXS_NAND_CHUNK_DATA_CHUNK_SIZE_SHIFT;
  844. tmp |= (14 == galois_field ? 1 : 0) <<
  845. BCH_FLASHLAYOUT1_GF13_0_GF14_1_OFFSET;
  846. writel(tmp, &bch_regs->hw_bch_flash0layout1);
  847. /* Set *all* chip selects to use layout 0 */
  848. writel(0, &bch_regs->hw_bch_layoutselect);
  849. /* Enable BCH complete interrupt */
  850. writel(BCH_CTRL_COMPLETE_IRQ_EN, &bch_regs->hw_bch_ctrl_set);
  851. /* Hook some operations at the MTD level. */
  852. if (mtd->_read_oob != mxs_nand_hook_read_oob) {
  853. nand_info->hooked_read_oob = mtd->_read_oob;
  854. mtd->_read_oob = mxs_nand_hook_read_oob;
  855. }
  856. if (mtd->_write_oob != mxs_nand_hook_write_oob) {
  857. nand_info->hooked_write_oob = mtd->_write_oob;
  858. mtd->_write_oob = mxs_nand_hook_write_oob;
  859. }
  860. if (mtd->_block_markbad != mxs_nand_hook_block_markbad) {
  861. nand_info->hooked_block_markbad = mtd->_block_markbad;
  862. mtd->_block_markbad = mxs_nand_hook_block_markbad;
  863. }
  864. /* We use the reference implementation for bad block management. */
  865. return nand_default_bbt(mtd);
  866. }
  867. /*
  868. * Allocate DMA buffers
  869. */
  870. int mxs_nand_alloc_buffers(struct mxs_nand_info *nand_info)
  871. {
  872. uint8_t *buf;
  873. const int size = NAND_MAX_PAGESIZE + NAND_MAX_OOBSIZE;
  874. nand_info->data_buf_size = roundup(size, MXS_DMA_ALIGNMENT);
  875. /* DMA buffers */
  876. buf = memalign(MXS_DMA_ALIGNMENT, nand_info->data_buf_size);
  877. if (!buf) {
  878. printf("MXS NAND: Error allocating DMA buffers\n");
  879. return -ENOMEM;
  880. }
  881. memset(buf, 0, nand_info->data_buf_size);
  882. nand_info->data_buf = buf;
  883. nand_info->oob_buf = buf + NAND_MAX_PAGESIZE;
  884. /* Command buffers */
  885. nand_info->cmd_buf = memalign(MXS_DMA_ALIGNMENT,
  886. MXS_NAND_COMMAND_BUFFER_SIZE);
  887. if (!nand_info->cmd_buf) {
  888. free(buf);
  889. printf("MXS NAND: Error allocating command buffers\n");
  890. return -ENOMEM;
  891. }
  892. memset(nand_info->cmd_buf, 0, MXS_NAND_COMMAND_BUFFER_SIZE);
  893. nand_info->cmd_queue_len = 0;
  894. return 0;
  895. }
  896. /*
  897. * Initializes the NFC hardware.
  898. */
  899. int mxs_nand_init(struct mxs_nand_info *info)
  900. {
  901. struct mxs_gpmi_regs *gpmi_regs =
  902. (struct mxs_gpmi_regs *)MXS_GPMI_BASE;
  903. struct mxs_bch_regs *bch_regs =
  904. (struct mxs_bch_regs *)MXS_BCH_BASE;
  905. int i = 0, j, ret = 0;
  906. info->desc = malloc(sizeof(struct mxs_dma_desc *) *
  907. MXS_NAND_DMA_DESCRIPTOR_COUNT);
  908. if (!info->desc) {
  909. ret = -ENOMEM;
  910. goto err1;
  911. }
  912. /* Allocate the DMA descriptors. */
  913. for (i = 0; i < MXS_NAND_DMA_DESCRIPTOR_COUNT; i++) {
  914. info->desc[i] = mxs_dma_desc_alloc();
  915. if (!info->desc[i]) {
  916. ret = -ENOMEM;
  917. goto err2;
  918. }
  919. }
  920. /* Init the DMA controller. */
  921. for (j = MXS_DMA_CHANNEL_AHB_APBH_GPMI0;
  922. j <= MXS_DMA_CHANNEL_AHB_APBH_GPMI7; j++) {
  923. ret = mxs_dma_init_channel(j);
  924. if (ret)
  925. goto err3;
  926. }
  927. /* Reset the GPMI block. */
  928. mxs_reset_block(&gpmi_regs->hw_gpmi_ctrl0_reg);
  929. mxs_reset_block(&bch_regs->hw_bch_ctrl_reg);
  930. /*
  931. * Choose NAND mode, set IRQ polarity, disable write protection and
  932. * select BCH ECC.
  933. */
  934. clrsetbits_le32(&gpmi_regs->hw_gpmi_ctrl1,
  935. GPMI_CTRL1_GPMI_MODE,
  936. GPMI_CTRL1_ATA_IRQRDY_POLARITY | GPMI_CTRL1_DEV_RESET |
  937. GPMI_CTRL1_BCH_MODE);
  938. return 0;
  939. err3:
  940. for (--j; j >= MXS_DMA_CHANNEL_AHB_APBH_GPMI0; j--)
  941. mxs_dma_release(j);
  942. err2:
  943. for (--i; i >= 0; i--)
  944. mxs_dma_desc_free(info->desc[i]);
  945. free(info->desc);
  946. err1:
  947. if (ret == -ENOMEM)
  948. printf("MXS NAND: Unable to allocate DMA descriptors\n");
  949. return ret;
  950. }
  951. /*!
  952. * This function is called during the driver binding process.
  953. *
  954. * @param pdev the device structure used to store device specific
  955. * information that is used by the suspend, resume and
  956. * remove functions
  957. *
  958. * @return The function always returns 0.
  959. */
  960. int board_nand_init(struct nand_chip *nand)
  961. {
  962. struct mxs_nand_info *nand_info;
  963. int err;
  964. nand_info = malloc(sizeof(struct mxs_nand_info));
  965. if (!nand_info) {
  966. printf("MXS NAND: Failed to allocate private data\n");
  967. return -ENOMEM;
  968. }
  969. memset(nand_info, 0, sizeof(struct mxs_nand_info));
  970. err = mxs_nand_alloc_buffers(nand_info);
  971. if (err)
  972. goto err1;
  973. err = mxs_nand_init(nand_info);
  974. if (err)
  975. goto err2;
  976. memset(&fake_ecc_layout, 0, sizeof(fake_ecc_layout));
  977. nand_set_controller_data(nand, nand_info);
  978. nand->options |= NAND_NO_SUBPAGE_WRITE;
  979. nand->cmd_ctrl = mxs_nand_cmd_ctrl;
  980. nand->dev_ready = mxs_nand_device_ready;
  981. nand->select_chip = mxs_nand_select_chip;
  982. nand->block_bad = mxs_nand_block_bad;
  983. nand->scan_bbt = mxs_nand_scan_bbt;
  984. nand->read_byte = mxs_nand_read_byte;
  985. nand->read_buf = mxs_nand_read_buf;
  986. nand->write_buf = mxs_nand_write_buf;
  987. nand->ecc.read_page = mxs_nand_ecc_read_page;
  988. nand->ecc.write_page = mxs_nand_ecc_write_page;
  989. nand->ecc.read_oob = mxs_nand_ecc_read_oob;
  990. nand->ecc.write_oob = mxs_nand_ecc_write_oob;
  991. nand->ecc.layout = &fake_ecc_layout;
  992. nand->ecc.mode = NAND_ECC_HW;
  993. nand->ecc.bytes = 9;
  994. nand->ecc.size = 512;
  995. nand->ecc.strength = 8;
  996. return 0;
  997. err2:
  998. free(nand_info->data_buf);
  999. free(nand_info->cmd_buf);
  1000. err1:
  1001. free(nand_info);
  1002. return err;
  1003. }