mxc_nand.c 33 KB

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  1. /*
  2. * Copyright 2004-2007 Freescale Semiconductor, Inc.
  3. * Copyright 2008 Sascha Hauer, kernel@pengutronix.de
  4. * Copyright 2009 Ilya Yanok, <yanok@emcraft.com>
  5. *
  6. * SPDX-License-Identifier: GPL-2.0+
  7. */
  8. #include <common.h>
  9. #include <nand.h>
  10. #include <linux/err.h>
  11. #include <asm/io.h>
  12. #if defined(CONFIG_MX25) || defined(CONFIG_MX27) || defined(CONFIG_MX35) || \
  13. defined(CONFIG_MX51) || defined(CONFIG_MX53)
  14. #include <asm/arch/imx-regs.h>
  15. #endif
  16. #include "mxc_nand.h"
  17. #define DRIVER_NAME "mxc_nand"
  18. struct mxc_nand_host {
  19. struct mtd_info mtd;
  20. struct nand_chip *nand;
  21. struct mxc_nand_regs __iomem *regs;
  22. #ifdef MXC_NFC_V3_2
  23. struct mxc_nand_ip_regs __iomem *ip_regs;
  24. #endif
  25. int spare_only;
  26. int status_request;
  27. int pagesize_2k;
  28. int clk_act;
  29. uint16_t col_addr;
  30. unsigned int page_addr;
  31. };
  32. static struct mxc_nand_host mxc_host;
  33. static struct mxc_nand_host *host = &mxc_host;
  34. /* Define delays in microsec for NAND device operations */
  35. #define TROP_US_DELAY 2000
  36. /* Macros to get byte and bit positions of ECC */
  37. #define COLPOS(x) ((x) >> 3)
  38. #define BITPOS(x) ((x) & 0xf)
  39. /* Define single bit Error positions in Main & Spare area */
  40. #define MAIN_SINGLEBIT_ERROR 0x4
  41. #define SPARE_SINGLEBIT_ERROR 0x1
  42. /* OOB placement block for use with hardware ecc generation */
  43. #if defined(MXC_NFC_V1)
  44. #ifndef CONFIG_SYS_NAND_LARGEPAGE
  45. static struct nand_ecclayout nand_hw_eccoob = {
  46. .eccbytes = 5,
  47. .eccpos = {6, 7, 8, 9, 10},
  48. .oobfree = { {0, 5}, {11, 5}, }
  49. };
  50. #else
  51. static struct nand_ecclayout nand_hw_eccoob2k = {
  52. .eccbytes = 20,
  53. .eccpos = {
  54. 6, 7, 8, 9, 10,
  55. 22, 23, 24, 25, 26,
  56. 38, 39, 40, 41, 42,
  57. 54, 55, 56, 57, 58,
  58. },
  59. .oobfree = { {2, 4}, {11, 11}, {27, 11}, {43, 11}, {59, 5} },
  60. };
  61. #endif
  62. #elif defined(MXC_NFC_V2_1) || defined(MXC_NFC_V3_2)
  63. #ifndef CONFIG_SYS_NAND_LARGEPAGE
  64. static struct nand_ecclayout nand_hw_eccoob = {
  65. .eccbytes = 9,
  66. .eccpos = {7, 8, 9, 10, 11, 12, 13, 14, 15},
  67. .oobfree = { {2, 5} }
  68. };
  69. #else
  70. static struct nand_ecclayout nand_hw_eccoob2k = {
  71. .eccbytes = 36,
  72. .eccpos = {
  73. 7, 8, 9, 10, 11, 12, 13, 14, 15,
  74. 23, 24, 25, 26, 27, 28, 29, 30, 31,
  75. 39, 40, 41, 42, 43, 44, 45, 46, 47,
  76. 55, 56, 57, 58, 59, 60, 61, 62, 63,
  77. },
  78. .oobfree = { {2, 5}, {16, 7}, {32, 7}, {48, 7} },
  79. };
  80. #endif
  81. #endif
  82. static int is_16bit_nand(void)
  83. {
  84. #if defined(CONFIG_SYS_NAND_BUSWIDTH_16BIT)
  85. return 1;
  86. #else
  87. return 0;
  88. #endif
  89. }
  90. static uint32_t *mxc_nand_memcpy32(uint32_t *dest, uint32_t *source, size_t size)
  91. {
  92. uint32_t *d = dest;
  93. size >>= 2;
  94. while (size--)
  95. __raw_writel(__raw_readl(source++), d++);
  96. return dest;
  97. }
  98. /*
  99. * This function polls the NANDFC to wait for the basic operation to
  100. * complete by checking the INT bit.
  101. */
  102. static void wait_op_done(struct mxc_nand_host *host, int max_retries,
  103. uint16_t param)
  104. {
  105. uint32_t tmp;
  106. while (max_retries-- > 0) {
  107. #if defined(MXC_NFC_V1) || defined(MXC_NFC_V2_1)
  108. tmp = readnfc(&host->regs->config2);
  109. if (tmp & NFC_V1_V2_CONFIG2_INT) {
  110. tmp &= ~NFC_V1_V2_CONFIG2_INT;
  111. writenfc(tmp, &host->regs->config2);
  112. #elif defined(MXC_NFC_V3_2)
  113. tmp = readnfc(&host->ip_regs->ipc);
  114. if (tmp & NFC_V3_IPC_INT) {
  115. tmp &= ~NFC_V3_IPC_INT;
  116. writenfc(tmp, &host->ip_regs->ipc);
  117. #endif
  118. break;
  119. }
  120. udelay(1);
  121. }
  122. if (max_retries < 0) {
  123. MTDDEBUG(MTD_DEBUG_LEVEL0, "%s(%d): INT not set\n",
  124. __func__, param);
  125. }
  126. }
  127. /*
  128. * This function issues the specified command to the NAND device and
  129. * waits for completion.
  130. */
  131. static void send_cmd(struct mxc_nand_host *host, uint16_t cmd)
  132. {
  133. MTDDEBUG(MTD_DEBUG_LEVEL3, "send_cmd(host, 0x%x)\n", cmd);
  134. writenfc(cmd, &host->regs->flash_cmd);
  135. writenfc(NFC_CMD, &host->regs->operation);
  136. /* Wait for operation to complete */
  137. wait_op_done(host, TROP_US_DELAY, cmd);
  138. }
  139. /*
  140. * This function sends an address (or partial address) to the
  141. * NAND device. The address is used to select the source/destination for
  142. * a NAND command.
  143. */
  144. static void send_addr(struct mxc_nand_host *host, uint16_t addr)
  145. {
  146. MTDDEBUG(MTD_DEBUG_LEVEL3, "send_addr(host, 0x%x)\n", addr);
  147. writenfc(addr, &host->regs->flash_addr);
  148. writenfc(NFC_ADDR, &host->regs->operation);
  149. /* Wait for operation to complete */
  150. wait_op_done(host, TROP_US_DELAY, addr);
  151. }
  152. /*
  153. * This function requests the NANDFC to initiate the transfer
  154. * of data currently in the NANDFC RAM buffer to the NAND device.
  155. */
  156. static void send_prog_page(struct mxc_nand_host *host, uint8_t buf_id,
  157. int spare_only)
  158. {
  159. if (spare_only)
  160. MTDDEBUG(MTD_DEBUG_LEVEL1, "send_prog_page (%d)\n", spare_only);
  161. if (is_mxc_nfc_21() || is_mxc_nfc_32()) {
  162. int i;
  163. /*
  164. * The controller copies the 64 bytes of spare data from
  165. * the first 16 bytes of each of the 4 64 byte spare buffers.
  166. * Copy the contiguous data starting in spare_area[0] to
  167. * the four spare area buffers.
  168. */
  169. for (i = 1; i < 4; i++) {
  170. void __iomem *src = &host->regs->spare_area[0][i * 16];
  171. void __iomem *dst = &host->regs->spare_area[i][0];
  172. mxc_nand_memcpy32(dst, src, 16);
  173. }
  174. }
  175. #if defined(MXC_NFC_V1) || defined(MXC_NFC_V2_1)
  176. writenfc(buf_id, &host->regs->buf_addr);
  177. #elif defined(MXC_NFC_V3_2)
  178. uint32_t tmp = readnfc(&host->regs->config1);
  179. tmp &= ~NFC_V3_CONFIG1_RBA_MASK;
  180. tmp |= NFC_V3_CONFIG1_RBA(buf_id);
  181. writenfc(tmp, &host->regs->config1);
  182. #endif
  183. /* Configure spare or page+spare access */
  184. if (!host->pagesize_2k) {
  185. uint32_t config1 = readnfc(&host->regs->config1);
  186. if (spare_only)
  187. config1 |= NFC_CONFIG1_SP_EN;
  188. else
  189. config1 &= ~NFC_CONFIG1_SP_EN;
  190. writenfc(config1, &host->regs->config1);
  191. }
  192. writenfc(NFC_INPUT, &host->regs->operation);
  193. /* Wait for operation to complete */
  194. wait_op_done(host, TROP_US_DELAY, spare_only);
  195. }
  196. /*
  197. * Requests NANDFC to initiate the transfer of data from the
  198. * NAND device into in the NANDFC ram buffer.
  199. */
  200. static void send_read_page(struct mxc_nand_host *host, uint8_t buf_id,
  201. int spare_only)
  202. {
  203. MTDDEBUG(MTD_DEBUG_LEVEL3, "send_read_page (%d)\n", spare_only);
  204. #if defined(MXC_NFC_V1) || defined(MXC_NFC_V2_1)
  205. writenfc(buf_id, &host->regs->buf_addr);
  206. #elif defined(MXC_NFC_V3_2)
  207. uint32_t tmp = readnfc(&host->regs->config1);
  208. tmp &= ~NFC_V3_CONFIG1_RBA_MASK;
  209. tmp |= NFC_V3_CONFIG1_RBA(buf_id);
  210. writenfc(tmp, &host->regs->config1);
  211. #endif
  212. /* Configure spare or page+spare access */
  213. if (!host->pagesize_2k) {
  214. uint32_t config1 = readnfc(&host->regs->config1);
  215. if (spare_only)
  216. config1 |= NFC_CONFIG1_SP_EN;
  217. else
  218. config1 &= ~NFC_CONFIG1_SP_EN;
  219. writenfc(config1, &host->regs->config1);
  220. }
  221. writenfc(NFC_OUTPUT, &host->regs->operation);
  222. /* Wait for operation to complete */
  223. wait_op_done(host, TROP_US_DELAY, spare_only);
  224. if (is_mxc_nfc_21() || is_mxc_nfc_32()) {
  225. int i;
  226. /*
  227. * The controller copies the 64 bytes of spare data to
  228. * the first 16 bytes of each of the 4 spare buffers.
  229. * Make the data contiguous starting in spare_area[0].
  230. */
  231. for (i = 1; i < 4; i++) {
  232. void __iomem *src = &host->regs->spare_area[i][0];
  233. void __iomem *dst = &host->regs->spare_area[0][i * 16];
  234. mxc_nand_memcpy32(dst, src, 16);
  235. }
  236. }
  237. }
  238. /* Request the NANDFC to perform a read of the NAND device ID. */
  239. static void send_read_id(struct mxc_nand_host *host)
  240. {
  241. uint32_t tmp;
  242. #if defined(MXC_NFC_V1) || defined(MXC_NFC_V2_1)
  243. /* NANDFC buffer 0 is used for device ID output */
  244. writenfc(0x0, &host->regs->buf_addr);
  245. #elif defined(MXC_NFC_V3_2)
  246. tmp = readnfc(&host->regs->config1);
  247. tmp &= ~NFC_V3_CONFIG1_RBA_MASK;
  248. writenfc(tmp, &host->regs->config1);
  249. #endif
  250. /* Read ID into main buffer */
  251. tmp = readnfc(&host->regs->config1);
  252. tmp &= ~NFC_CONFIG1_SP_EN;
  253. writenfc(tmp, &host->regs->config1);
  254. writenfc(NFC_ID, &host->regs->operation);
  255. /* Wait for operation to complete */
  256. wait_op_done(host, TROP_US_DELAY, 0);
  257. }
  258. /*
  259. * This function requests the NANDFC to perform a read of the
  260. * NAND device status and returns the current status.
  261. */
  262. static uint16_t get_dev_status(struct mxc_nand_host *host)
  263. {
  264. #if defined(MXC_NFC_V1) || defined(MXC_NFC_V2_1)
  265. void __iomem *main_buf = host->regs->main_area[1];
  266. uint32_t store;
  267. #endif
  268. uint32_t ret, tmp;
  269. /* Issue status request to NAND device */
  270. #if defined(MXC_NFC_V1) || defined(MXC_NFC_V2_1)
  271. /* store the main area1 first word, later do recovery */
  272. store = readl(main_buf);
  273. /* NANDFC buffer 1 is used for device status */
  274. writenfc(1, &host->regs->buf_addr);
  275. #endif
  276. /* Read status into main buffer */
  277. tmp = readnfc(&host->regs->config1);
  278. tmp &= ~NFC_CONFIG1_SP_EN;
  279. writenfc(tmp, &host->regs->config1);
  280. writenfc(NFC_STATUS, &host->regs->operation);
  281. /* Wait for operation to complete */
  282. wait_op_done(host, TROP_US_DELAY, 0);
  283. #if defined(MXC_NFC_V1) || defined(MXC_NFC_V2_1)
  284. /*
  285. * Status is placed in first word of main buffer
  286. * get status, then recovery area 1 data
  287. */
  288. ret = readw(main_buf);
  289. writel(store, main_buf);
  290. #elif defined(MXC_NFC_V3_2)
  291. ret = readnfc(&host->regs->config1) >> 16;
  292. #endif
  293. return ret;
  294. }
  295. /* This function is used by upper layer to checks if device is ready */
  296. static int mxc_nand_dev_ready(struct mtd_info *mtd)
  297. {
  298. /*
  299. * NFC handles R/B internally. Therefore, this function
  300. * always returns status as ready.
  301. */
  302. return 1;
  303. }
  304. static void _mxc_nand_enable_hwecc(struct mtd_info *mtd, int on)
  305. {
  306. struct nand_chip *nand_chip = mtd_to_nand(mtd);
  307. struct mxc_nand_host *host = nand_get_controller_data(nand_chip);
  308. #if defined(MXC_NFC_V1) || defined(MXC_NFC_V2_1)
  309. uint16_t tmp = readnfc(&host->regs->config1);
  310. if (on)
  311. tmp |= NFC_V1_V2_CONFIG1_ECC_EN;
  312. else
  313. tmp &= ~NFC_V1_V2_CONFIG1_ECC_EN;
  314. writenfc(tmp, &host->regs->config1);
  315. #elif defined(MXC_NFC_V3_2)
  316. uint32_t tmp = readnfc(&host->ip_regs->config2);
  317. if (on)
  318. tmp |= NFC_V3_CONFIG2_ECC_EN;
  319. else
  320. tmp &= ~NFC_V3_CONFIG2_ECC_EN;
  321. writenfc(tmp, &host->ip_regs->config2);
  322. #endif
  323. }
  324. #ifdef CONFIG_MXC_NAND_HWECC
  325. static void mxc_nand_enable_hwecc(struct mtd_info *mtd, int mode)
  326. {
  327. /*
  328. * If HW ECC is enabled, we turn it on during init. There is
  329. * no need to enable again here.
  330. */
  331. }
  332. #if defined(MXC_NFC_V2_1) || defined(MXC_NFC_V3_2)
  333. static int mxc_nand_read_oob_syndrome(struct mtd_info *mtd,
  334. struct nand_chip *chip,
  335. int page)
  336. {
  337. struct mxc_nand_host *host = nand_get_controller_data(chip);
  338. uint8_t *buf = chip->oob_poi;
  339. int length = mtd->oobsize;
  340. int eccpitch = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad;
  341. uint8_t *bufpoi = buf;
  342. int i, toread;
  343. MTDDEBUG(MTD_DEBUG_LEVEL0,
  344. "%s: Reading OOB area of page %u to oob %p\n",
  345. __func__, page, buf);
  346. chip->cmdfunc(mtd, NAND_CMD_READOOB, mtd->writesize, page);
  347. for (i = 0; i < chip->ecc.steps; i++) {
  348. toread = min_t(int, length, chip->ecc.prepad);
  349. if (toread) {
  350. chip->read_buf(mtd, bufpoi, toread);
  351. bufpoi += toread;
  352. length -= toread;
  353. }
  354. bufpoi += chip->ecc.bytes;
  355. host->col_addr += chip->ecc.bytes;
  356. length -= chip->ecc.bytes;
  357. toread = min_t(int, length, chip->ecc.postpad);
  358. if (toread) {
  359. chip->read_buf(mtd, bufpoi, toread);
  360. bufpoi += toread;
  361. length -= toread;
  362. }
  363. }
  364. if (length > 0)
  365. chip->read_buf(mtd, bufpoi, length);
  366. _mxc_nand_enable_hwecc(mtd, 0);
  367. chip->cmdfunc(mtd, NAND_CMD_READOOB,
  368. mtd->writesize + chip->ecc.prepad, page);
  369. bufpoi = buf + chip->ecc.prepad;
  370. length = mtd->oobsize - chip->ecc.prepad;
  371. for (i = 0; i < chip->ecc.steps; i++) {
  372. toread = min_t(int, length, chip->ecc.bytes);
  373. chip->read_buf(mtd, bufpoi, toread);
  374. bufpoi += eccpitch;
  375. length -= eccpitch;
  376. host->col_addr += chip->ecc.postpad + chip->ecc.prepad;
  377. }
  378. _mxc_nand_enable_hwecc(mtd, 1);
  379. return 1;
  380. }
  381. static int mxc_nand_read_page_raw_syndrome(struct mtd_info *mtd,
  382. struct nand_chip *chip,
  383. uint8_t *buf,
  384. int oob_required,
  385. int page)
  386. {
  387. struct mxc_nand_host *host = nand_get_controller_data(chip);
  388. int eccsize = chip->ecc.size;
  389. int eccbytes = chip->ecc.bytes;
  390. int eccpitch = eccbytes + chip->ecc.prepad + chip->ecc.postpad;
  391. uint8_t *oob = chip->oob_poi;
  392. int steps, size;
  393. int n;
  394. _mxc_nand_enable_hwecc(mtd, 0);
  395. chip->cmdfunc(mtd, NAND_CMD_READ0, 0x00, page);
  396. for (n = 0, steps = chip->ecc.steps; steps > 0; n++, steps--) {
  397. host->col_addr = n * eccsize;
  398. chip->read_buf(mtd, buf, eccsize);
  399. buf += eccsize;
  400. host->col_addr = mtd->writesize + n * eccpitch;
  401. if (chip->ecc.prepad) {
  402. chip->read_buf(mtd, oob, chip->ecc.prepad);
  403. oob += chip->ecc.prepad;
  404. }
  405. chip->read_buf(mtd, oob, eccbytes);
  406. oob += eccbytes;
  407. if (chip->ecc.postpad) {
  408. chip->read_buf(mtd, oob, chip->ecc.postpad);
  409. oob += chip->ecc.postpad;
  410. }
  411. }
  412. size = mtd->oobsize - (oob - chip->oob_poi);
  413. if (size)
  414. chip->read_buf(mtd, oob, size);
  415. _mxc_nand_enable_hwecc(mtd, 1);
  416. return 0;
  417. }
  418. static int mxc_nand_read_page_syndrome(struct mtd_info *mtd,
  419. struct nand_chip *chip,
  420. uint8_t *buf,
  421. int oob_required,
  422. int page)
  423. {
  424. struct mxc_nand_host *host = nand_get_controller_data(chip);
  425. int n, eccsize = chip->ecc.size;
  426. int eccbytes = chip->ecc.bytes;
  427. int eccpitch = eccbytes + chip->ecc.prepad + chip->ecc.postpad;
  428. int eccsteps = chip->ecc.steps;
  429. uint8_t *p = buf;
  430. uint8_t *oob = chip->oob_poi;
  431. MTDDEBUG(MTD_DEBUG_LEVEL1, "Reading page %u to buf %p oob %p\n",
  432. page, buf, oob);
  433. /* first read the data area and the available portion of OOB */
  434. for (n = 0; eccsteps; n++, eccsteps--, p += eccsize) {
  435. int stat;
  436. host->col_addr = n * eccsize;
  437. chip->read_buf(mtd, p, eccsize);
  438. host->col_addr = mtd->writesize + n * eccpitch;
  439. if (chip->ecc.prepad) {
  440. chip->read_buf(mtd, oob, chip->ecc.prepad);
  441. oob += chip->ecc.prepad;
  442. }
  443. stat = chip->ecc.correct(mtd, p, oob, NULL);
  444. if (stat < 0)
  445. mtd->ecc_stats.failed++;
  446. else
  447. mtd->ecc_stats.corrected += stat;
  448. oob += eccbytes;
  449. if (chip->ecc.postpad) {
  450. chip->read_buf(mtd, oob, chip->ecc.postpad);
  451. oob += chip->ecc.postpad;
  452. }
  453. }
  454. /* Calculate remaining oob bytes */
  455. n = mtd->oobsize - (oob - chip->oob_poi);
  456. if (n)
  457. chip->read_buf(mtd, oob, n);
  458. /* Then switch ECC off and read the OOB area to get the ECC code */
  459. _mxc_nand_enable_hwecc(mtd, 0);
  460. chip->cmdfunc(mtd, NAND_CMD_READOOB, mtd->writesize, page);
  461. eccsteps = chip->ecc.steps;
  462. oob = chip->oob_poi + chip->ecc.prepad;
  463. for (n = 0; eccsteps; n++, eccsteps--, p += eccsize) {
  464. host->col_addr = mtd->writesize +
  465. n * eccpitch +
  466. chip->ecc.prepad;
  467. chip->read_buf(mtd, oob, eccbytes);
  468. oob += eccbytes + chip->ecc.postpad;
  469. }
  470. _mxc_nand_enable_hwecc(mtd, 1);
  471. return 0;
  472. }
  473. static int mxc_nand_write_oob_syndrome(struct mtd_info *mtd,
  474. struct nand_chip *chip, int page)
  475. {
  476. struct mxc_nand_host *host = nand_get_controller_data(chip);
  477. int eccpitch = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad;
  478. int length = mtd->oobsize;
  479. int i, len, status, steps = chip->ecc.steps;
  480. const uint8_t *bufpoi = chip->oob_poi;
  481. chip->cmdfunc(mtd, NAND_CMD_SEQIN, mtd->writesize, page);
  482. for (i = 0; i < steps; i++) {
  483. len = min_t(int, length, eccpitch);
  484. chip->write_buf(mtd, bufpoi, len);
  485. bufpoi += len;
  486. length -= len;
  487. host->col_addr += chip->ecc.prepad + chip->ecc.postpad;
  488. }
  489. if (length > 0)
  490. chip->write_buf(mtd, bufpoi, length);
  491. chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
  492. status = chip->waitfunc(mtd, chip);
  493. return status & NAND_STATUS_FAIL ? -EIO : 0;
  494. }
  495. static int mxc_nand_write_page_raw_syndrome(struct mtd_info *mtd,
  496. struct nand_chip *chip,
  497. const uint8_t *buf,
  498. int oob_required)
  499. {
  500. struct mxc_nand_host *host = nand_get_controller_data(chip);
  501. int eccsize = chip->ecc.size;
  502. int eccbytes = chip->ecc.bytes;
  503. int eccpitch = eccbytes + chip->ecc.prepad + chip->ecc.postpad;
  504. uint8_t *oob = chip->oob_poi;
  505. int steps, size;
  506. int n;
  507. for (n = 0, steps = chip->ecc.steps; steps > 0; n++, steps--) {
  508. host->col_addr = n * eccsize;
  509. chip->write_buf(mtd, buf, eccsize);
  510. buf += eccsize;
  511. host->col_addr = mtd->writesize + n * eccpitch;
  512. if (chip->ecc.prepad) {
  513. chip->write_buf(mtd, oob, chip->ecc.prepad);
  514. oob += chip->ecc.prepad;
  515. }
  516. host->col_addr += eccbytes;
  517. oob += eccbytes;
  518. if (chip->ecc.postpad) {
  519. chip->write_buf(mtd, oob, chip->ecc.postpad);
  520. oob += chip->ecc.postpad;
  521. }
  522. }
  523. size = mtd->oobsize - (oob - chip->oob_poi);
  524. if (size)
  525. chip->write_buf(mtd, oob, size);
  526. return 0;
  527. }
  528. static int mxc_nand_write_page_syndrome(struct mtd_info *mtd,
  529. struct nand_chip *chip,
  530. const uint8_t *buf,
  531. int oob_required)
  532. {
  533. struct mxc_nand_host *host = nand_get_controller_data(chip);
  534. int i, n, eccsize = chip->ecc.size;
  535. int eccbytes = chip->ecc.bytes;
  536. int eccpitch = eccbytes + chip->ecc.prepad + chip->ecc.postpad;
  537. int eccsteps = chip->ecc.steps;
  538. const uint8_t *p = buf;
  539. uint8_t *oob = chip->oob_poi;
  540. chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
  541. for (i = n = 0;
  542. eccsteps;
  543. n++, eccsteps--, i += eccbytes, p += eccsize) {
  544. host->col_addr = n * eccsize;
  545. chip->write_buf(mtd, p, eccsize);
  546. host->col_addr = mtd->writesize + n * eccpitch;
  547. if (chip->ecc.prepad) {
  548. chip->write_buf(mtd, oob, chip->ecc.prepad);
  549. oob += chip->ecc.prepad;
  550. }
  551. chip->write_buf(mtd, oob, eccbytes);
  552. oob += eccbytes;
  553. if (chip->ecc.postpad) {
  554. chip->write_buf(mtd, oob, chip->ecc.postpad);
  555. oob += chip->ecc.postpad;
  556. }
  557. }
  558. /* Calculate remaining oob bytes */
  559. i = mtd->oobsize - (oob - chip->oob_poi);
  560. if (i)
  561. chip->write_buf(mtd, oob, i);
  562. return 0;
  563. }
  564. static int mxc_nand_correct_data(struct mtd_info *mtd, u_char *dat,
  565. u_char *read_ecc, u_char *calc_ecc)
  566. {
  567. struct nand_chip *nand_chip = mtd_to_nand(mtd);
  568. struct mxc_nand_host *host = nand_get_controller_data(nand_chip);
  569. uint32_t ecc_status = readl(&host->regs->ecc_status_result);
  570. int subpages = mtd->writesize / nand_chip->subpagesize;
  571. int pg2blk_shift = nand_chip->phys_erase_shift -
  572. nand_chip->page_shift;
  573. do {
  574. if ((ecc_status & 0xf) > 4) {
  575. static int last_bad = -1;
  576. if (last_bad != host->page_addr >> pg2blk_shift) {
  577. last_bad = host->page_addr >> pg2blk_shift;
  578. printk(KERN_DEBUG
  579. "MXC_NAND: HWECC uncorrectable ECC error"
  580. " in block %u page %u subpage %d\n",
  581. last_bad, host->page_addr,
  582. mtd->writesize / nand_chip->subpagesize
  583. - subpages);
  584. }
  585. return -1;
  586. }
  587. ecc_status >>= 4;
  588. subpages--;
  589. } while (subpages > 0);
  590. return 0;
  591. }
  592. #else
  593. #define mxc_nand_read_page_syndrome NULL
  594. #define mxc_nand_read_page_raw_syndrome NULL
  595. #define mxc_nand_read_oob_syndrome NULL
  596. #define mxc_nand_write_page_syndrome NULL
  597. #define mxc_nand_write_page_raw_syndrome NULL
  598. #define mxc_nand_write_oob_syndrome NULL
  599. static int mxc_nand_correct_data(struct mtd_info *mtd, u_char *dat,
  600. u_char *read_ecc, u_char *calc_ecc)
  601. {
  602. struct nand_chip *nand_chip = mtd_to_nand(mtd);
  603. struct mxc_nand_host *host = nand_get_controller_data(nand_chip);
  604. /*
  605. * 1-Bit errors are automatically corrected in HW. No need for
  606. * additional correction. 2-Bit errors cannot be corrected by
  607. * HW ECC, so we need to return failure
  608. */
  609. uint16_t ecc_status = readnfc(&host->regs->ecc_status_result);
  610. if (((ecc_status & 0x3) == 2) || ((ecc_status >> 2) == 2)) {
  611. MTDDEBUG(MTD_DEBUG_LEVEL0,
  612. "MXC_NAND: HWECC uncorrectable 2-bit ECC error\n");
  613. return -1;
  614. }
  615. return 0;
  616. }
  617. #endif
  618. static int mxc_nand_calculate_ecc(struct mtd_info *mtd, const u_char *dat,
  619. u_char *ecc_code)
  620. {
  621. return 0;
  622. }
  623. #endif
  624. static u_char mxc_nand_read_byte(struct mtd_info *mtd)
  625. {
  626. struct nand_chip *nand_chip = mtd_to_nand(mtd);
  627. struct mxc_nand_host *host = nand_get_controller_data(nand_chip);
  628. uint8_t ret = 0;
  629. uint16_t col;
  630. uint16_t __iomem *main_buf =
  631. (uint16_t __iomem *)host->regs->main_area[0];
  632. uint16_t __iomem *spare_buf =
  633. (uint16_t __iomem *)host->regs->spare_area[0];
  634. union {
  635. uint16_t word;
  636. uint8_t bytes[2];
  637. } nfc_word;
  638. /* Check for status request */
  639. if (host->status_request)
  640. return get_dev_status(host) & 0xFF;
  641. /* Get column for 16-bit access */
  642. col = host->col_addr >> 1;
  643. /* If we are accessing the spare region */
  644. if (host->spare_only)
  645. nfc_word.word = readw(&spare_buf[col]);
  646. else
  647. nfc_word.word = readw(&main_buf[col]);
  648. /* Pick upper/lower byte of word from RAM buffer */
  649. ret = nfc_word.bytes[host->col_addr & 0x1];
  650. /* Update saved column address */
  651. if (nand_chip->options & NAND_BUSWIDTH_16)
  652. host->col_addr += 2;
  653. else
  654. host->col_addr++;
  655. return ret;
  656. }
  657. static uint16_t mxc_nand_read_word(struct mtd_info *mtd)
  658. {
  659. struct nand_chip *nand_chip = mtd_to_nand(mtd);
  660. struct mxc_nand_host *host = nand_get_controller_data(nand_chip);
  661. uint16_t col, ret;
  662. uint16_t __iomem *p;
  663. MTDDEBUG(MTD_DEBUG_LEVEL3,
  664. "mxc_nand_read_word(col = %d)\n", host->col_addr);
  665. col = host->col_addr;
  666. /* Adjust saved column address */
  667. if (col < mtd->writesize && host->spare_only)
  668. col += mtd->writesize;
  669. if (col < mtd->writesize) {
  670. p = (uint16_t __iomem *)(host->regs->main_area[0] +
  671. (col >> 1));
  672. } else {
  673. p = (uint16_t __iomem *)(host->regs->spare_area[0] +
  674. ((col - mtd->writesize) >> 1));
  675. }
  676. if (col & 1) {
  677. union {
  678. uint16_t word;
  679. uint8_t bytes[2];
  680. } nfc_word[3];
  681. nfc_word[0].word = readw(p);
  682. nfc_word[1].word = readw(p + 1);
  683. nfc_word[2].bytes[0] = nfc_word[0].bytes[1];
  684. nfc_word[2].bytes[1] = nfc_word[1].bytes[0];
  685. ret = nfc_word[2].word;
  686. } else {
  687. ret = readw(p);
  688. }
  689. /* Update saved column address */
  690. host->col_addr = col + 2;
  691. return ret;
  692. }
  693. /*
  694. * Write data of length len to buffer buf. The data to be
  695. * written on NAND Flash is first copied to RAMbuffer. After the Data Input
  696. * Operation by the NFC, the data is written to NAND Flash
  697. */
  698. static void mxc_nand_write_buf(struct mtd_info *mtd,
  699. const u_char *buf, int len)
  700. {
  701. struct nand_chip *nand_chip = mtd_to_nand(mtd);
  702. struct mxc_nand_host *host = nand_get_controller_data(nand_chip);
  703. int n, col, i = 0;
  704. MTDDEBUG(MTD_DEBUG_LEVEL3,
  705. "mxc_nand_write_buf(col = %d, len = %d)\n", host->col_addr,
  706. len);
  707. col = host->col_addr;
  708. /* Adjust saved column address */
  709. if (col < mtd->writesize && host->spare_only)
  710. col += mtd->writesize;
  711. n = mtd->writesize + mtd->oobsize - col;
  712. n = min(len, n);
  713. MTDDEBUG(MTD_DEBUG_LEVEL3,
  714. "%s:%d: col = %d, n = %d\n", __func__, __LINE__, col, n);
  715. while (n > 0) {
  716. void __iomem *p;
  717. if (col < mtd->writesize) {
  718. p = host->regs->main_area[0] + (col & ~3);
  719. } else {
  720. p = host->regs->spare_area[0] -
  721. mtd->writesize + (col & ~3);
  722. }
  723. MTDDEBUG(MTD_DEBUG_LEVEL3, "%s:%d: p = %p\n", __func__,
  724. __LINE__, p);
  725. if (((col | (unsigned long)&buf[i]) & 3) || n < 4) {
  726. union {
  727. uint32_t word;
  728. uint8_t bytes[4];
  729. } nfc_word;
  730. nfc_word.word = readl(p);
  731. nfc_word.bytes[col & 3] = buf[i++];
  732. n--;
  733. col++;
  734. writel(nfc_word.word, p);
  735. } else {
  736. int m = mtd->writesize - col;
  737. if (col >= mtd->writesize)
  738. m += mtd->oobsize;
  739. m = min(n, m) & ~3;
  740. MTDDEBUG(MTD_DEBUG_LEVEL3,
  741. "%s:%d: n = %d, m = %d, i = %d, col = %d\n",
  742. __func__, __LINE__, n, m, i, col);
  743. mxc_nand_memcpy32(p, (uint32_t *)&buf[i], m);
  744. col += m;
  745. i += m;
  746. n -= m;
  747. }
  748. }
  749. /* Update saved column address */
  750. host->col_addr = col;
  751. }
  752. /*
  753. * Read the data buffer from the NAND Flash. To read the data from NAND
  754. * Flash first the data output cycle is initiated by the NFC, which copies
  755. * the data to RAMbuffer. This data of length len is then copied to buffer buf.
  756. */
  757. static void mxc_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len)
  758. {
  759. struct nand_chip *nand_chip = mtd_to_nand(mtd);
  760. struct mxc_nand_host *host = nand_get_controller_data(nand_chip);
  761. int n, col, i = 0;
  762. MTDDEBUG(MTD_DEBUG_LEVEL3,
  763. "mxc_nand_read_buf(col = %d, len = %d)\n", host->col_addr, len);
  764. col = host->col_addr;
  765. /* Adjust saved column address */
  766. if (col < mtd->writesize && host->spare_only)
  767. col += mtd->writesize;
  768. n = mtd->writesize + mtd->oobsize - col;
  769. n = min(len, n);
  770. while (n > 0) {
  771. void __iomem *p;
  772. if (col < mtd->writesize) {
  773. p = host->regs->main_area[0] + (col & ~3);
  774. } else {
  775. p = host->regs->spare_area[0] -
  776. mtd->writesize + (col & ~3);
  777. }
  778. if (((col | (int)&buf[i]) & 3) || n < 4) {
  779. union {
  780. uint32_t word;
  781. uint8_t bytes[4];
  782. } nfc_word;
  783. nfc_word.word = readl(p);
  784. buf[i++] = nfc_word.bytes[col & 3];
  785. n--;
  786. col++;
  787. } else {
  788. int m = mtd->writesize - col;
  789. if (col >= mtd->writesize)
  790. m += mtd->oobsize;
  791. m = min(n, m) & ~3;
  792. mxc_nand_memcpy32((uint32_t *)&buf[i], p, m);
  793. col += m;
  794. i += m;
  795. n -= m;
  796. }
  797. }
  798. /* Update saved column address */
  799. host->col_addr = col;
  800. }
  801. /*
  802. * This function is used by upper layer for select and
  803. * deselect of the NAND chip
  804. */
  805. static void mxc_nand_select_chip(struct mtd_info *mtd, int chip)
  806. {
  807. struct nand_chip *nand_chip = mtd_to_nand(mtd);
  808. struct mxc_nand_host *host = nand_get_controller_data(nand_chip);
  809. switch (chip) {
  810. case -1:
  811. /* TODO: Disable the NFC clock */
  812. if (host->clk_act)
  813. host->clk_act = 0;
  814. break;
  815. case 0:
  816. /* TODO: Enable the NFC clock */
  817. if (!host->clk_act)
  818. host->clk_act = 1;
  819. break;
  820. default:
  821. break;
  822. }
  823. }
  824. /*
  825. * Used by the upper layer to write command to NAND Flash for
  826. * different operations to be carried out on NAND Flash
  827. */
  828. void mxc_nand_command(struct mtd_info *mtd, unsigned command,
  829. int column, int page_addr)
  830. {
  831. struct nand_chip *nand_chip = mtd_to_nand(mtd);
  832. struct mxc_nand_host *host = nand_get_controller_data(nand_chip);
  833. MTDDEBUG(MTD_DEBUG_LEVEL3,
  834. "mxc_nand_command (cmd = 0x%x, col = 0x%x, page = 0x%x)\n",
  835. command, column, page_addr);
  836. /* Reset command state information */
  837. host->status_request = false;
  838. /* Command pre-processing step */
  839. switch (command) {
  840. case NAND_CMD_STATUS:
  841. host->col_addr = 0;
  842. host->status_request = true;
  843. break;
  844. case NAND_CMD_READ0:
  845. host->page_addr = page_addr;
  846. host->col_addr = column;
  847. host->spare_only = false;
  848. break;
  849. case NAND_CMD_READOOB:
  850. host->col_addr = column;
  851. host->spare_only = true;
  852. if (host->pagesize_2k)
  853. command = NAND_CMD_READ0; /* only READ0 is valid */
  854. break;
  855. case NAND_CMD_SEQIN:
  856. if (column >= mtd->writesize) {
  857. /*
  858. * before sending SEQIN command for partial write,
  859. * we need read one page out. FSL NFC does not support
  860. * partial write. It always sends out 512+ecc+512+ecc
  861. * for large page nand flash. But for small page nand
  862. * flash, it does support SPARE ONLY operation.
  863. */
  864. if (host->pagesize_2k) {
  865. /* call ourself to read a page */
  866. mxc_nand_command(mtd, NAND_CMD_READ0, 0,
  867. page_addr);
  868. }
  869. host->col_addr = column - mtd->writesize;
  870. host->spare_only = true;
  871. /* Set program pointer to spare region */
  872. if (!host->pagesize_2k)
  873. send_cmd(host, NAND_CMD_READOOB);
  874. } else {
  875. host->spare_only = false;
  876. host->col_addr = column;
  877. /* Set program pointer to page start */
  878. if (!host->pagesize_2k)
  879. send_cmd(host, NAND_CMD_READ0);
  880. }
  881. break;
  882. case NAND_CMD_PAGEPROG:
  883. send_prog_page(host, 0, host->spare_only);
  884. if (host->pagesize_2k && is_mxc_nfc_1()) {
  885. /* data in 4 areas */
  886. send_prog_page(host, 1, host->spare_only);
  887. send_prog_page(host, 2, host->spare_only);
  888. send_prog_page(host, 3, host->spare_only);
  889. }
  890. break;
  891. }
  892. /* Write out the command to the device. */
  893. send_cmd(host, command);
  894. /* Write out column address, if necessary */
  895. if (column != -1) {
  896. /*
  897. * MXC NANDFC can only perform full page+spare or
  898. * spare-only read/write. When the upper layers perform
  899. * a read/write buffer operation, we will use the saved
  900. * column address to index into the full page.
  901. */
  902. send_addr(host, 0);
  903. if (host->pagesize_2k)
  904. /* another col addr cycle for 2k page */
  905. send_addr(host, 0);
  906. }
  907. /* Write out page address, if necessary */
  908. if (page_addr != -1) {
  909. u32 page_mask = nand_chip->pagemask;
  910. do {
  911. send_addr(host, page_addr & 0xFF);
  912. page_addr >>= 8;
  913. page_mask >>= 8;
  914. } while (page_mask);
  915. }
  916. /* Command post-processing step */
  917. switch (command) {
  918. case NAND_CMD_RESET:
  919. break;
  920. case NAND_CMD_READOOB:
  921. case NAND_CMD_READ0:
  922. if (host->pagesize_2k) {
  923. /* send read confirm command */
  924. send_cmd(host, NAND_CMD_READSTART);
  925. /* read for each AREA */
  926. send_read_page(host, 0, host->spare_only);
  927. if (is_mxc_nfc_1()) {
  928. send_read_page(host, 1, host->spare_only);
  929. send_read_page(host, 2, host->spare_only);
  930. send_read_page(host, 3, host->spare_only);
  931. }
  932. } else {
  933. send_read_page(host, 0, host->spare_only);
  934. }
  935. break;
  936. case NAND_CMD_READID:
  937. host->col_addr = 0;
  938. send_read_id(host);
  939. break;
  940. case NAND_CMD_PAGEPROG:
  941. break;
  942. case NAND_CMD_STATUS:
  943. break;
  944. case NAND_CMD_ERASE2:
  945. break;
  946. }
  947. }
  948. #ifdef CONFIG_SYS_NAND_USE_FLASH_BBT
  949. static u8 bbt_pattern[] = {'B', 'b', 't', '0' };
  950. static u8 mirror_pattern[] = {'1', 't', 'b', 'B' };
  951. static struct nand_bbt_descr bbt_main_descr = {
  952. .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE |
  953. NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP,
  954. .offs = 0,
  955. .len = 4,
  956. .veroffs = 4,
  957. .maxblocks = 4,
  958. .pattern = bbt_pattern,
  959. };
  960. static struct nand_bbt_descr bbt_mirror_descr = {
  961. .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE |
  962. NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP,
  963. .offs = 0,
  964. .len = 4,
  965. .veroffs = 4,
  966. .maxblocks = 4,
  967. .pattern = mirror_pattern,
  968. };
  969. #endif
  970. int board_nand_init(struct nand_chip *this)
  971. {
  972. struct mtd_info *mtd;
  973. #if defined(MXC_NFC_V2_1) || defined(MXC_NFC_V3_2)
  974. uint32_t tmp;
  975. #endif
  976. #ifdef CONFIG_SYS_NAND_USE_FLASH_BBT
  977. this->bbt_options |= NAND_BBT_USE_FLASH;
  978. this->bbt_td = &bbt_main_descr;
  979. this->bbt_md = &bbt_mirror_descr;
  980. #endif
  981. /* structures must be linked */
  982. mtd = &this->mtd;
  983. host->nand = this;
  984. /* 5 us command delay time */
  985. this->chip_delay = 5;
  986. nand_set_controller_data(this, host);
  987. this->dev_ready = mxc_nand_dev_ready;
  988. this->cmdfunc = mxc_nand_command;
  989. this->select_chip = mxc_nand_select_chip;
  990. this->read_byte = mxc_nand_read_byte;
  991. this->read_word = mxc_nand_read_word;
  992. this->write_buf = mxc_nand_write_buf;
  993. this->read_buf = mxc_nand_read_buf;
  994. host->regs = (struct mxc_nand_regs __iomem *)CONFIG_MXC_NAND_REGS_BASE;
  995. #ifdef MXC_NFC_V3_2
  996. host->ip_regs =
  997. (struct mxc_nand_ip_regs __iomem *)CONFIG_MXC_NAND_IP_REGS_BASE;
  998. #endif
  999. host->clk_act = 1;
  1000. #ifdef CONFIG_MXC_NAND_HWECC
  1001. this->ecc.calculate = mxc_nand_calculate_ecc;
  1002. this->ecc.hwctl = mxc_nand_enable_hwecc;
  1003. this->ecc.correct = mxc_nand_correct_data;
  1004. if (is_mxc_nfc_21() || is_mxc_nfc_32()) {
  1005. this->ecc.mode = NAND_ECC_HW_SYNDROME;
  1006. this->ecc.read_page = mxc_nand_read_page_syndrome;
  1007. this->ecc.read_page_raw = mxc_nand_read_page_raw_syndrome;
  1008. this->ecc.read_oob = mxc_nand_read_oob_syndrome;
  1009. this->ecc.write_page = mxc_nand_write_page_syndrome;
  1010. this->ecc.write_page_raw = mxc_nand_write_page_raw_syndrome;
  1011. this->ecc.write_oob = mxc_nand_write_oob_syndrome;
  1012. this->ecc.bytes = 9;
  1013. this->ecc.prepad = 7;
  1014. } else {
  1015. this->ecc.mode = NAND_ECC_HW;
  1016. }
  1017. if (is_mxc_nfc_1())
  1018. this->ecc.strength = 1;
  1019. else
  1020. this->ecc.strength = 4;
  1021. host->pagesize_2k = 0;
  1022. this->ecc.size = 512;
  1023. _mxc_nand_enable_hwecc(mtd, 1);
  1024. #else
  1025. this->ecc.layout = &nand_soft_eccoob;
  1026. this->ecc.mode = NAND_ECC_SOFT;
  1027. _mxc_nand_enable_hwecc(mtd, 0);
  1028. #endif
  1029. /* Reset NAND */
  1030. this->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
  1031. /* NAND bus width determines access functions used by upper layer */
  1032. if (is_16bit_nand())
  1033. this->options |= NAND_BUSWIDTH_16;
  1034. #ifdef CONFIG_SYS_NAND_LARGEPAGE
  1035. host->pagesize_2k = 1;
  1036. this->ecc.layout = &nand_hw_eccoob2k;
  1037. #else
  1038. host->pagesize_2k = 0;
  1039. this->ecc.layout = &nand_hw_eccoob;
  1040. #endif
  1041. #if defined(MXC_NFC_V1) || defined(MXC_NFC_V2_1)
  1042. #ifdef MXC_NFC_V2_1
  1043. tmp = readnfc(&host->regs->config1);
  1044. tmp |= NFC_V2_CONFIG1_ONE_CYCLE;
  1045. tmp |= NFC_V2_CONFIG1_ECC_MODE_4;
  1046. writenfc(tmp, &host->regs->config1);
  1047. if (host->pagesize_2k)
  1048. writenfc(64/2, &host->regs->spare_area_size);
  1049. else
  1050. writenfc(16/2, &host->regs->spare_area_size);
  1051. #endif
  1052. /*
  1053. * preset operation
  1054. * Unlock the internal RAM Buffer
  1055. */
  1056. writenfc(0x2, &host->regs->config);
  1057. /* Blocks to be unlocked */
  1058. writenfc(0x0, &host->regs->unlockstart_blkaddr);
  1059. /* Originally (Freescale LTIB 2.6.21) 0x4000 was written to the
  1060. * unlockend_blkaddr, but the magic 0x4000 does not always work
  1061. * when writing more than some 32 megabytes (on 2k page nands)
  1062. * However 0xFFFF doesn't seem to have this kind
  1063. * of limitation (tried it back and forth several times).
  1064. * The linux kernel driver sets this to 0xFFFF for the v2 controller
  1065. * only, but probably this was not tested there for v1.
  1066. * The very same limitation seems to apply to this kernel driver.
  1067. * This might be NAND chip specific and the i.MX31 datasheet is
  1068. * extremely vague about the semantics of this register.
  1069. */
  1070. writenfc(0xFFFF, &host->regs->unlockend_blkaddr);
  1071. /* Unlock Block Command for given address range */
  1072. writenfc(0x4, &host->regs->wrprot);
  1073. #elif defined(MXC_NFC_V3_2)
  1074. writenfc(NFC_V3_CONFIG1_RBA(0), &host->regs->config1);
  1075. writenfc(NFC_V3_IPC_CREQ, &host->ip_regs->ipc);
  1076. /* Unlock the internal RAM Buffer */
  1077. writenfc(NFC_V3_WRPROT_BLS_UNLOCK | NFC_V3_WRPROT_UNLOCK,
  1078. &host->ip_regs->wrprot);
  1079. /* Blocks to be unlocked */
  1080. for (tmp = 0; tmp < CONFIG_SYS_NAND_MAX_CHIPS; tmp++)
  1081. writenfc(0x0 | 0xFFFF << 16,
  1082. &host->ip_regs->wrprot_unlock_blkaddr[tmp]);
  1083. writenfc(0, &host->ip_regs->ipc);
  1084. tmp = readnfc(&host->ip_regs->config2);
  1085. tmp &= ~(NFC_V3_CONFIG2_SPAS_MASK | NFC_V3_CONFIG2_EDC_MASK |
  1086. NFC_V3_CONFIG2_ECC_MODE_8 | NFC_V3_CONFIG2_PS_MASK);
  1087. tmp |= NFC_V3_CONFIG2_ONE_CYCLE;
  1088. if (host->pagesize_2k) {
  1089. tmp |= NFC_V3_CONFIG2_SPAS(64/2);
  1090. tmp |= NFC_V3_CONFIG2_PS_2048;
  1091. } else {
  1092. tmp |= NFC_V3_CONFIG2_SPAS(16/2);
  1093. tmp |= NFC_V3_CONFIG2_PS_512;
  1094. }
  1095. writenfc(tmp, &host->ip_regs->config2);
  1096. tmp = NFC_V3_CONFIG3_NUM_OF_DEVS(0) |
  1097. NFC_V3_CONFIG3_NO_SDMA |
  1098. NFC_V3_CONFIG3_RBB_MODE |
  1099. NFC_V3_CONFIG3_SBB(6) | /* Reset default */
  1100. NFC_V3_CONFIG3_ADD_OP(0);
  1101. if (!(this->options & NAND_BUSWIDTH_16))
  1102. tmp |= NFC_V3_CONFIG3_FW8;
  1103. writenfc(tmp, &host->ip_regs->config3);
  1104. writenfc(0, &host->ip_regs->delay_line);
  1105. #endif
  1106. return 0;
  1107. }