lpc32xx_nand_slc.c 17 KB

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  1. /*
  2. * LPC32xx SLC NAND flash controller driver
  3. *
  4. * (C) Copyright 2015 Vladimir Zapolskiy <vz@mleia.com>
  5. *
  6. * Hardware ECC support original source code
  7. * Copyright (C) 2008 by NXP Semiconductors
  8. * Author: Kevin Wells
  9. *
  10. * Copyright (c) 2015 Tyco Fire Protection Products.
  11. *
  12. * SPDX-License-Identifier: GPL-2.0+
  13. */
  14. #include <common.h>
  15. #include <nand.h>
  16. #include <linux/mtd/nand_ecc.h>
  17. #include <asm/errno.h>
  18. #include <asm/io.h>
  19. #include <asm/arch/config.h>
  20. #include <asm/arch/clk.h>
  21. #include <asm/arch/sys_proto.h>
  22. #include <asm/arch/dma.h>
  23. #include <asm/arch/cpu.h>
  24. #if defined(CONFIG_DMA_LPC32XX) && defined(CONFIG_SPL_BUILD)
  25. #warning "DMA support in SPL image is not tested"
  26. #endif
  27. struct lpc32xx_nand_slc_regs {
  28. u32 data;
  29. u32 addr;
  30. u32 cmd;
  31. u32 stop;
  32. u32 ctrl;
  33. u32 cfg;
  34. u32 stat;
  35. u32 int_stat;
  36. u32 ien;
  37. u32 isr;
  38. u32 icr;
  39. u32 tac;
  40. u32 tc;
  41. u32 ecc;
  42. u32 dma_data;
  43. };
  44. /* CFG register */
  45. #define CFG_CE_LOW (1 << 5)
  46. #define CFG_DMA_ECC (1 << 4) /* Enable DMA ECC bit */
  47. #define CFG_ECC_EN (1 << 3) /* ECC enable bit */
  48. #define CFG_DMA_BURST (1 << 2) /* DMA burst bit */
  49. #define CFG_DMA_DIR (1 << 1) /* DMA write(0)/read(1) bit */
  50. /* CTRL register */
  51. #define CTRL_SW_RESET (1 << 2)
  52. #define CTRL_ECC_CLEAR (1 << 1) /* Reset ECC bit */
  53. #define CTRL_DMA_START (1 << 0) /* Start DMA channel bit */
  54. /* STAT register */
  55. #define STAT_DMA_FIFO (1 << 2) /* DMA FIFO has data bit */
  56. #define STAT_NAND_READY (1 << 0)
  57. /* INT_STAT register */
  58. #define INT_STAT_TC (1 << 1)
  59. #define INT_STAT_RDY (1 << 0)
  60. /* TAC register bits, be aware of overflows */
  61. #define TAC_W_RDY(n) (max_t(uint32_t, (n), 0xF) << 28)
  62. #define TAC_W_WIDTH(n) (max_t(uint32_t, (n), 0xF) << 24)
  63. #define TAC_W_HOLD(n) (max_t(uint32_t, (n), 0xF) << 20)
  64. #define TAC_W_SETUP(n) (max_t(uint32_t, (n), 0xF) << 16)
  65. #define TAC_R_RDY(n) (max_t(uint32_t, (n), 0xF) << 12)
  66. #define TAC_R_WIDTH(n) (max_t(uint32_t, (n), 0xF) << 8)
  67. #define TAC_R_HOLD(n) (max_t(uint32_t, (n), 0xF) << 4)
  68. #define TAC_R_SETUP(n) (max_t(uint32_t, (n), 0xF) << 0)
  69. /* NAND ECC Layout for small page NAND devices
  70. * Note: For large page devices, the default layouts are used. */
  71. static struct nand_ecclayout lpc32xx_nand_oob_16 = {
  72. .eccbytes = 6,
  73. .eccpos = {10, 11, 12, 13, 14, 15},
  74. .oobfree = {
  75. {.offset = 0,
  76. . length = 4},
  77. {.offset = 6,
  78. . length = 4}
  79. }
  80. };
  81. #if defined(CONFIG_DMA_LPC32XX)
  82. #define ECCSTEPS (CONFIG_SYS_NAND_PAGE_SIZE / CONFIG_SYS_NAND_ECCSIZE)
  83. /*
  84. * DMA Descriptors
  85. * For Large Block: 17 descriptors = ((16 Data and ECC Read) + 1 Spare Area)
  86. * For Small Block: 5 descriptors = ((4 Data and ECC Read) + 1 Spare Area)
  87. */
  88. static struct lpc32xx_dmac_ll dmalist[ECCSTEPS * 2 + 1];
  89. static u32 ecc_buffer[8]; /* MAX ECC size */
  90. static unsigned int dmachan = (unsigned int)-1; /* Invalid channel */
  91. /*
  92. * Helper macro for the DMA client (i.e. NAND SLC):
  93. * - to write the next DMA linked list item address
  94. * (see arch/include/asm/arch-lpc32xx/dma.h).
  95. * - to assign the DMA data register to DMA source or destination address.
  96. * - to assign the ECC register to DMA source or destination address.
  97. */
  98. #define lpc32xx_dmac_next_lli(x) ((u32)x)
  99. #define lpc32xx_dmac_set_dma_data() ((u32)&lpc32xx_nand_slc_regs->dma_data)
  100. #define lpc32xx_dmac_set_ecc() ((u32)&lpc32xx_nand_slc_regs->ecc)
  101. #endif
  102. static struct lpc32xx_nand_slc_regs __iomem *lpc32xx_nand_slc_regs
  103. = (struct lpc32xx_nand_slc_regs __iomem *)SLC_NAND_BASE;
  104. static void lpc32xx_nand_init(void)
  105. {
  106. uint32_t hclk = get_hclk_clk_rate();
  107. /* Reset SLC NAND controller */
  108. writel(CTRL_SW_RESET, &lpc32xx_nand_slc_regs->ctrl);
  109. /* 8-bit bus, no DMA, no ECC, ordinary CE signal */
  110. writel(0, &lpc32xx_nand_slc_regs->cfg);
  111. /* Interrupts disabled and cleared */
  112. writel(0, &lpc32xx_nand_slc_regs->ien);
  113. writel(INT_STAT_TC | INT_STAT_RDY,
  114. &lpc32xx_nand_slc_regs->icr);
  115. /* Configure NAND flash timings */
  116. writel(TAC_W_RDY(CONFIG_LPC32XX_NAND_SLC_WDR_CLKS) |
  117. TAC_W_WIDTH(hclk / CONFIG_LPC32XX_NAND_SLC_WWIDTH) |
  118. TAC_W_HOLD(hclk / CONFIG_LPC32XX_NAND_SLC_WHOLD) |
  119. TAC_W_SETUP(hclk / CONFIG_LPC32XX_NAND_SLC_WSETUP) |
  120. TAC_R_RDY(CONFIG_LPC32XX_NAND_SLC_RDR_CLKS) |
  121. TAC_R_WIDTH(hclk / CONFIG_LPC32XX_NAND_SLC_RWIDTH) |
  122. TAC_R_HOLD(hclk / CONFIG_LPC32XX_NAND_SLC_RHOLD) |
  123. TAC_R_SETUP(hclk / CONFIG_LPC32XX_NAND_SLC_RSETUP),
  124. &lpc32xx_nand_slc_regs->tac);
  125. }
  126. static void lpc32xx_nand_cmd_ctrl(struct mtd_info *mtd,
  127. int cmd, unsigned int ctrl)
  128. {
  129. debug("ctrl: 0x%08x, cmd: 0x%08x\n", ctrl, cmd);
  130. if (ctrl & NAND_NCE)
  131. setbits_le32(&lpc32xx_nand_slc_regs->cfg, CFG_CE_LOW);
  132. else
  133. clrbits_le32(&lpc32xx_nand_slc_regs->cfg, CFG_CE_LOW);
  134. if (cmd == NAND_CMD_NONE)
  135. return;
  136. if (ctrl & NAND_CLE)
  137. writel(cmd & 0xFF, &lpc32xx_nand_slc_regs->cmd);
  138. else if (ctrl & NAND_ALE)
  139. writel(cmd & 0xFF, &lpc32xx_nand_slc_regs->addr);
  140. }
  141. static int lpc32xx_nand_dev_ready(struct mtd_info *mtd)
  142. {
  143. return readl(&lpc32xx_nand_slc_regs->stat) & STAT_NAND_READY;
  144. }
  145. #if defined(CONFIG_DMA_LPC32XX)
  146. /*
  147. * Prepares DMA descriptors for NAND RD/WR operations
  148. * If the size is < 256 Bytes then it is assumed to be
  149. * an OOB transfer
  150. */
  151. static void lpc32xx_nand_dma_configure(struct nand_chip *chip,
  152. const u8 *buffer, int size,
  153. int read)
  154. {
  155. u32 i, dmasrc, ctrl, ecc_ctrl, oob_ctrl, dmadst;
  156. struct lpc32xx_dmac_ll *dmalist_cur;
  157. struct lpc32xx_dmac_ll *dmalist_cur_ecc;
  158. /*
  159. * CTRL descriptor entry for reading ECC
  160. * Copy Multiple times to sync DMA with Flash Controller
  161. */
  162. ecc_ctrl = 0x5 |
  163. DMAC_CHAN_SRC_BURST_1 |
  164. DMAC_CHAN_DEST_BURST_1 |
  165. DMAC_CHAN_SRC_WIDTH_32 |
  166. DMAC_CHAN_DEST_WIDTH_32 |
  167. DMAC_CHAN_DEST_AHB1;
  168. /* CTRL descriptor entry for reading/writing Data */
  169. ctrl = (CONFIG_SYS_NAND_ECCSIZE / 4) |
  170. DMAC_CHAN_SRC_BURST_4 |
  171. DMAC_CHAN_DEST_BURST_4 |
  172. DMAC_CHAN_SRC_WIDTH_32 |
  173. DMAC_CHAN_DEST_WIDTH_32 |
  174. DMAC_CHAN_DEST_AHB1;
  175. /* CTRL descriptor entry for reading/writing Spare Area */
  176. oob_ctrl = (CONFIG_SYS_NAND_OOBSIZE / 4) |
  177. DMAC_CHAN_SRC_BURST_4 |
  178. DMAC_CHAN_DEST_BURST_4 |
  179. DMAC_CHAN_SRC_WIDTH_32 |
  180. DMAC_CHAN_DEST_WIDTH_32 |
  181. DMAC_CHAN_DEST_AHB1;
  182. if (read) {
  183. dmasrc = lpc32xx_dmac_set_dma_data();
  184. dmadst = (u32)buffer;
  185. ctrl |= DMAC_CHAN_DEST_AUTOINC;
  186. } else {
  187. dmadst = lpc32xx_dmac_set_dma_data();
  188. dmasrc = (u32)buffer;
  189. ctrl |= DMAC_CHAN_SRC_AUTOINC;
  190. }
  191. /*
  192. * Write Operation Sequence for Small Block NAND
  193. * ----------------------------------------------------------
  194. * 1. X'fer 256 bytes of data from Memory to Flash.
  195. * 2. Copy generated ECC data from Register to Spare Area
  196. * 3. X'fer next 256 bytes of data from Memory to Flash.
  197. * 4. Copy generated ECC data from Register to Spare Area.
  198. * 5. X'fer 16 byets of Spare area from Memory to Flash.
  199. * Read Operation Sequence for Small Block NAND
  200. * ----------------------------------------------------------
  201. * 1. X'fer 256 bytes of data from Flash to Memory.
  202. * 2. Copy generated ECC data from Register to ECC calc Buffer.
  203. * 3. X'fer next 256 bytes of data from Flash to Memory.
  204. * 4. Copy generated ECC data from Register to ECC calc Buffer.
  205. * 5. X'fer 16 bytes of Spare area from Flash to Memory.
  206. * Write Operation Sequence for Large Block NAND
  207. * ----------------------------------------------------------
  208. * 1. Steps(1-4) of Write Operations repeate for four times
  209. * which generates 16 DMA descriptors to X'fer 2048 bytes of
  210. * data & 32 bytes of ECC data.
  211. * 2. X'fer 64 bytes of Spare area from Memory to Flash.
  212. * Read Operation Sequence for Large Block NAND
  213. * ----------------------------------------------------------
  214. * 1. Steps(1-4) of Read Operations repeate for four times
  215. * which generates 16 DMA descriptors to X'fer 2048 bytes of
  216. * data & 32 bytes of ECC data.
  217. * 2. X'fer 64 bytes of Spare area from Flash to Memory.
  218. */
  219. for (i = 0; i < size/CONFIG_SYS_NAND_ECCSIZE; i++) {
  220. dmalist_cur = &dmalist[i * 2];
  221. dmalist_cur_ecc = &dmalist[(i * 2) + 1];
  222. dmalist_cur->dma_src = (read ? (dmasrc) : (dmasrc + (i*256)));
  223. dmalist_cur->dma_dest = (read ? (dmadst + (i*256)) : dmadst);
  224. dmalist_cur->next_lli = lpc32xx_dmac_next_lli(dmalist_cur_ecc);
  225. dmalist_cur->next_ctrl = ctrl;
  226. dmalist_cur_ecc->dma_src = lpc32xx_dmac_set_ecc();
  227. dmalist_cur_ecc->dma_dest = (u32)&ecc_buffer[i];
  228. dmalist_cur_ecc->next_lli =
  229. lpc32xx_dmac_next_lli(&dmalist[(i * 2) + 2]);
  230. dmalist_cur_ecc->next_ctrl = ecc_ctrl;
  231. }
  232. if (i) { /* Data only transfer */
  233. dmalist_cur_ecc = &dmalist[(i * 2) - 1];
  234. dmalist_cur_ecc->next_lli = 0;
  235. dmalist_cur_ecc->next_ctrl |= DMAC_CHAN_INT_TC_EN;
  236. return;
  237. }
  238. /* OOB only transfer */
  239. if (read) {
  240. dmasrc = lpc32xx_dmac_set_dma_data();
  241. dmadst = (u32)buffer;
  242. oob_ctrl |= DMAC_CHAN_DEST_AUTOINC;
  243. } else {
  244. dmadst = lpc32xx_dmac_set_dma_data();
  245. dmasrc = (u32)buffer;
  246. oob_ctrl |= DMAC_CHAN_SRC_AUTOINC;
  247. }
  248. /* Read/ Write Spare Area Data To/From Flash */
  249. dmalist_cur = &dmalist[i * 2];
  250. dmalist_cur->dma_src = dmasrc;
  251. dmalist_cur->dma_dest = dmadst;
  252. dmalist_cur->next_lli = 0;
  253. dmalist_cur->next_ctrl = (oob_ctrl | DMAC_CHAN_INT_TC_EN);
  254. }
  255. static void lpc32xx_nand_xfer(struct mtd_info *mtd, const u8 *buf,
  256. int len, int read)
  257. {
  258. struct nand_chip *chip = mtd_to_nand(mtd);
  259. u32 config;
  260. int ret;
  261. /* DMA Channel Configuration */
  262. config = (read ? DMAC_CHAN_FLOW_D_P2M : DMAC_CHAN_FLOW_D_M2P) |
  263. (read ? DMAC_DEST_PERIP(0) : DMAC_DEST_PERIP(DMA_PERID_NAND1)) |
  264. (read ? DMAC_SRC_PERIP(DMA_PERID_NAND1) : DMAC_SRC_PERIP(0)) |
  265. DMAC_CHAN_ENABLE;
  266. /* Prepare DMA descriptors */
  267. lpc32xx_nand_dma_configure(chip, buf, len, read);
  268. /* Setup SLC controller and start transfer */
  269. if (read)
  270. setbits_le32(&lpc32xx_nand_slc_regs->cfg, CFG_DMA_DIR);
  271. else /* NAND_ECC_WRITE */
  272. clrbits_le32(&lpc32xx_nand_slc_regs->cfg, CFG_DMA_DIR);
  273. setbits_le32(&lpc32xx_nand_slc_regs->cfg, CFG_DMA_BURST);
  274. /* Write length for new transfers */
  275. if (!((readl(&lpc32xx_nand_slc_regs->stat) & STAT_DMA_FIFO) |
  276. readl(&lpc32xx_nand_slc_regs->tc))) {
  277. int tmp = (len != mtd->oobsize) ? mtd->oobsize : 0;
  278. writel(len + tmp, &lpc32xx_nand_slc_regs->tc);
  279. }
  280. setbits_le32(&lpc32xx_nand_slc_regs->ctrl, CTRL_DMA_START);
  281. /* Start DMA transfers */
  282. ret = lpc32xx_dma_start_xfer(dmachan, dmalist, config);
  283. if (unlikely(ret < 0))
  284. BUG();
  285. /* Wait for NAND to be ready */
  286. while (!lpc32xx_nand_dev_ready(mtd))
  287. ;
  288. /* Wait till DMA transfer is DONE */
  289. if (lpc32xx_dma_wait_status(dmachan))
  290. pr_err("NAND DMA transfer error!\r\n");
  291. /* Stop DMA & HW ECC */
  292. clrbits_le32(&lpc32xx_nand_slc_regs->ctrl, CTRL_DMA_START);
  293. clrbits_le32(&lpc32xx_nand_slc_regs->cfg,
  294. CFG_DMA_DIR | CFG_DMA_BURST | CFG_ECC_EN | CFG_DMA_ECC);
  295. }
  296. static u32 slc_ecc_copy_to_buffer(u8 *spare, const u32 *ecc, int count)
  297. {
  298. int i;
  299. for (i = 0; i < (count * CONFIG_SYS_NAND_ECCBYTES);
  300. i += CONFIG_SYS_NAND_ECCBYTES) {
  301. u32 ce = ecc[i / CONFIG_SYS_NAND_ECCBYTES];
  302. ce = ~(ce << 2) & 0xFFFFFF;
  303. spare[i+2] = (u8)(ce & 0xFF); ce >>= 8;
  304. spare[i+1] = (u8)(ce & 0xFF); ce >>= 8;
  305. spare[i] = (u8)(ce & 0xFF);
  306. }
  307. return 0;
  308. }
  309. static int lpc32xx_ecc_calculate(struct mtd_info *mtd, const uint8_t *dat,
  310. uint8_t *ecc_code)
  311. {
  312. return slc_ecc_copy_to_buffer(ecc_code, ecc_buffer, ECCSTEPS);
  313. }
  314. /*
  315. * Enables and prepares SLC NAND controller
  316. * for doing data transfers with H/W ECC enabled.
  317. */
  318. static void lpc32xx_hwecc_enable(struct mtd_info *mtd, int mode)
  319. {
  320. /* Clear ECC */
  321. writel(CTRL_ECC_CLEAR, &lpc32xx_nand_slc_regs->ctrl);
  322. /* Setup SLC controller for H/W ECC operations */
  323. setbits_le32(&lpc32xx_nand_slc_regs->cfg, CFG_ECC_EN | CFG_DMA_ECC);
  324. }
  325. /*
  326. * lpc32xx_correct_data - [NAND Interface] Detect and correct bit error(s)
  327. * mtd: MTD block structure
  328. * dat: raw data read from the chip
  329. * read_ecc: ECC from the chip
  330. * calc_ecc: the ECC calculated from raw data
  331. *
  332. * Detect and correct a 1 bit error for 256 byte block
  333. */
  334. int lpc32xx_correct_data(struct mtd_info *mtd, u_char *dat,
  335. u_char *read_ecc, u_char *calc_ecc)
  336. {
  337. unsigned int i;
  338. int ret1, ret2 = 0;
  339. u_char *r = read_ecc;
  340. u_char *c = calc_ecc;
  341. u16 data_offset = 0;
  342. for (i = 0 ; i < ECCSTEPS ; i++) {
  343. r += CONFIG_SYS_NAND_ECCBYTES;
  344. c += CONFIG_SYS_NAND_ECCBYTES;
  345. data_offset += CONFIG_SYS_NAND_ECCSIZE;
  346. ret1 = nand_correct_data(mtd, dat + data_offset, r, c);
  347. if (ret1 < 0)
  348. return -EBADMSG;
  349. else
  350. ret2 += ret1;
  351. }
  352. return ret2;
  353. }
  354. #endif
  355. #if defined(CONFIG_DMA_LPC32XX)
  356. static void lpc32xx_dma_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
  357. {
  358. lpc32xx_nand_xfer(mtd, buf, len, 1);
  359. }
  360. #else
  361. static void lpc32xx_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
  362. {
  363. while (len-- > 0)
  364. *buf++ = readl(&lpc32xx_nand_slc_regs->data);
  365. }
  366. #endif
  367. static uint8_t lpc32xx_read_byte(struct mtd_info *mtd)
  368. {
  369. return readl(&lpc32xx_nand_slc_regs->data);
  370. }
  371. #if defined(CONFIG_DMA_LPC32XX)
  372. static void lpc32xx_dma_write_buf(struct mtd_info *mtd, const uint8_t *buf,
  373. int len)
  374. {
  375. lpc32xx_nand_xfer(mtd, buf, len, 0);
  376. }
  377. #else
  378. static void lpc32xx_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
  379. {
  380. while (len-- > 0)
  381. writel(*buf++, &lpc32xx_nand_slc_regs->data);
  382. }
  383. #endif
  384. static void lpc32xx_write_byte(struct mtd_info *mtd, uint8_t byte)
  385. {
  386. writel(byte, &lpc32xx_nand_slc_regs->data);
  387. }
  388. #if defined(CONFIG_DMA_LPC32XX)
  389. /* Reuse the logic from "nand_read_page_hwecc()" */
  390. static int lpc32xx_read_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
  391. uint8_t *buf, int oob_required, int page)
  392. {
  393. int i;
  394. int stat;
  395. uint8_t *p = buf;
  396. uint8_t *ecc_calc = chip->buffers->ecccalc;
  397. uint8_t *ecc_code = chip->buffers->ecccode;
  398. uint32_t *eccpos = chip->ecc.layout->eccpos;
  399. unsigned int max_bitflips = 0;
  400. /*
  401. * As per the "LPC32x0 and LPC32x0/01 User manual" table 173 notes
  402. * and section 9.7, the NAND SLC & DMA allowed single DMA transaction
  403. * of a page size using DMA controller scatter/gather mode through
  404. * linked list; the ECC read is done without any software intervention.
  405. */
  406. lpc32xx_hwecc_enable(mtd, NAND_ECC_READ);
  407. lpc32xx_dma_read_buf(mtd, p, chip->ecc.size * chip->ecc.steps);
  408. lpc32xx_ecc_calculate(mtd, p, &ecc_calc[0]);
  409. lpc32xx_dma_read_buf(mtd, chip->oob_poi, mtd->oobsize);
  410. for (i = 0; i < chip->ecc.total; i++)
  411. ecc_code[i] = chip->oob_poi[eccpos[i]];
  412. stat = chip->ecc.correct(mtd, p, &ecc_code[0], &ecc_calc[0]);
  413. if (stat < 0)
  414. mtd->ecc_stats.failed++;
  415. else {
  416. mtd->ecc_stats.corrected += stat;
  417. max_bitflips = max_t(unsigned int, max_bitflips, stat);
  418. }
  419. return max_bitflips;
  420. }
  421. /* Reuse the logic from "nand_write_page_hwecc()" */
  422. static int lpc32xx_write_page_hwecc(struct mtd_info *mtd,
  423. struct nand_chip *chip,
  424. const uint8_t *buf, int oob_required)
  425. {
  426. int i;
  427. uint8_t *ecc_calc = chip->buffers->ecccalc;
  428. const uint8_t *p = buf;
  429. uint32_t *eccpos = chip->ecc.layout->eccpos;
  430. /*
  431. * As per the "LPC32x0 and LPC32x0/01 User manual" table 173 notes
  432. * and section 9.7, the NAND SLC & DMA allowed single DMA transaction
  433. * of a page size using DMA controller scatter/gather mode through
  434. * linked list; the ECC read is done without any software intervention.
  435. */
  436. lpc32xx_hwecc_enable(mtd, NAND_ECC_WRITE);
  437. lpc32xx_dma_write_buf(mtd, p, chip->ecc.size * chip->ecc.steps);
  438. lpc32xx_ecc_calculate(mtd, p, &ecc_calc[0]);
  439. for (i = 0; i < chip->ecc.total; i++)
  440. chip->oob_poi[eccpos[i]] = ecc_calc[i];
  441. lpc32xx_dma_write_buf(mtd, chip->oob_poi, mtd->oobsize);
  442. return 0;
  443. }
  444. #endif
  445. /*
  446. * LPC32xx has only one SLC NAND controller, don't utilize
  447. * CONFIG_SYS_NAND_SELF_INIT to be able to reuse this function
  448. * both in SPL NAND and U-Boot images.
  449. */
  450. int board_nand_init(struct nand_chip *lpc32xx_chip)
  451. {
  452. #if defined(CONFIG_DMA_LPC32XX)
  453. int ret;
  454. /* Acquire a channel for our use */
  455. ret = lpc32xx_dma_get_channel();
  456. if (unlikely(ret < 0)) {
  457. pr_info("Unable to get free DMA channel for NAND transfers\n");
  458. return -1;
  459. }
  460. dmachan = (unsigned int)ret;
  461. #endif
  462. lpc32xx_chip->cmd_ctrl = lpc32xx_nand_cmd_ctrl;
  463. lpc32xx_chip->dev_ready = lpc32xx_nand_dev_ready;
  464. /*
  465. * The implementation of these functions is quite common, but
  466. * they MUST be defined, because access to data register
  467. * is strictly 32-bit aligned.
  468. */
  469. lpc32xx_chip->read_byte = lpc32xx_read_byte;
  470. lpc32xx_chip->write_byte = lpc32xx_write_byte;
  471. #if defined(CONFIG_DMA_LPC32XX)
  472. /* Hardware ECC calculation is supported when DMA driver is selected */
  473. lpc32xx_chip->ecc.mode = NAND_ECC_HW;
  474. lpc32xx_chip->read_buf = lpc32xx_dma_read_buf;
  475. lpc32xx_chip->write_buf = lpc32xx_dma_write_buf;
  476. lpc32xx_chip->ecc.calculate = lpc32xx_ecc_calculate;
  477. lpc32xx_chip->ecc.correct = lpc32xx_correct_data;
  478. lpc32xx_chip->ecc.hwctl = lpc32xx_hwecc_enable;
  479. lpc32xx_chip->chip_delay = 2000;
  480. lpc32xx_chip->ecc.read_page = lpc32xx_read_page_hwecc;
  481. lpc32xx_chip->ecc.write_page = lpc32xx_write_page_hwecc;
  482. lpc32xx_chip->options |= NAND_NO_SUBPAGE_WRITE;
  483. #else
  484. /*
  485. * Hardware ECC calculation is not supported by the driver,
  486. * because it requires DMA support, see LPC32x0 User Manual,
  487. * note after SLC_ECC register description (UM10326, p.198)
  488. */
  489. lpc32xx_chip->ecc.mode = NAND_ECC_SOFT;
  490. /*
  491. * The implementation of these functions is quite common, but
  492. * they MUST be defined, because access to data register
  493. * is strictly 32-bit aligned.
  494. */
  495. lpc32xx_chip->read_buf = lpc32xx_read_buf;
  496. lpc32xx_chip->write_buf = lpc32xx_write_buf;
  497. #endif
  498. /*
  499. * These values are predefined
  500. * for both small and large page NAND flash devices.
  501. */
  502. lpc32xx_chip->ecc.size = CONFIG_SYS_NAND_ECCSIZE;
  503. lpc32xx_chip->ecc.bytes = CONFIG_SYS_NAND_ECCBYTES;
  504. lpc32xx_chip->ecc.strength = 1;
  505. if (CONFIG_SYS_NAND_PAGE_SIZE != NAND_LARGE_BLOCK_PAGE_SIZE)
  506. lpc32xx_chip->ecc.layout = &lpc32xx_nand_oob_16;
  507. #if defined(CONFIG_SYS_NAND_USE_FLASH_BBT)
  508. lpc32xx_chip->bbt_options |= NAND_BBT_USE_FLASH;
  509. #endif
  510. /* Initialize NAND interface */
  511. lpc32xx_nand_init();
  512. return 0;
  513. }