kirkwood_nand.c 1.9 KB

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  1. /*
  2. * (C) Copyright 2009
  3. * Marvell Semiconductor <www.marvell.com>
  4. * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
  5. *
  6. * SPDX-License-Identifier: GPL-2.0+
  7. */
  8. #include <common.h>
  9. #include <asm/io.h>
  10. #include <asm/arch/soc.h>
  11. #include <asm/arch/mpp.h>
  12. #include <nand.h>
  13. /* NAND Flash Soc registers */
  14. struct kwnandf_registers {
  15. u32 rd_params; /* 0x10418 */
  16. u32 wr_param; /* 0x1041c */
  17. u8 pad[0x10470 - 0x1041c - 4];
  18. u32 ctrl; /* 0x10470 */
  19. };
  20. static struct kwnandf_registers *nf_reg =
  21. (struct kwnandf_registers *)KW_NANDF_BASE;
  22. static u32 nand_mpp_backup[9] = { 0 };
  23. /*
  24. * hardware specific access to control-lines/bits
  25. */
  26. #define NAND_ACTCEBOOT_BIT 0x02
  27. static void kw_nand_hwcontrol(struct mtd_info *mtd, int cmd,
  28. unsigned int ctrl)
  29. {
  30. struct nand_chip *nc = mtd_to_nand(mtd);
  31. u32 offs;
  32. if (cmd == NAND_CMD_NONE)
  33. return;
  34. if (ctrl & NAND_CLE)
  35. offs = (1 << 0); /* Commands with A[1:0] == 01 */
  36. else if (ctrl & NAND_ALE)
  37. offs = (1 << 1); /* Addresses with A[1:0] == 10 */
  38. else
  39. return;
  40. writeb(cmd, nc->IO_ADDR_W + offs);
  41. }
  42. void kw_nand_select_chip(struct mtd_info *mtd, int chip)
  43. {
  44. u32 data;
  45. static const u32 nand_config[] = {
  46. MPP0_NF_IO2,
  47. MPP1_NF_IO3,
  48. MPP2_NF_IO4,
  49. MPP3_NF_IO5,
  50. MPP4_NF_IO6,
  51. MPP5_NF_IO7,
  52. MPP18_NF_IO0,
  53. MPP19_NF_IO1,
  54. 0
  55. };
  56. if (chip >= 0)
  57. kirkwood_mpp_conf(nand_config, nand_mpp_backup);
  58. else
  59. kirkwood_mpp_conf(nand_mpp_backup, NULL);
  60. data = readl(&nf_reg->ctrl);
  61. data |= NAND_ACTCEBOOT_BIT;
  62. writel(data, &nf_reg->ctrl);
  63. }
  64. int board_nand_init(struct nand_chip *nand)
  65. {
  66. nand->options = NAND_COPYBACK | NAND_CACHEPRG | NAND_NO_PADDING;
  67. #if defined(CONFIG_SYS_NAND_NO_SUBPAGE_WRITE)
  68. nand->options |= NAND_NO_SUBPAGE_WRITE;
  69. #endif
  70. #if defined(CONFIG_NAND_ECC_BCH)
  71. nand->ecc.mode = NAND_ECC_SOFT_BCH;
  72. #else
  73. nand->ecc.mode = NAND_ECC_SOFT;
  74. #endif
  75. nand->cmd_ctrl = kw_nand_hwcontrol;
  76. nand->chip_delay = 40;
  77. nand->select_chip = kw_nand_select_chip;
  78. return 0;
  79. }