kb9202_nand.c 3.9 KB

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  1. /*
  2. * (C) Copyright 2006
  3. * KwikByte <kb9200_dev@kwikbyte.com>
  4. *
  5. * (C) Copyright 2009
  6. * Matthias Kaehlcke <matthias@kaehlcke.net>
  7. *
  8. * SPDX-License-Identifier: GPL-2.0+
  9. */
  10. #include <common.h>
  11. #include <asm/io.h>
  12. #include <asm/arch/AT91RM9200.h>
  13. #include <asm/arch/hardware.h>
  14. #include <nand.h>
  15. /*
  16. * hardware specific access to control-lines
  17. */
  18. #define MASK_ALE (1 << 22) /* our ALE is A22 */
  19. #define MASK_CLE (1 << 21) /* our CLE is A21 */
  20. #define KB9202_NAND_NCE (1 << 28) /* EN* on D28 */
  21. #define KB9202_NAND_BUSY (1 << 29) /* RB* on D29 */
  22. #define KB9202_SMC2_NWS (1 << 2)
  23. #define KB9202_SMC2_TDF (1 << 8)
  24. #define KB9202_SMC2_RWSETUP (1 << 24)
  25. #define KB9202_SMC2_RWHOLD (1 << 29)
  26. /*
  27. * Board-specific function to access device control signals
  28. */
  29. static void kb9202_nand_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl)
  30. {
  31. struct nand_chip *this = mtd_to_nand(mtd);
  32. if (ctrl & NAND_CTRL_CHANGE) {
  33. ulong IO_ADDR_W = (ulong) this->IO_ADDR_W;
  34. /* clear ALE and CLE bits */
  35. IO_ADDR_W &= ~(MASK_ALE | MASK_CLE);
  36. if (ctrl & NAND_CLE)
  37. IO_ADDR_W |= MASK_CLE;
  38. if (ctrl & NAND_ALE)
  39. IO_ADDR_W |= MASK_ALE;
  40. this->IO_ADDR_W = (void *) IO_ADDR_W;
  41. if (ctrl & NAND_NCE)
  42. writel(KB9202_NAND_NCE, AT91C_PIOC_CODR);
  43. else
  44. writel(KB9202_NAND_NCE, AT91C_PIOC_SODR);
  45. }
  46. if (cmd != NAND_CMD_NONE)
  47. writeb(cmd, this->IO_ADDR_W);
  48. }
  49. /*
  50. * Board-specific function to access the device ready signal.
  51. */
  52. static int kb9202_nand_ready(struct mtd_info *mtd)
  53. {
  54. return readl(AT91C_PIOC_PDSR) & KB9202_NAND_BUSY;
  55. }
  56. /*
  57. * Board-specific NAND init. Copied from include/linux/mtd/nand.h for reference.
  58. *
  59. * struct nand_chip - NAND Private Flash Chip Data
  60. * @IO_ADDR_R: [BOARDSPECIFIC] address to read the 8 I/O lines of the flash device
  61. * @IO_ADDR_W: [BOARDSPECIFIC] address to write the 8 I/O lines of the flash device
  62. * @hwcontrol: [BOARDSPECIFIC] hardwarespecific function for accesing control-lines
  63. * @dev_ready: [BOARDSPECIFIC] hardwarespecific function for accesing device ready/busy line
  64. * If set to NULL no access to ready/busy is available and the ready/busy information
  65. * is read from the chip status register
  66. * @enable_hwecc: [BOARDSPECIFIC] function to enable (reset) hardware ecc generator. Must only
  67. * be provided if a hardware ECC is available
  68. * @eccmode: [BOARDSPECIFIC] mode of ecc, see defines
  69. * @chip_delay: [BOARDSPECIFIC] chip dependent delay for transfering data from array to read regs (tR)
  70. * @options: [BOARDSPECIFIC] various chip options. They can partly be set to inform nand_scan about
  71. * special functionality. See the defines for further explanation
  72. */
  73. /*
  74. * This routine initializes controller and GPIOs.
  75. */
  76. int board_nand_init(struct nand_chip *nand)
  77. {
  78. unsigned int value;
  79. nand->ecc.mode = NAND_ECC_SOFT;
  80. nand->cmd_ctrl = kb9202_nand_hwcontrol;
  81. nand->dev_ready = kb9202_nand_ready;
  82. /* in case running outside of bootloader */
  83. writel(1 << AT91C_ID_PIOC, AT91C_PMC_PCER);
  84. /* setup nand flash access (allow ample margin) */
  85. /* 4 wait states, 1 setup, 1 hold, 1 float for 8-bit device */
  86. writel(AT91C_SMC2_WSEN | KB9202_SMC2_NWS | KB9202_SMC2_TDF |
  87. AT91C_SMC2_DBW_8 | KB9202_SMC2_RWSETUP | KB9202_SMC2_RWHOLD,
  88. AT91C_SMC_CSR3);
  89. /* enable internal NAND controller */
  90. value = readl(AT91C_EBI_CSA);
  91. value |= AT91C_EBI_CS3A_SMC_SmartMedia;
  92. writel(value, AT91C_EBI_CSA);
  93. /* enable SMOE/SMWE */
  94. writel(AT91C_PC1_BFRDY_SMOE | AT91C_PC3_BFBAA_SMWE, AT91C_PIOC_ASR);
  95. writel(AT91C_PC1_BFRDY_SMOE | AT91C_PC3_BFBAA_SMWE, AT91C_PIOC_PDR);
  96. writel(AT91C_PC1_BFRDY_SMOE | AT91C_PC3_BFBAA_SMWE, AT91C_PIOC_OER);
  97. /* set NCE to high */
  98. writel(KB9202_NAND_NCE, AT91C_PIOC_SODR);
  99. /* disable output on pin connected to the busy line of the NAND */
  100. writel(KB9202_NAND_BUSY, AT91C_PIOC_ODR);
  101. /* enable the PIO to control NCE and BUSY */
  102. writel(KB9202_NAND_NCE | KB9202_NAND_BUSY, AT91C_PIOC_PER);
  103. /* enable output for NCE */
  104. writel(KB9202_NAND_NCE, AT91C_PIOC_OER);
  105. return (0);
  106. }