fsl_ifc_nand.c 29 KB

1234567891011121314151617181920212223242526272829303132333435363738394041424344454647484950515253545556575859606162636465666768697071727374757677787980818283848586878889909192939495969798991001011021031041051061071081091101111121131141151161171181191201211221231241251261271281291301311321331341351361371381391401411421431441451461471481491501511521531541551561571581591601611621631641651661671681691701711721731741751761771781791801811821831841851861871881891901911921931941951961971981992002012022032042052062072082092102112122132142152162172182192202212222232242252262272282292302312322332342352362372382392402412422432442452462472482492502512522532542552562572582592602612622632642652662672682692702712722732742752762772782792802812822832842852862872882892902912922932942952962972982993003013023033043053063073083093103113123133143153163173183193203213223233243253263273283293303313323333343353363373383393403413423433443453463473483493503513523533543553563573583593603613623633643653663673683693703713723733743753763773783793803813823833843853863873883893903913923933943953963973983994004014024034044054064074084094104114124134144154164174184194204214224234244254264274284294304314324334344354364374384394404414424434444454464474484494504514524534544554564574584594604614624634644654664674684694704714724734744754764774784794804814824834844854864874884894904914924934944954964974984995005015025035045055065075085095105115125135145155165175185195205215225235245255265275285295305315325335345355365375385395405415425435445455465475485495505515525535545555565575585595605615625635645655665675685695705715725735745755765775785795805815825835845855865875885895905915925935945955965975985996006016026036046056066076086096106116126136146156166176186196206216226236246256266276286296306316326336346356366376386396406416426436446456466476486496506516526536546556566576586596606616626636646656666676686696706716726736746756766776786796806816826836846856866876886896906916926936946956966976986997007017027037047057067077087097107117127137147157167177187197207217227237247257267277287297307317327337347357367377387397407417427437447457467477487497507517527537547557567577587597607617627637647657667677687697707717727737747757767777787797807817827837847857867877887897907917927937947957967977987998008018028038048058068078088098108118128138148158168178188198208218228238248258268278288298308318328338348358368378388398408418428438448458468478488498508518528538548558568578588598608618628638648658668678688698708718728738748758768778788798808818828838848858868878888898908918928938948958968978988999009019029039049059069079089099109119129139149159169179189199209219229239249259269279289299309319329339349359369379389399409419429439449459469479489499509519529539549559569579589599609619629639649659669679689699709719729739749759769779789799809819829839849859869879889899909919929939949959969979989991000100110021003100410051006100710081009101010111012101310141015101610171018101910201021102210231024102510261027102810291030103110321033103410351036103710381039104010411042104310441045104610471048104910501051105210531054105510561057105810591060106110621063106410651066
  1. /* Integrated Flash Controller NAND Machine Driver
  2. *
  3. * Copyright (c) 2012 Freescale Semiconductor, Inc
  4. *
  5. * Authors: Dipen Dudhat <Dipen.Dudhat@freescale.com>
  6. *
  7. * SPDX-License-Identifier: GPL-2.0+
  8. */
  9. #include <common.h>
  10. #include <malloc.h>
  11. #include <nand.h>
  12. #include <linux/mtd/mtd.h>
  13. #include <linux/mtd/nand.h>
  14. #include <linux/mtd/nand_ecc.h>
  15. #include <asm/io.h>
  16. #include <asm/errno.h>
  17. #include <fsl_ifc.h>
  18. #ifndef CONFIG_SYS_FSL_IFC_BANK_COUNT
  19. #define CONFIG_SYS_FSL_IFC_BANK_COUNT 4
  20. #endif
  21. #define MAX_BANKS CONFIG_SYS_FSL_IFC_BANK_COUNT
  22. #define ERR_BYTE 0xFF /* Value returned for read bytes
  23. when read failed */
  24. struct fsl_ifc_ctrl;
  25. /* mtd information per set */
  26. struct fsl_ifc_mtd {
  27. struct nand_chip chip;
  28. struct fsl_ifc_ctrl *ctrl;
  29. struct device *dev;
  30. int bank; /* Chip select bank number */
  31. unsigned int bufnum_mask; /* bufnum = page & bufnum_mask */
  32. u8 __iomem *vbase; /* Chip select base virtual address */
  33. };
  34. /* overview of the fsl ifc controller */
  35. struct fsl_ifc_ctrl {
  36. struct nand_hw_control controller;
  37. struct fsl_ifc_mtd *chips[MAX_BANKS];
  38. /* device info */
  39. struct fsl_ifc regs;
  40. void __iomem *addr; /* Address of assigned IFC buffer */
  41. unsigned int cs_nand; /* On which chipsel NAND is connected */
  42. unsigned int page; /* Last page written to / read from */
  43. unsigned int read_bytes; /* Number of bytes read during command */
  44. unsigned int column; /* Saved column from SEQIN */
  45. unsigned int index; /* Pointer to next byte to 'read' */
  46. unsigned int status; /* status read from NEESR after last op */
  47. unsigned int oob; /* Non zero if operating on OOB data */
  48. unsigned int eccread; /* Non zero for a full-page ECC read */
  49. };
  50. static struct fsl_ifc_ctrl *ifc_ctrl;
  51. /* 512-byte page with 4-bit ECC, 8-bit */
  52. static struct nand_ecclayout oob_512_8bit_ecc4 = {
  53. .eccbytes = 8,
  54. .eccpos = {8, 9, 10, 11, 12, 13, 14, 15},
  55. .oobfree = { {0, 5}, {6, 2} },
  56. };
  57. /* 512-byte page with 4-bit ECC, 16-bit */
  58. static struct nand_ecclayout oob_512_16bit_ecc4 = {
  59. .eccbytes = 8,
  60. .eccpos = {8, 9, 10, 11, 12, 13, 14, 15},
  61. .oobfree = { {2, 6}, },
  62. };
  63. /* 2048-byte page size with 4-bit ECC */
  64. static struct nand_ecclayout oob_2048_ecc4 = {
  65. .eccbytes = 32,
  66. .eccpos = {
  67. 8, 9, 10, 11, 12, 13, 14, 15,
  68. 16, 17, 18, 19, 20, 21, 22, 23,
  69. 24, 25, 26, 27, 28, 29, 30, 31,
  70. 32, 33, 34, 35, 36, 37, 38, 39,
  71. },
  72. .oobfree = { {2, 6}, {40, 24} },
  73. };
  74. /* 4096-byte page size with 4-bit ECC */
  75. static struct nand_ecclayout oob_4096_ecc4 = {
  76. .eccbytes = 64,
  77. .eccpos = {
  78. 8, 9, 10, 11, 12, 13, 14, 15,
  79. 16, 17, 18, 19, 20, 21, 22, 23,
  80. 24, 25, 26, 27, 28, 29, 30, 31,
  81. 32, 33, 34, 35, 36, 37, 38, 39,
  82. 40, 41, 42, 43, 44, 45, 46, 47,
  83. 48, 49, 50, 51, 52, 53, 54, 55,
  84. 56, 57, 58, 59, 60, 61, 62, 63,
  85. 64, 65, 66, 67, 68, 69, 70, 71,
  86. },
  87. .oobfree = { {2, 6}, {72, 56} },
  88. };
  89. /* 4096-byte page size with 8-bit ECC -- requires 218-byte OOB */
  90. static struct nand_ecclayout oob_4096_ecc8 = {
  91. .eccbytes = 128,
  92. .eccpos = {
  93. 8, 9, 10, 11, 12, 13, 14, 15,
  94. 16, 17, 18, 19, 20, 21, 22, 23,
  95. 24, 25, 26, 27, 28, 29, 30, 31,
  96. 32, 33, 34, 35, 36, 37, 38, 39,
  97. 40, 41, 42, 43, 44, 45, 46, 47,
  98. 48, 49, 50, 51, 52, 53, 54, 55,
  99. 56, 57, 58, 59, 60, 61, 62, 63,
  100. 64, 65, 66, 67, 68, 69, 70, 71,
  101. 72, 73, 74, 75, 76, 77, 78, 79,
  102. 80, 81, 82, 83, 84, 85, 86, 87,
  103. 88, 89, 90, 91, 92, 93, 94, 95,
  104. 96, 97, 98, 99, 100, 101, 102, 103,
  105. 104, 105, 106, 107, 108, 109, 110, 111,
  106. 112, 113, 114, 115, 116, 117, 118, 119,
  107. 120, 121, 122, 123, 124, 125, 126, 127,
  108. 128, 129, 130, 131, 132, 133, 134, 135,
  109. },
  110. .oobfree = { {2, 6}, {136, 82} },
  111. };
  112. /* 8192-byte page size with 4-bit ECC */
  113. static struct nand_ecclayout oob_8192_ecc4 = {
  114. .eccbytes = 128,
  115. .eccpos = {
  116. 8, 9, 10, 11, 12, 13, 14, 15,
  117. 16, 17, 18, 19, 20, 21, 22, 23,
  118. 24, 25, 26, 27, 28, 29, 30, 31,
  119. 32, 33, 34, 35, 36, 37, 38, 39,
  120. 40, 41, 42, 43, 44, 45, 46, 47,
  121. 48, 49, 50, 51, 52, 53, 54, 55,
  122. 56, 57, 58, 59, 60, 61, 62, 63,
  123. 64, 65, 66, 67, 68, 69, 70, 71,
  124. 72, 73, 74, 75, 76, 77, 78, 79,
  125. 80, 81, 82, 83, 84, 85, 86, 87,
  126. 88, 89, 90, 91, 92, 93, 94, 95,
  127. 96, 97, 98, 99, 100, 101, 102, 103,
  128. 104, 105, 106, 107, 108, 109, 110, 111,
  129. 112, 113, 114, 115, 116, 117, 118, 119,
  130. 120, 121, 122, 123, 124, 125, 126, 127,
  131. 128, 129, 130, 131, 132, 133, 134, 135,
  132. },
  133. .oobfree = { {2, 6}, {136, 208} },
  134. };
  135. /* 8192-byte page size with 8-bit ECC -- requires 218-byte OOB */
  136. static struct nand_ecclayout oob_8192_ecc8 = {
  137. .eccbytes = 256,
  138. .eccpos = {
  139. 8, 9, 10, 11, 12, 13, 14, 15,
  140. 16, 17, 18, 19, 20, 21, 22, 23,
  141. 24, 25, 26, 27, 28, 29, 30, 31,
  142. 32, 33, 34, 35, 36, 37, 38, 39,
  143. 40, 41, 42, 43, 44, 45, 46, 47,
  144. 48, 49, 50, 51, 52, 53, 54, 55,
  145. 56, 57, 58, 59, 60, 61, 62, 63,
  146. 64, 65, 66, 67, 68, 69, 70, 71,
  147. 72, 73, 74, 75, 76, 77, 78, 79,
  148. 80, 81, 82, 83, 84, 85, 86, 87,
  149. 88, 89, 90, 91, 92, 93, 94, 95,
  150. 96, 97, 98, 99, 100, 101, 102, 103,
  151. 104, 105, 106, 107, 108, 109, 110, 111,
  152. 112, 113, 114, 115, 116, 117, 118, 119,
  153. 120, 121, 122, 123, 124, 125, 126, 127,
  154. 128, 129, 130, 131, 132, 133, 134, 135,
  155. 136, 137, 138, 139, 140, 141, 142, 143,
  156. 144, 145, 146, 147, 148, 149, 150, 151,
  157. 152, 153, 154, 155, 156, 157, 158, 159,
  158. 160, 161, 162, 163, 164, 165, 166, 167,
  159. 168, 169, 170, 171, 172, 173, 174, 175,
  160. 176, 177, 178, 179, 180, 181, 182, 183,
  161. 184, 185, 186, 187, 188, 189, 190, 191,
  162. 192, 193, 194, 195, 196, 197, 198, 199,
  163. 200, 201, 202, 203, 204, 205, 206, 207,
  164. 208, 209, 210, 211, 212, 213, 214, 215,
  165. 216, 217, 218, 219, 220, 221, 222, 223,
  166. 224, 225, 226, 227, 228, 229, 230, 231,
  167. 232, 233, 234, 235, 236, 237, 238, 239,
  168. 240, 241, 242, 243, 244, 245, 246, 247,
  169. 248, 249, 250, 251, 252, 253, 254, 255,
  170. 256, 257, 258, 259, 260, 261, 262, 263,
  171. },
  172. .oobfree = { {2, 6}, {264, 80} },
  173. };
  174. /*
  175. * Generic flash bbt descriptors
  176. */
  177. static u8 bbt_pattern[] = {'B', 'b', 't', '0' };
  178. static u8 mirror_pattern[] = {'1', 't', 'b', 'B' };
  179. static struct nand_bbt_descr bbt_main_descr = {
  180. .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE |
  181. NAND_BBT_2BIT | NAND_BBT_VERSION,
  182. .offs = 2, /* 0 on 8-bit small page */
  183. .len = 4,
  184. .veroffs = 6,
  185. .maxblocks = 4,
  186. .pattern = bbt_pattern,
  187. };
  188. static struct nand_bbt_descr bbt_mirror_descr = {
  189. .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE |
  190. NAND_BBT_2BIT | NAND_BBT_VERSION,
  191. .offs = 2, /* 0 on 8-bit small page */
  192. .len = 4,
  193. .veroffs = 6,
  194. .maxblocks = 4,
  195. .pattern = mirror_pattern,
  196. };
  197. /*
  198. * Set up the IFC hardware block and page address fields, and the ifc nand
  199. * structure addr field to point to the correct IFC buffer in memory
  200. */
  201. static void set_addr(struct mtd_info *mtd, int column, int page_addr, int oob)
  202. {
  203. struct nand_chip *chip = mtd_to_nand(mtd);
  204. struct fsl_ifc_mtd *priv = nand_get_controller_data(chip);
  205. struct fsl_ifc_ctrl *ctrl = priv->ctrl;
  206. struct fsl_ifc_runtime *ifc = ctrl->regs.rregs;
  207. int buf_num;
  208. ctrl->page = page_addr;
  209. /* Program ROW0/COL0 */
  210. ifc_out32(&ifc->ifc_nand.row0, page_addr);
  211. ifc_out32(&ifc->ifc_nand.col0, (oob ? IFC_NAND_COL_MS : 0) | column);
  212. buf_num = page_addr & priv->bufnum_mask;
  213. ctrl->addr = priv->vbase + buf_num * (mtd->writesize * 2);
  214. ctrl->index = column;
  215. /* for OOB data point to the second half of the buffer */
  216. if (oob)
  217. ctrl->index += mtd->writesize;
  218. }
  219. static int is_blank(struct mtd_info *mtd, struct fsl_ifc_ctrl *ctrl,
  220. unsigned int bufnum)
  221. {
  222. struct nand_chip *chip = mtd_to_nand(mtd);
  223. struct fsl_ifc_mtd *priv = nand_get_controller_data(chip);
  224. u8 __iomem *addr = priv->vbase + bufnum * (mtd->writesize * 2);
  225. u32 __iomem *main = (u32 *)addr;
  226. u8 __iomem *oob = addr + mtd->writesize;
  227. int i;
  228. for (i = 0; i < mtd->writesize / 4; i++) {
  229. if (__raw_readl(&main[i]) != 0xffffffff)
  230. return 0;
  231. }
  232. for (i = 0; i < chip->ecc.layout->eccbytes; i++) {
  233. int pos = chip->ecc.layout->eccpos[i];
  234. if (__raw_readb(&oob[pos]) != 0xff)
  235. return 0;
  236. }
  237. return 1;
  238. }
  239. /* returns nonzero if entire page is blank */
  240. static int check_read_ecc(struct mtd_info *mtd, struct fsl_ifc_ctrl *ctrl,
  241. u32 *eccstat, unsigned int bufnum)
  242. {
  243. u32 reg = eccstat[bufnum / 4];
  244. int errors;
  245. errors = (reg >> ((3 - bufnum % 4) * 8)) & 15;
  246. return errors;
  247. }
  248. /*
  249. * execute IFC NAND command and wait for it to complete
  250. */
  251. static int fsl_ifc_run_command(struct mtd_info *mtd)
  252. {
  253. struct nand_chip *chip = mtd_to_nand(mtd);
  254. struct fsl_ifc_mtd *priv = nand_get_controller_data(chip);
  255. struct fsl_ifc_ctrl *ctrl = priv->ctrl;
  256. struct fsl_ifc_runtime *ifc = ctrl->regs.rregs;
  257. u32 timeo = (CONFIG_SYS_HZ * 10) / 1000;
  258. u32 time_start;
  259. u32 eccstat[8] = {0};
  260. int i;
  261. /* set the chip select for NAND Transaction */
  262. ifc_out32(&ifc->ifc_nand.nand_csel, ifc_ctrl->cs_nand);
  263. /* start read/write seq */
  264. ifc_out32(&ifc->ifc_nand.nandseq_strt,
  265. IFC_NAND_SEQ_STRT_FIR_STRT);
  266. /* wait for NAND Machine complete flag or timeout */
  267. time_start = get_timer(0);
  268. while (get_timer(time_start) < timeo) {
  269. ctrl->status = ifc_in32(&ifc->ifc_nand.nand_evter_stat);
  270. if (ctrl->status & IFC_NAND_EVTER_STAT_OPC)
  271. break;
  272. }
  273. ifc_out32(&ifc->ifc_nand.nand_evter_stat, ctrl->status);
  274. if (ctrl->status & IFC_NAND_EVTER_STAT_FTOER)
  275. printf("%s: Flash Time Out Error\n", __func__);
  276. if (ctrl->status & IFC_NAND_EVTER_STAT_WPER)
  277. printf("%s: Write Protect Error\n", __func__);
  278. if (ctrl->eccread) {
  279. int errors;
  280. int bufnum = ctrl->page & priv->bufnum_mask;
  281. int sector = bufnum * chip->ecc.steps;
  282. int sector_end = sector + chip->ecc.steps - 1;
  283. for (i = sector / 4; i <= sector_end / 4; i++) {
  284. if (i >= ARRAY_SIZE(eccstat)) {
  285. printf("%s: eccstat too small for %d\n",
  286. __func__, i);
  287. return -EIO;
  288. }
  289. eccstat[i] = ifc_in32(&ifc->ifc_nand.nand_eccstat[i]);
  290. }
  291. for (i = sector; i <= sector_end; i++) {
  292. errors = check_read_ecc(mtd, ctrl, eccstat, i);
  293. if (errors == 15) {
  294. /*
  295. * Uncorrectable error.
  296. * OK only if the whole page is blank.
  297. *
  298. * We disable ECCER reporting due to erratum
  299. * IFC-A002770 -- so report it now if we
  300. * see an uncorrectable error in ECCSTAT.
  301. */
  302. if (!is_blank(mtd, ctrl, bufnum))
  303. ctrl->status |=
  304. IFC_NAND_EVTER_STAT_ECCER;
  305. break;
  306. }
  307. mtd->ecc_stats.corrected += errors;
  308. }
  309. ctrl->eccread = 0;
  310. }
  311. /* returns 0 on success otherwise non-zero) */
  312. return ctrl->status == IFC_NAND_EVTER_STAT_OPC ? 0 : -EIO;
  313. }
  314. static void fsl_ifc_do_read(struct nand_chip *chip,
  315. int oob,
  316. struct mtd_info *mtd)
  317. {
  318. struct fsl_ifc_mtd *priv = nand_get_controller_data(chip);
  319. struct fsl_ifc_ctrl *ctrl = priv->ctrl;
  320. struct fsl_ifc_runtime *ifc = ctrl->regs.rregs;
  321. /* Program FIR/IFC_NAND_FCR0 for Small/Large page */
  322. if (mtd->writesize > 512) {
  323. ifc_out32(&ifc->ifc_nand.nand_fir0,
  324. (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
  325. (IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP1_SHIFT) |
  326. (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP2_SHIFT) |
  327. (IFC_FIR_OP_CMD1 << IFC_NAND_FIR0_OP3_SHIFT) |
  328. (IFC_FIR_OP_RBCD << IFC_NAND_FIR0_OP4_SHIFT));
  329. ifc_out32(&ifc->ifc_nand.nand_fir1, 0x0);
  330. ifc_out32(&ifc->ifc_nand.nand_fcr0,
  331. (NAND_CMD_READ0 << IFC_NAND_FCR0_CMD0_SHIFT) |
  332. (NAND_CMD_READSTART << IFC_NAND_FCR0_CMD1_SHIFT));
  333. } else {
  334. ifc_out32(&ifc->ifc_nand.nand_fir0,
  335. (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
  336. (IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP1_SHIFT) |
  337. (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP2_SHIFT) |
  338. (IFC_FIR_OP_RBCD << IFC_NAND_FIR0_OP3_SHIFT));
  339. if (oob)
  340. ifc_out32(&ifc->ifc_nand.nand_fcr0,
  341. NAND_CMD_READOOB << IFC_NAND_FCR0_CMD0_SHIFT);
  342. else
  343. ifc_out32(&ifc->ifc_nand.nand_fcr0,
  344. NAND_CMD_READ0 << IFC_NAND_FCR0_CMD0_SHIFT);
  345. }
  346. }
  347. /* cmdfunc send commands to the IFC NAND Machine */
  348. static void fsl_ifc_cmdfunc(struct mtd_info *mtd, unsigned int command,
  349. int column, int page_addr)
  350. {
  351. struct nand_chip *chip = mtd_to_nand(mtd);
  352. struct fsl_ifc_mtd *priv = nand_get_controller_data(chip);
  353. struct fsl_ifc_ctrl *ctrl = priv->ctrl;
  354. struct fsl_ifc_runtime *ifc = ctrl->regs.rregs;
  355. /* clear the read buffer */
  356. ctrl->read_bytes = 0;
  357. if (command != NAND_CMD_PAGEPROG)
  358. ctrl->index = 0;
  359. switch (command) {
  360. /* READ0 read the entire buffer to use hardware ECC. */
  361. case NAND_CMD_READ0: {
  362. ifc_out32(&ifc->ifc_nand.nand_fbcr, 0);
  363. set_addr(mtd, 0, page_addr, 0);
  364. ctrl->read_bytes = mtd->writesize + mtd->oobsize;
  365. ctrl->index += column;
  366. if (chip->ecc.mode == NAND_ECC_HW)
  367. ctrl->eccread = 1;
  368. fsl_ifc_do_read(chip, 0, mtd);
  369. fsl_ifc_run_command(mtd);
  370. return;
  371. }
  372. /* READOOB reads only the OOB because no ECC is performed. */
  373. case NAND_CMD_READOOB:
  374. ifc_out32(&ifc->ifc_nand.nand_fbcr, mtd->oobsize - column);
  375. set_addr(mtd, column, page_addr, 1);
  376. ctrl->read_bytes = mtd->writesize + mtd->oobsize;
  377. fsl_ifc_do_read(chip, 1, mtd);
  378. fsl_ifc_run_command(mtd);
  379. return;
  380. /* READID must read all possible bytes while CEB is active */
  381. case NAND_CMD_READID:
  382. case NAND_CMD_PARAM: {
  383. int timing = IFC_FIR_OP_RB;
  384. if (command == NAND_CMD_PARAM)
  385. timing = IFC_FIR_OP_RBCD;
  386. ifc_out32(&ifc->ifc_nand.nand_fir0,
  387. (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
  388. (IFC_FIR_OP_UA << IFC_NAND_FIR0_OP1_SHIFT) |
  389. (timing << IFC_NAND_FIR0_OP2_SHIFT));
  390. ifc_out32(&ifc->ifc_nand.nand_fcr0,
  391. command << IFC_NAND_FCR0_CMD0_SHIFT);
  392. ifc_out32(&ifc->ifc_nand.row3, column);
  393. /*
  394. * although currently it's 8 bytes for READID, we always read
  395. * the maximum 256 bytes(for PARAM)
  396. */
  397. ifc_out32(&ifc->ifc_nand.nand_fbcr, 256);
  398. ctrl->read_bytes = 256;
  399. set_addr(mtd, 0, 0, 0);
  400. fsl_ifc_run_command(mtd);
  401. return;
  402. }
  403. /* ERASE1 stores the block and page address */
  404. case NAND_CMD_ERASE1:
  405. set_addr(mtd, 0, page_addr, 0);
  406. return;
  407. /* ERASE2 uses the block and page address from ERASE1 */
  408. case NAND_CMD_ERASE2:
  409. ifc_out32(&ifc->ifc_nand.nand_fir0,
  410. (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
  411. (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP1_SHIFT) |
  412. (IFC_FIR_OP_CMD1 << IFC_NAND_FIR0_OP2_SHIFT));
  413. ifc_out32(&ifc->ifc_nand.nand_fcr0,
  414. (NAND_CMD_ERASE1 << IFC_NAND_FCR0_CMD0_SHIFT) |
  415. (NAND_CMD_ERASE2 << IFC_NAND_FCR0_CMD1_SHIFT));
  416. ifc_out32(&ifc->ifc_nand.nand_fbcr, 0);
  417. ctrl->read_bytes = 0;
  418. fsl_ifc_run_command(mtd);
  419. return;
  420. /* SEQIN sets up the addr buffer and all registers except the length */
  421. case NAND_CMD_SEQIN: {
  422. u32 nand_fcr0;
  423. ctrl->column = column;
  424. ctrl->oob = 0;
  425. if (mtd->writesize > 512) {
  426. nand_fcr0 =
  427. (NAND_CMD_SEQIN << IFC_NAND_FCR0_CMD0_SHIFT) |
  428. (NAND_CMD_STATUS << IFC_NAND_FCR0_CMD1_SHIFT) |
  429. (NAND_CMD_PAGEPROG << IFC_NAND_FCR0_CMD2_SHIFT);
  430. ifc_out32(&ifc->ifc_nand.nand_fir0,
  431. (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
  432. (IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP1_SHIFT) |
  433. (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP2_SHIFT) |
  434. (IFC_FIR_OP_WBCD <<
  435. IFC_NAND_FIR0_OP3_SHIFT) |
  436. (IFC_FIR_OP_CMD2 << IFC_NAND_FIR0_OP4_SHIFT));
  437. ifc_out32(&ifc->ifc_nand.nand_fir1,
  438. (IFC_FIR_OP_CW1 << IFC_NAND_FIR1_OP5_SHIFT) |
  439. (IFC_FIR_OP_RDSTAT <<
  440. IFC_NAND_FIR1_OP6_SHIFT) |
  441. (IFC_FIR_OP_NOP << IFC_NAND_FIR1_OP7_SHIFT));
  442. } else {
  443. nand_fcr0 = ((NAND_CMD_PAGEPROG <<
  444. IFC_NAND_FCR0_CMD1_SHIFT) |
  445. (NAND_CMD_SEQIN <<
  446. IFC_NAND_FCR0_CMD2_SHIFT) |
  447. (NAND_CMD_STATUS <<
  448. IFC_NAND_FCR0_CMD3_SHIFT));
  449. ifc_out32(&ifc->ifc_nand.nand_fir0,
  450. (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
  451. (IFC_FIR_OP_CMD2 << IFC_NAND_FIR0_OP1_SHIFT) |
  452. (IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP2_SHIFT) |
  453. (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP3_SHIFT) |
  454. (IFC_FIR_OP_WBCD << IFC_NAND_FIR0_OP4_SHIFT));
  455. ifc_out32(&ifc->ifc_nand.nand_fir1,
  456. (IFC_FIR_OP_CMD1 << IFC_NAND_FIR1_OP5_SHIFT) |
  457. (IFC_FIR_OP_CW3 << IFC_NAND_FIR1_OP6_SHIFT) |
  458. (IFC_FIR_OP_RDSTAT <<
  459. IFC_NAND_FIR1_OP7_SHIFT) |
  460. (IFC_FIR_OP_NOP << IFC_NAND_FIR1_OP8_SHIFT));
  461. if (column >= mtd->writesize)
  462. nand_fcr0 |=
  463. NAND_CMD_READOOB << IFC_NAND_FCR0_CMD0_SHIFT;
  464. else
  465. nand_fcr0 |=
  466. NAND_CMD_READ0 << IFC_NAND_FCR0_CMD0_SHIFT;
  467. }
  468. if (column >= mtd->writesize) {
  469. /* OOB area --> READOOB */
  470. column -= mtd->writesize;
  471. ctrl->oob = 1;
  472. }
  473. ifc_out32(&ifc->ifc_nand.nand_fcr0, nand_fcr0);
  474. set_addr(mtd, column, page_addr, ctrl->oob);
  475. return;
  476. }
  477. /* PAGEPROG reuses all of the setup from SEQIN and adds the length */
  478. case NAND_CMD_PAGEPROG:
  479. if (ctrl->oob)
  480. ifc_out32(&ifc->ifc_nand.nand_fbcr,
  481. ctrl->index - ctrl->column);
  482. else
  483. ifc_out32(&ifc->ifc_nand.nand_fbcr, 0);
  484. fsl_ifc_run_command(mtd);
  485. return;
  486. case NAND_CMD_STATUS:
  487. ifc_out32(&ifc->ifc_nand.nand_fir0,
  488. (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
  489. (IFC_FIR_OP_RB << IFC_NAND_FIR0_OP1_SHIFT));
  490. ifc_out32(&ifc->ifc_nand.nand_fcr0,
  491. NAND_CMD_STATUS << IFC_NAND_FCR0_CMD0_SHIFT);
  492. ifc_out32(&ifc->ifc_nand.nand_fbcr, 1);
  493. set_addr(mtd, 0, 0, 0);
  494. ctrl->read_bytes = 1;
  495. fsl_ifc_run_command(mtd);
  496. /*
  497. * The chip always seems to report that it is
  498. * write-protected, even when it is not.
  499. */
  500. if (chip->options & NAND_BUSWIDTH_16)
  501. ifc_out16(ctrl->addr,
  502. ifc_in16(ctrl->addr) | NAND_STATUS_WP);
  503. else
  504. out_8(ctrl->addr, in_8(ctrl->addr) | NAND_STATUS_WP);
  505. return;
  506. case NAND_CMD_RESET:
  507. ifc_out32(&ifc->ifc_nand.nand_fir0,
  508. IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT);
  509. ifc_out32(&ifc->ifc_nand.nand_fcr0,
  510. NAND_CMD_RESET << IFC_NAND_FCR0_CMD0_SHIFT);
  511. fsl_ifc_run_command(mtd);
  512. return;
  513. default:
  514. printf("%s: error, unsupported command 0x%x.\n",
  515. __func__, command);
  516. }
  517. }
  518. /*
  519. * Write buf to the IFC NAND Controller Data Buffer
  520. */
  521. static void fsl_ifc_write_buf(struct mtd_info *mtd, const u8 *buf, int len)
  522. {
  523. struct nand_chip *chip = mtd_to_nand(mtd);
  524. struct fsl_ifc_mtd *priv = nand_get_controller_data(chip);
  525. struct fsl_ifc_ctrl *ctrl = priv->ctrl;
  526. unsigned int bufsize = mtd->writesize + mtd->oobsize;
  527. if (len <= 0) {
  528. printf("%s of %d bytes", __func__, len);
  529. ctrl->status = 0;
  530. return;
  531. }
  532. if ((unsigned int)len > bufsize - ctrl->index) {
  533. printf("%s beyond end of buffer "
  534. "(%d requested, %u available)\n",
  535. __func__, len, bufsize - ctrl->index);
  536. len = bufsize - ctrl->index;
  537. }
  538. memcpy_toio(ctrl->addr + ctrl->index, buf, len);
  539. ctrl->index += len;
  540. }
  541. /*
  542. * read a byte from either the IFC hardware buffer if it has any data left
  543. * otherwise issue a command to read a single byte.
  544. */
  545. static u8 fsl_ifc_read_byte(struct mtd_info *mtd)
  546. {
  547. struct nand_chip *chip = mtd_to_nand(mtd);
  548. struct fsl_ifc_mtd *priv = nand_get_controller_data(chip);
  549. struct fsl_ifc_ctrl *ctrl = priv->ctrl;
  550. unsigned int offset;
  551. /*
  552. * If there are still bytes in the IFC buffer, then use the
  553. * next byte.
  554. */
  555. if (ctrl->index < ctrl->read_bytes) {
  556. offset = ctrl->index++;
  557. return in_8(ctrl->addr + offset);
  558. }
  559. printf("%s beyond end of buffer\n", __func__);
  560. return ERR_BYTE;
  561. }
  562. /*
  563. * Read two bytes from the IFC hardware buffer
  564. * read function for 16-bit buswith
  565. */
  566. static uint8_t fsl_ifc_read_byte16(struct mtd_info *mtd)
  567. {
  568. struct nand_chip *chip = mtd_to_nand(mtd);
  569. struct fsl_ifc_mtd *priv = nand_get_controller_data(chip);
  570. struct fsl_ifc_ctrl *ctrl = priv->ctrl;
  571. uint16_t data;
  572. /*
  573. * If there are still bytes in the IFC buffer, then use the
  574. * next byte.
  575. */
  576. if (ctrl->index < ctrl->read_bytes) {
  577. data = ifc_in16(ctrl->addr + ctrl->index);
  578. ctrl->index += 2;
  579. return (uint8_t)data;
  580. }
  581. printf("%s beyond end of buffer\n", __func__);
  582. return ERR_BYTE;
  583. }
  584. /*
  585. * Read from the IFC Controller Data Buffer
  586. */
  587. static void fsl_ifc_read_buf(struct mtd_info *mtd, u8 *buf, int len)
  588. {
  589. struct nand_chip *chip = mtd_to_nand(mtd);
  590. struct fsl_ifc_mtd *priv = nand_get_controller_data(chip);
  591. struct fsl_ifc_ctrl *ctrl = priv->ctrl;
  592. int avail;
  593. if (len < 0)
  594. return;
  595. avail = min((unsigned int)len, ctrl->read_bytes - ctrl->index);
  596. memcpy_fromio(buf, ctrl->addr + ctrl->index, avail);
  597. ctrl->index += avail;
  598. if (len > avail)
  599. printf("%s beyond end of buffer "
  600. "(%d requested, %d available)\n",
  601. __func__, len, avail);
  602. }
  603. /* This function is called after Program and Erase Operations to
  604. * check for success or failure.
  605. */
  606. static int fsl_ifc_wait(struct mtd_info *mtd, struct nand_chip *chip)
  607. {
  608. struct fsl_ifc_mtd *priv = nand_get_controller_data(chip);
  609. struct fsl_ifc_ctrl *ctrl = priv->ctrl;
  610. struct fsl_ifc_runtime *ifc = ctrl->regs.rregs;
  611. u32 nand_fsr;
  612. if (ctrl->status != IFC_NAND_EVTER_STAT_OPC)
  613. return NAND_STATUS_FAIL;
  614. /* Use READ_STATUS command, but wait for the device to be ready */
  615. ifc_out32(&ifc->ifc_nand.nand_fir0,
  616. (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
  617. (IFC_FIR_OP_RDSTAT << IFC_NAND_FIR0_OP1_SHIFT));
  618. ifc_out32(&ifc->ifc_nand.nand_fcr0, NAND_CMD_STATUS <<
  619. IFC_NAND_FCR0_CMD0_SHIFT);
  620. ifc_out32(&ifc->ifc_nand.nand_fbcr, 1);
  621. set_addr(mtd, 0, 0, 0);
  622. ctrl->read_bytes = 1;
  623. fsl_ifc_run_command(mtd);
  624. if (ctrl->status != IFC_NAND_EVTER_STAT_OPC)
  625. return NAND_STATUS_FAIL;
  626. nand_fsr = ifc_in32(&ifc->ifc_nand.nand_fsr);
  627. /* Chip sometimes reporting write protect even when it's not */
  628. nand_fsr = nand_fsr | NAND_STATUS_WP;
  629. return nand_fsr;
  630. }
  631. static int fsl_ifc_read_page(struct mtd_info *mtd, struct nand_chip *chip,
  632. uint8_t *buf, int oob_required, int page)
  633. {
  634. struct fsl_ifc_mtd *priv = nand_get_controller_data(chip);
  635. struct fsl_ifc_ctrl *ctrl = priv->ctrl;
  636. fsl_ifc_read_buf(mtd, buf, mtd->writesize);
  637. fsl_ifc_read_buf(mtd, chip->oob_poi, mtd->oobsize);
  638. if (ctrl->status != IFC_NAND_EVTER_STAT_OPC)
  639. mtd->ecc_stats.failed++;
  640. return 0;
  641. }
  642. /* ECC will be calculated automatically, and errors will be detected in
  643. * waitfunc.
  644. */
  645. static int fsl_ifc_write_page(struct mtd_info *mtd, struct nand_chip *chip,
  646. const uint8_t *buf, int oob_required)
  647. {
  648. fsl_ifc_write_buf(mtd, buf, mtd->writesize);
  649. fsl_ifc_write_buf(mtd, chip->oob_poi, mtd->oobsize);
  650. return 0;
  651. }
  652. static void fsl_ifc_ctrl_init(void)
  653. {
  654. uint32_t ver = 0;
  655. ifc_ctrl = kzalloc(sizeof(*ifc_ctrl), GFP_KERNEL);
  656. if (!ifc_ctrl)
  657. return;
  658. ifc_ctrl->regs.gregs = IFC_FCM_BASE_ADDR;
  659. ver = ifc_in32(&ifc_ctrl->regs.gregs->ifc_rev);
  660. if (ver >= FSL_IFC_V2_0_0)
  661. ifc_ctrl->regs.rregs =
  662. (void *)CONFIG_SYS_IFC_ADDR + IFC_RREGS_64KOFFSET;
  663. else
  664. ifc_ctrl->regs.rregs =
  665. (void *)CONFIG_SYS_IFC_ADDR + IFC_RREGS_4KOFFSET;
  666. /* clear event registers */
  667. ifc_out32(&ifc_ctrl->regs.rregs->ifc_nand.nand_evter_stat, ~0U);
  668. ifc_out32(&ifc_ctrl->regs.rregs->ifc_nand.pgrdcmpl_evt_stat, ~0U);
  669. /* Enable error and event for any detected errors */
  670. ifc_out32(&ifc_ctrl->regs.rregs->ifc_nand.nand_evter_en,
  671. IFC_NAND_EVTER_EN_OPC_EN |
  672. IFC_NAND_EVTER_EN_PGRDCMPL_EN |
  673. IFC_NAND_EVTER_EN_FTOER_EN |
  674. IFC_NAND_EVTER_EN_WPER_EN);
  675. ifc_out32(&ifc_ctrl->regs.rregs->ifc_nand.ncfgr, 0x0);
  676. }
  677. static void fsl_ifc_select_chip(struct mtd_info *mtd, int chip)
  678. {
  679. }
  680. static int fsl_ifc_sram_init(uint32_t ver)
  681. {
  682. struct fsl_ifc_runtime *ifc = ifc_ctrl->regs.rregs;
  683. uint32_t cs = 0, csor = 0, csor_8k = 0, csor_ext = 0;
  684. uint32_t ncfgr = 0;
  685. u32 timeo = (CONFIG_SYS_HZ * 10) / 1000;
  686. u32 time_start;
  687. if (ver > FSL_IFC_V1_1_0) {
  688. ncfgr = ifc_in32(&ifc->ifc_nand.ncfgr);
  689. ifc_out32(&ifc->ifc_nand.ncfgr, ncfgr | IFC_NAND_SRAM_INIT_EN);
  690. /* wait for SRAM_INIT bit to be clear or timeout */
  691. time_start = get_timer(0);
  692. while (get_timer(time_start) < timeo) {
  693. ifc_ctrl->status =
  694. ifc_in32(&ifc->ifc_nand.nand_evter_stat);
  695. if (!(ifc_ctrl->status & IFC_NAND_SRAM_INIT_EN))
  696. return 0;
  697. }
  698. printf("fsl-ifc: Failed to Initialise SRAM\n");
  699. return 1;
  700. }
  701. cs = ifc_ctrl->cs_nand >> IFC_NAND_CSEL_SHIFT;
  702. /* Save CSOR and CSOR_ext */
  703. csor = ifc_in32(&ifc_ctrl->regs.gregs->csor_cs[cs].csor);
  704. csor_ext = ifc_in32(&ifc_ctrl->regs.gregs->csor_cs[cs].csor_ext);
  705. /* chage PageSize 8K and SpareSize 1K*/
  706. csor_8k = (csor & ~(CSOR_NAND_PGS_MASK)) | 0x0018C000;
  707. ifc_out32(&ifc_ctrl->regs.gregs->csor_cs[cs].csor, csor_8k);
  708. ifc_out32(&ifc_ctrl->regs.gregs->csor_cs[cs].csor_ext, 0x0000400);
  709. /* READID */
  710. ifc_out32(&ifc->ifc_nand.nand_fir0,
  711. (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
  712. (IFC_FIR_OP_UA << IFC_NAND_FIR0_OP1_SHIFT) |
  713. (IFC_FIR_OP_RB << IFC_NAND_FIR0_OP2_SHIFT));
  714. ifc_out32(&ifc->ifc_nand.nand_fcr0,
  715. NAND_CMD_READID << IFC_NAND_FCR0_CMD0_SHIFT);
  716. ifc_out32(&ifc->ifc_nand.row3, 0x0);
  717. ifc_out32(&ifc->ifc_nand.nand_fbcr, 0x0);
  718. /* Program ROW0/COL0 */
  719. ifc_out32(&ifc->ifc_nand.row0, 0x0);
  720. ifc_out32(&ifc->ifc_nand.col0, 0x0);
  721. /* set the chip select for NAND Transaction */
  722. ifc_out32(&ifc->ifc_nand.nand_csel, ifc_ctrl->cs_nand);
  723. /* start read seq */
  724. ifc_out32(&ifc->ifc_nand.nandseq_strt, IFC_NAND_SEQ_STRT_FIR_STRT);
  725. time_start = get_timer(0);
  726. while (get_timer(time_start) < timeo) {
  727. ifc_ctrl->status = ifc_in32(&ifc->ifc_nand.nand_evter_stat);
  728. if (ifc_ctrl->status & IFC_NAND_EVTER_STAT_OPC)
  729. break;
  730. }
  731. if (ifc_ctrl->status != IFC_NAND_EVTER_STAT_OPC) {
  732. printf("fsl-ifc: Failed to Initialise SRAM\n");
  733. return 1;
  734. }
  735. ifc_out32(&ifc->ifc_nand.nand_evter_stat, ifc_ctrl->status);
  736. /* Restore CSOR and CSOR_ext */
  737. ifc_out32(&ifc_ctrl->regs.gregs->csor_cs[cs].csor, csor);
  738. ifc_out32(&ifc_ctrl->regs.gregs->csor_cs[cs].csor_ext, csor_ext);
  739. return 0;
  740. }
  741. static int fsl_ifc_chip_init(int devnum, u8 *addr)
  742. {
  743. struct mtd_info *mtd;
  744. struct nand_chip *nand;
  745. struct fsl_ifc_mtd *priv;
  746. struct nand_ecclayout *layout;
  747. struct fsl_ifc_fcm *gregs = NULL;
  748. uint32_t cspr = 0, csor = 0, ver = 0;
  749. int ret = 0;
  750. if (!ifc_ctrl) {
  751. fsl_ifc_ctrl_init();
  752. if (!ifc_ctrl)
  753. return -1;
  754. }
  755. priv = kzalloc(sizeof(*priv), GFP_KERNEL);
  756. if (!priv)
  757. return -ENOMEM;
  758. priv->ctrl = ifc_ctrl;
  759. priv->vbase = addr;
  760. gregs = ifc_ctrl->regs.gregs;
  761. /* Find which chip select it is connected to.
  762. */
  763. for (priv->bank = 0; priv->bank < MAX_BANKS; priv->bank++) {
  764. phys_addr_t phys_addr = virt_to_phys(addr);
  765. cspr = ifc_in32(&gregs->cspr_cs[priv->bank].cspr);
  766. csor = ifc_in32(&gregs->csor_cs[priv->bank].csor);
  767. if ((cspr & CSPR_V) && (cspr & CSPR_MSEL) == CSPR_MSEL_NAND &&
  768. (cspr & CSPR_BA) == CSPR_PHYS_ADDR(phys_addr)) {
  769. ifc_ctrl->cs_nand = priv->bank << IFC_NAND_CSEL_SHIFT;
  770. break;
  771. }
  772. }
  773. if (priv->bank >= MAX_BANKS) {
  774. printf("%s: address did not match any "
  775. "chip selects\n", __func__);
  776. kfree(priv);
  777. return -ENODEV;
  778. }
  779. nand = &priv->chip;
  780. mtd = nand_to_mtd(nand);
  781. ifc_ctrl->chips[priv->bank] = priv;
  782. /* fill in nand_chip structure */
  783. /* set up function call table */
  784. nand->write_buf = fsl_ifc_write_buf;
  785. nand->read_buf = fsl_ifc_read_buf;
  786. nand->select_chip = fsl_ifc_select_chip;
  787. nand->cmdfunc = fsl_ifc_cmdfunc;
  788. nand->waitfunc = fsl_ifc_wait;
  789. /* set up nand options */
  790. nand->bbt_td = &bbt_main_descr;
  791. nand->bbt_md = &bbt_mirror_descr;
  792. /* set up nand options */
  793. nand->options = NAND_NO_SUBPAGE_WRITE;
  794. nand->bbt_options = NAND_BBT_USE_FLASH;
  795. if (cspr & CSPR_PORT_SIZE_16) {
  796. nand->read_byte = fsl_ifc_read_byte16;
  797. nand->options |= NAND_BUSWIDTH_16;
  798. } else {
  799. nand->read_byte = fsl_ifc_read_byte;
  800. }
  801. nand->controller = &ifc_ctrl->controller;
  802. nand_set_controller_data(nand, priv);
  803. nand->ecc.read_page = fsl_ifc_read_page;
  804. nand->ecc.write_page = fsl_ifc_write_page;
  805. /* Hardware generates ECC per 512 Bytes */
  806. nand->ecc.size = 512;
  807. nand->ecc.bytes = 8;
  808. switch (csor & CSOR_NAND_PGS_MASK) {
  809. case CSOR_NAND_PGS_512:
  810. if (nand->options & NAND_BUSWIDTH_16) {
  811. layout = &oob_512_16bit_ecc4;
  812. } else {
  813. layout = &oob_512_8bit_ecc4;
  814. /* Avoid conflict with bad block marker */
  815. bbt_main_descr.offs = 0;
  816. bbt_mirror_descr.offs = 0;
  817. }
  818. nand->ecc.strength = 4;
  819. priv->bufnum_mask = 15;
  820. break;
  821. case CSOR_NAND_PGS_2K:
  822. layout = &oob_2048_ecc4;
  823. nand->ecc.strength = 4;
  824. priv->bufnum_mask = 3;
  825. break;
  826. case CSOR_NAND_PGS_4K:
  827. if ((csor & CSOR_NAND_ECC_MODE_MASK) ==
  828. CSOR_NAND_ECC_MODE_4) {
  829. layout = &oob_4096_ecc4;
  830. nand->ecc.strength = 4;
  831. } else {
  832. layout = &oob_4096_ecc8;
  833. nand->ecc.strength = 8;
  834. nand->ecc.bytes = 16;
  835. }
  836. priv->bufnum_mask = 1;
  837. break;
  838. case CSOR_NAND_PGS_8K:
  839. if ((csor & CSOR_NAND_ECC_MODE_MASK) ==
  840. CSOR_NAND_ECC_MODE_4) {
  841. layout = &oob_8192_ecc4;
  842. nand->ecc.strength = 4;
  843. } else {
  844. layout = &oob_8192_ecc8;
  845. nand->ecc.strength = 8;
  846. nand->ecc.bytes = 16;
  847. }
  848. priv->bufnum_mask = 0;
  849. break;
  850. default:
  851. printf("ifc nand: bad csor %#x: bad page size\n", csor);
  852. return -ENODEV;
  853. }
  854. /* Must also set CSOR_NAND_ECC_ENC_EN if DEC_EN set */
  855. if (csor & CSOR_NAND_ECC_DEC_EN) {
  856. nand->ecc.mode = NAND_ECC_HW;
  857. nand->ecc.layout = layout;
  858. } else {
  859. nand->ecc.mode = NAND_ECC_SOFT;
  860. }
  861. ver = ifc_in32(&gregs->ifc_rev);
  862. if (ver >= FSL_IFC_V1_1_0)
  863. ret = fsl_ifc_sram_init(ver);
  864. if (ret)
  865. return ret;
  866. if (ver >= FSL_IFC_V2_0_0)
  867. priv->bufnum_mask = (priv->bufnum_mask * 2) + 1;
  868. ret = nand_scan_ident(mtd, 1, NULL);
  869. if (ret)
  870. return ret;
  871. ret = nand_scan_tail(mtd);
  872. if (ret)
  873. return ret;
  874. ret = nand_register(devnum, mtd);
  875. if (ret)
  876. return ret;
  877. return 0;
  878. }
  879. #ifndef CONFIG_SYS_NAND_BASE_LIST
  880. #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
  881. #endif
  882. static unsigned long base_address[CONFIG_SYS_MAX_NAND_DEVICE] =
  883. CONFIG_SYS_NAND_BASE_LIST;
  884. void board_nand_init(void)
  885. {
  886. int i;
  887. for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
  888. fsl_ifc_chip_init(i, (u8 *)base_address[i]);
  889. }