davinci_nand.c 22 KB

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  1. /*
  2. * NAND driver for TI DaVinci based boards.
  3. *
  4. * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
  5. *
  6. * Based on Linux DaVinci NAND driver by TI. Original copyright follows:
  7. */
  8. /*
  9. *
  10. * linux/drivers/mtd/nand/nand_davinci.c
  11. *
  12. * NAND Flash Driver
  13. *
  14. * Copyright (C) 2006 Texas Instruments.
  15. *
  16. * ----------------------------------------------------------------------------
  17. *
  18. * SPDX-License-Identifier: GPL-2.0+
  19. *
  20. * ----------------------------------------------------------------------------
  21. *
  22. * Overview:
  23. * This is a device driver for the NAND flash device found on the
  24. * DaVinci board which utilizes the Samsung k9k2g08 part.
  25. *
  26. Modifications:
  27. ver. 1.0: Feb 2005, Vinod/Sudhakar
  28. -
  29. */
  30. #include <common.h>
  31. #include <asm/io.h>
  32. #include <nand.h>
  33. #include <asm/ti-common/davinci_nand.h>
  34. /* Definitions for 4-bit hardware ECC */
  35. #define NAND_TIMEOUT 10240
  36. #define NAND_ECC_BUSY 0xC
  37. #define NAND_4BITECC_MASK 0x03FF03FF
  38. #define EMIF_NANDFSR_ECC_STATE_MASK 0x00000F00
  39. #define ECC_STATE_NO_ERR 0x0
  40. #define ECC_STATE_TOO_MANY_ERRS 0x1
  41. #define ECC_STATE_ERR_CORR_COMP_P 0x2
  42. #define ECC_STATE_ERR_CORR_COMP_N 0x3
  43. /*
  44. * Exploit the little endianness of the ARM to do multi-byte transfers
  45. * per device read. This can perform over twice as quickly as individual
  46. * byte transfers when buffer alignment is conducive.
  47. *
  48. * NOTE: This only works if the NAND is not connected to the 2 LSBs of
  49. * the address bus. On Davinci EVM platforms this has always been true.
  50. */
  51. static void nand_davinci_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
  52. {
  53. struct nand_chip *chip = mtd_to_nand(mtd);
  54. const u32 *nand = chip->IO_ADDR_R;
  55. /* Make sure that buf is 32 bit aligned */
  56. if (((int)buf & 0x3) != 0) {
  57. if (((int)buf & 0x1) != 0) {
  58. if (len) {
  59. *buf = readb(nand);
  60. buf += 1;
  61. len--;
  62. }
  63. }
  64. if (((int)buf & 0x3) != 0) {
  65. if (len >= 2) {
  66. *(u16 *)buf = readw(nand);
  67. buf += 2;
  68. len -= 2;
  69. }
  70. }
  71. }
  72. /* copy aligned data */
  73. while (len >= 4) {
  74. *(u32 *)buf = __raw_readl(nand);
  75. buf += 4;
  76. len -= 4;
  77. }
  78. /* mop up any remaining bytes */
  79. if (len) {
  80. if (len >= 2) {
  81. *(u16 *)buf = readw(nand);
  82. buf += 2;
  83. len -= 2;
  84. }
  85. if (len)
  86. *buf = readb(nand);
  87. }
  88. }
  89. static void nand_davinci_write_buf(struct mtd_info *mtd, const uint8_t *buf,
  90. int len)
  91. {
  92. struct nand_chip *chip = mtd_to_nand(mtd);
  93. const u32 *nand = chip->IO_ADDR_W;
  94. /* Make sure that buf is 32 bit aligned */
  95. if (((int)buf & 0x3) != 0) {
  96. if (((int)buf & 0x1) != 0) {
  97. if (len) {
  98. writeb(*buf, nand);
  99. buf += 1;
  100. len--;
  101. }
  102. }
  103. if (((int)buf & 0x3) != 0) {
  104. if (len >= 2) {
  105. writew(*(u16 *)buf, nand);
  106. buf += 2;
  107. len -= 2;
  108. }
  109. }
  110. }
  111. /* copy aligned data */
  112. while (len >= 4) {
  113. __raw_writel(*(u32 *)buf, nand);
  114. buf += 4;
  115. len -= 4;
  116. }
  117. /* mop up any remaining bytes */
  118. if (len) {
  119. if (len >= 2) {
  120. writew(*(u16 *)buf, nand);
  121. buf += 2;
  122. len -= 2;
  123. }
  124. if (len)
  125. writeb(*buf, nand);
  126. }
  127. }
  128. static void nand_davinci_hwcontrol(struct mtd_info *mtd, int cmd,
  129. unsigned int ctrl)
  130. {
  131. struct nand_chip *this = mtd_to_nand(mtd);
  132. u_int32_t IO_ADDR_W = (u_int32_t)this->IO_ADDR_W;
  133. if (ctrl & NAND_CTRL_CHANGE) {
  134. IO_ADDR_W &= ~(MASK_ALE|MASK_CLE);
  135. if (ctrl & NAND_CLE)
  136. IO_ADDR_W |= MASK_CLE;
  137. if (ctrl & NAND_ALE)
  138. IO_ADDR_W |= MASK_ALE;
  139. this->IO_ADDR_W = (void __iomem *) IO_ADDR_W;
  140. }
  141. if (cmd != NAND_CMD_NONE)
  142. writeb(cmd, IO_ADDR_W);
  143. }
  144. #ifdef CONFIG_SYS_NAND_HW_ECC
  145. static u_int32_t nand_davinci_readecc(struct mtd_info *mtd)
  146. {
  147. u_int32_t ecc = 0;
  148. ecc = __raw_readl(&(davinci_emif_regs->nandfecc[
  149. CONFIG_SYS_NAND_CS - 2]));
  150. return ecc;
  151. }
  152. static void nand_davinci_enable_hwecc(struct mtd_info *mtd, int mode)
  153. {
  154. u_int32_t val;
  155. /* reading the ECC result register resets the ECC calculation */
  156. nand_davinci_readecc(mtd);
  157. val = __raw_readl(&davinci_emif_regs->nandfcr);
  158. val |= DAVINCI_NANDFCR_NAND_ENABLE(CONFIG_SYS_NAND_CS);
  159. val |= DAVINCI_NANDFCR_1BIT_ECC_START(CONFIG_SYS_NAND_CS);
  160. __raw_writel(val, &davinci_emif_regs->nandfcr);
  161. }
  162. static int nand_davinci_calculate_ecc(struct mtd_info *mtd, const u_char *dat,
  163. u_char *ecc_code)
  164. {
  165. u_int32_t tmp;
  166. tmp = nand_davinci_readecc(mtd);
  167. /* Squeeze 4 bytes ECC into 3 bytes by removing RESERVED bits
  168. * and shifting. RESERVED bits are 31 to 28 and 15 to 12. */
  169. tmp = (tmp & 0x00000fff) | ((tmp & 0x0fff0000) >> 4);
  170. /* Invert so that erased block ECC is correct */
  171. tmp = ~tmp;
  172. *ecc_code++ = tmp;
  173. *ecc_code++ = tmp >> 8;
  174. *ecc_code++ = tmp >> 16;
  175. /* NOTE: the above code matches mainline Linux:
  176. * .PQR.stu ==> ~PQRstu
  177. *
  178. * MontaVista/TI kernels encode those bytes differently, use
  179. * complicated (and allegedly sometimes-wrong) correction code,
  180. * and usually shipped with U-Boot that uses software ECC:
  181. * .PQR.stu ==> PsQRtu
  182. *
  183. * If you need MV/TI compatible NAND I/O in U-Boot, it should
  184. * be possible to (a) change the mangling above, (b) reverse
  185. * that mangling in nand_davinci_correct_data() below.
  186. */
  187. return 0;
  188. }
  189. static int nand_davinci_correct_data(struct mtd_info *mtd, u_char *dat,
  190. u_char *read_ecc, u_char *calc_ecc)
  191. {
  192. struct nand_chip *this = mtd_to_nand(mtd);
  193. u_int32_t ecc_nand = read_ecc[0] | (read_ecc[1] << 8) |
  194. (read_ecc[2] << 16);
  195. u_int32_t ecc_calc = calc_ecc[0] | (calc_ecc[1] << 8) |
  196. (calc_ecc[2] << 16);
  197. u_int32_t diff = ecc_calc ^ ecc_nand;
  198. if (diff) {
  199. if ((((diff >> 12) ^ diff) & 0xfff) == 0xfff) {
  200. /* Correctable error */
  201. if ((diff >> (12 + 3)) < this->ecc.size) {
  202. uint8_t find_bit = 1 << ((diff >> 12) & 7);
  203. uint32_t find_byte = diff >> (12 + 3);
  204. dat[find_byte] ^= find_bit;
  205. MTDDEBUG(MTD_DEBUG_LEVEL0, "Correcting single "
  206. "bit ECC error at offset: %d, bit: "
  207. "%d\n", find_byte, find_bit);
  208. return 1;
  209. } else {
  210. return -1;
  211. }
  212. } else if (!(diff & (diff - 1))) {
  213. /* Single bit ECC error in the ECC itself,
  214. nothing to fix */
  215. MTDDEBUG(MTD_DEBUG_LEVEL0, "Single bit ECC error in "
  216. "ECC.\n");
  217. return 1;
  218. } else {
  219. /* Uncorrectable error */
  220. MTDDEBUG(MTD_DEBUG_LEVEL0, "ECC UNCORRECTED_ERROR 1\n");
  221. return -1;
  222. }
  223. }
  224. return 0;
  225. }
  226. #endif /* CONFIG_SYS_NAND_HW_ECC */
  227. #ifdef CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST
  228. static struct nand_ecclayout nand_davinci_4bit_layout_oobfirst = {
  229. #if defined(CONFIG_SYS_NAND_PAGE_2K)
  230. .eccbytes = 40,
  231. #ifdef CONFIG_NAND_6BYTES_OOB_FREE_10BYTES_ECC
  232. .eccpos = {
  233. 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,
  234. 22, 23, 24, 25, 26, 27, 28, 29, 30, 31,
  235. 38, 39, 40, 41, 42, 43, 44, 45, 46, 47,
  236. 54, 55, 56, 57, 58, 59, 60, 61, 62, 63,
  237. },
  238. .oobfree = {
  239. {2, 4}, {16, 6}, {32, 6}, {48, 6},
  240. },
  241. #else
  242. .eccpos = {
  243. 24, 25, 26, 27, 28,
  244. 29, 30, 31, 32, 33, 34, 35, 36, 37, 38,
  245. 39, 40, 41, 42, 43, 44, 45, 46, 47, 48,
  246. 49, 50, 51, 52, 53, 54, 55, 56, 57, 58,
  247. 59, 60, 61, 62, 63,
  248. },
  249. .oobfree = {
  250. {.offset = 2, .length = 22, },
  251. },
  252. #endif /* #ifdef CONFIG_NAND_6BYTES_OOB_FREE_10BYTES_ECC */
  253. #elif defined(CONFIG_SYS_NAND_PAGE_4K)
  254. .eccbytes = 80,
  255. .eccpos = {
  256. 48, 49, 50, 51, 52, 53, 54, 55, 56, 57,
  257. 58, 59, 60, 61, 62, 63, 64, 65, 66, 67,
  258. 68, 69, 70, 71, 72, 73, 74, 75, 76, 77,
  259. 78, 79, 80, 81, 82, 83, 84, 85, 86, 87,
  260. 88, 89, 90, 91, 92, 93, 94, 95, 96, 97,
  261. 98, 99, 100, 101, 102, 103, 104, 105, 106, 107,
  262. 108, 109, 110, 111, 112, 113, 114, 115, 116, 117,
  263. 118, 119, 120, 121, 122, 123, 124, 125, 126, 127,
  264. },
  265. .oobfree = {
  266. {.offset = 2, .length = 46, },
  267. },
  268. #endif
  269. };
  270. #if defined CONFIG_KEYSTONE_RBL_NAND
  271. static struct nand_ecclayout nand_keystone_rbl_4bit_layout_oobfirst = {
  272. #if defined(CONFIG_SYS_NAND_PAGE_2K)
  273. .eccbytes = 40,
  274. .eccpos = {
  275. 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,
  276. 22, 23, 24, 25, 26, 27, 28, 29, 30, 31,
  277. 38, 39, 40, 41, 42, 43, 44, 45, 46, 47,
  278. 54, 55, 56, 57, 58, 59, 60, 61, 62, 63,
  279. },
  280. .oobfree = {
  281. {.offset = 2, .length = 4, },
  282. {.offset = 16, .length = 6, },
  283. {.offset = 32, .length = 6, },
  284. {.offset = 48, .length = 6, },
  285. },
  286. #elif defined(CONFIG_SYS_NAND_PAGE_4K)
  287. .eccbytes = 80,
  288. .eccpos = {
  289. 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,
  290. 22, 23, 24, 25, 26, 27, 28, 29, 30, 31,
  291. 38, 39, 40, 41, 42, 43, 44, 45, 46, 47,
  292. 54, 55, 56, 57, 58, 59, 60, 61, 62, 63,
  293. 70, 71, 72, 73, 74, 75, 76, 77, 78, 79,
  294. 86, 87, 88, 89, 90, 91, 92, 93, 94, 95,
  295. 102, 103, 104, 105, 106, 107, 108, 109, 110, 111,
  296. 118, 119, 120, 121, 122, 123, 124, 125, 126, 127,
  297. },
  298. .oobfree = {
  299. {.offset = 2, .length = 4, },
  300. {.offset = 16, .length = 6, },
  301. {.offset = 32, .length = 6, },
  302. {.offset = 48, .length = 6, },
  303. {.offset = 64, .length = 6, },
  304. {.offset = 80, .length = 6, },
  305. {.offset = 96, .length = 6, },
  306. {.offset = 112, .length = 6, },
  307. },
  308. #endif
  309. };
  310. #ifdef CONFIG_SYS_NAND_PAGE_2K
  311. #define CONFIG_KEYSTONE_NAND_MAX_RBL_PAGE CONFIG_KEYSTONE_NAND_MAX_RBL_SIZE >> 11
  312. #elif defined(CONFIG_SYS_NAND_PAGE_4K)
  313. #define CONFIG_KEYSTONE_NAND_MAX_RBL_PAGE CONFIG_KEYSTONE_NAND_MAX_RBL_SIZE >> 12
  314. #endif
  315. /**
  316. * nand_davinci_write_page - write one page
  317. * @mtd: MTD device structure
  318. * @chip: NAND chip descriptor
  319. * @buf: the data to write
  320. * @oob_required: must write chip->oob_poi to OOB
  321. * @page: page number to write
  322. * @cached: cached programming
  323. * @raw: use _raw version of write_page
  324. */
  325. static int nand_davinci_write_page(struct mtd_info *mtd, struct nand_chip *chip,
  326. uint32_t offset, int data_len,
  327. const uint8_t *buf, int oob_required,
  328. int page, int cached, int raw)
  329. {
  330. int status;
  331. int ret = 0;
  332. struct nand_ecclayout *saved_ecc_layout;
  333. /* save current ECC layout and assign Keystone RBL ECC layout */
  334. if (page < CONFIG_KEYSTONE_NAND_MAX_RBL_PAGE) {
  335. saved_ecc_layout = chip->ecc.layout;
  336. chip->ecc.layout = &nand_keystone_rbl_4bit_layout_oobfirst;
  337. mtd->oobavail = chip->ecc.layout->oobavail;
  338. }
  339. chip->cmdfunc(mtd, NAND_CMD_SEQIN, 0x00, page);
  340. if (unlikely(raw))
  341. status = chip->ecc.write_page_raw(mtd, chip, buf, oob_required);
  342. else
  343. status = chip->ecc.write_page(mtd, chip, buf, oob_required);
  344. if (status < 0) {
  345. ret = status;
  346. goto err;
  347. }
  348. chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
  349. status = chip->waitfunc(mtd, chip);
  350. /*
  351. * See if operation failed and additional status checks are
  352. * available.
  353. */
  354. if ((status & NAND_STATUS_FAIL) && (chip->errstat))
  355. status = chip->errstat(mtd, chip, FL_WRITING, status, page);
  356. if (status & NAND_STATUS_FAIL) {
  357. ret = -EIO;
  358. goto err;
  359. }
  360. err:
  361. /* restore ECC layout */
  362. if (page < CONFIG_KEYSTONE_NAND_MAX_RBL_PAGE) {
  363. chip->ecc.layout = saved_ecc_layout;
  364. mtd->oobavail = saved_ecc_layout->oobavail;
  365. }
  366. return ret;
  367. }
  368. /**
  369. * nand_davinci_read_page_hwecc - hardware ECC based page read function
  370. * @mtd: mtd info structure
  371. * @chip: nand chip info structure
  372. * @buf: buffer to store read data
  373. * @oob_required: caller requires OOB data read to chip->oob_poi
  374. * @page: page number to read
  375. *
  376. * Not for syndrome calculating ECC controllers which need a special oob layout.
  377. */
  378. static int nand_davinci_read_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
  379. uint8_t *buf, int oob_required, int page)
  380. {
  381. int i, eccsize = chip->ecc.size;
  382. int eccbytes = chip->ecc.bytes;
  383. int eccsteps = chip->ecc.steps;
  384. uint32_t *eccpos;
  385. uint8_t *p = buf;
  386. uint8_t *ecc_code = chip->buffers->ecccode;
  387. uint8_t *ecc_calc = chip->buffers->ecccalc;
  388. struct nand_ecclayout *saved_ecc_layout = chip->ecc.layout;
  389. /* save current ECC layout and assign Keystone RBL ECC layout */
  390. if (page < CONFIG_KEYSTONE_NAND_MAX_RBL_PAGE) {
  391. chip->ecc.layout = &nand_keystone_rbl_4bit_layout_oobfirst;
  392. mtd->oobavail = chip->ecc.layout->oobavail;
  393. }
  394. eccpos = chip->ecc.layout->eccpos;
  395. /* Read the OOB area first */
  396. chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page);
  397. chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
  398. chip->cmdfunc(mtd, NAND_CMD_READ0, 0, page);
  399. for (i = 0; i < chip->ecc.total; i++)
  400. ecc_code[i] = chip->oob_poi[eccpos[i]];
  401. for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
  402. int stat;
  403. chip->ecc.hwctl(mtd, NAND_ECC_READ);
  404. chip->read_buf(mtd, p, eccsize);
  405. chip->ecc.calculate(mtd, p, &ecc_calc[i]);
  406. stat = chip->ecc.correct(mtd, p, &ecc_code[i], NULL);
  407. if (stat < 0)
  408. mtd->ecc_stats.failed++;
  409. else
  410. mtd->ecc_stats.corrected += stat;
  411. }
  412. /* restore ECC layout */
  413. if (page < CONFIG_KEYSTONE_NAND_MAX_RBL_PAGE) {
  414. chip->ecc.layout = saved_ecc_layout;
  415. mtd->oobavail = saved_ecc_layout->oobavail;
  416. }
  417. return 0;
  418. }
  419. #endif /* CONFIG_KEYSTONE_RBL_NAND */
  420. static void nand_davinci_4bit_enable_hwecc(struct mtd_info *mtd, int mode)
  421. {
  422. u32 val;
  423. switch (mode) {
  424. case NAND_ECC_WRITE:
  425. case NAND_ECC_READ:
  426. /*
  427. * Start a new ECC calculation for reading or writing 512 bytes
  428. * of data.
  429. */
  430. val = __raw_readl(&davinci_emif_regs->nandfcr);
  431. val &= ~DAVINCI_NANDFCR_4BIT_ECC_SEL_MASK;
  432. val |= DAVINCI_NANDFCR_NAND_ENABLE(CONFIG_SYS_NAND_CS);
  433. val |= DAVINCI_NANDFCR_4BIT_ECC_SEL(CONFIG_SYS_NAND_CS);
  434. val |= DAVINCI_NANDFCR_4BIT_ECC_START;
  435. __raw_writel(val, &davinci_emif_regs->nandfcr);
  436. break;
  437. case NAND_ECC_READSYN:
  438. val = __raw_readl(&davinci_emif_regs->nand4bitecc[0]);
  439. break;
  440. default:
  441. break;
  442. }
  443. }
  444. static u32 nand_davinci_4bit_readecc(struct mtd_info *mtd, unsigned int ecc[4])
  445. {
  446. int i;
  447. for (i = 0; i < 4; i++) {
  448. ecc[i] = __raw_readl(&davinci_emif_regs->nand4bitecc[i]) &
  449. NAND_4BITECC_MASK;
  450. }
  451. return 0;
  452. }
  453. static int nand_davinci_4bit_calculate_ecc(struct mtd_info *mtd,
  454. const uint8_t *dat,
  455. uint8_t *ecc_code)
  456. {
  457. unsigned int hw_4ecc[4];
  458. unsigned int i;
  459. nand_davinci_4bit_readecc(mtd, hw_4ecc);
  460. /*Convert 10 bit ecc value to 8 bit */
  461. for (i = 0; i < 2; i++) {
  462. unsigned int hw_ecc_low = hw_4ecc[i * 2];
  463. unsigned int hw_ecc_hi = hw_4ecc[(i * 2) + 1];
  464. /* Take first 8 bits from val1 (count1=0) or val5 (count1=1) */
  465. *ecc_code++ = hw_ecc_low & 0xFF;
  466. /*
  467. * Take 2 bits as LSB bits from val1 (count1=0) or val5
  468. * (count1=1) and 6 bits from val2 (count1=0) or
  469. * val5 (count1=1)
  470. */
  471. *ecc_code++ =
  472. ((hw_ecc_low >> 8) & 0x3) | ((hw_ecc_low >> 14) & 0xFC);
  473. /*
  474. * Take 4 bits from val2 (count1=0) or val5 (count1=1) and
  475. * 4 bits from val3 (count1=0) or val6 (count1=1)
  476. */
  477. *ecc_code++ =
  478. ((hw_ecc_low >> 22) & 0xF) | ((hw_ecc_hi << 4) & 0xF0);
  479. /*
  480. * Take 6 bits from val3(count1=0) or val6 (count1=1) and
  481. * 2 bits from val4 (count1=0) or val7 (count1=1)
  482. */
  483. *ecc_code++ =
  484. ((hw_ecc_hi >> 4) & 0x3F) | ((hw_ecc_hi >> 10) & 0xC0);
  485. /* Take 8 bits from val4 (count1=0) or val7 (count1=1) */
  486. *ecc_code++ = (hw_ecc_hi >> 18) & 0xFF;
  487. }
  488. return 0;
  489. }
  490. static int nand_davinci_4bit_correct_data(struct mtd_info *mtd, uint8_t *dat,
  491. uint8_t *read_ecc, uint8_t *calc_ecc)
  492. {
  493. int i;
  494. unsigned int hw_4ecc[4];
  495. unsigned int iserror;
  496. unsigned short *ecc16;
  497. unsigned int numerrors, erroraddress, errorvalue;
  498. u32 val;
  499. /*
  500. * Check for an ECC where all bytes are 0xFF. If this is the case, we
  501. * will assume we are looking at an erased page and we should ignore
  502. * the ECC.
  503. */
  504. for (i = 0; i < 10; i++) {
  505. if (read_ecc[i] != 0xFF)
  506. break;
  507. }
  508. if (i == 10)
  509. return 0;
  510. /* Convert 8 bit in to 10 bit */
  511. ecc16 = (unsigned short *)&read_ecc[0];
  512. /*
  513. * Write the parity values in the NAND Flash 4-bit ECC Load register.
  514. * Write each parity value one at a time starting from 4bit_ecc_val8
  515. * to 4bit_ecc_val1.
  516. */
  517. /*Take 2 bits from 8th byte and 8 bits from 9th byte */
  518. __raw_writel(((ecc16[4]) >> 6) & 0x3FF,
  519. &davinci_emif_regs->nand4biteccload);
  520. /* Take 4 bits from 7th byte and 6 bits from 8th byte */
  521. __raw_writel((((ecc16[3]) >> 12) & 0xF) | ((((ecc16[4])) << 4) & 0x3F0),
  522. &davinci_emif_regs->nand4biteccload);
  523. /* Take 6 bits from 6th byte and 4 bits from 7th byte */
  524. __raw_writel((ecc16[3] >> 2) & 0x3FF,
  525. &davinci_emif_regs->nand4biteccload);
  526. /* Take 8 bits from 5th byte and 2 bits from 6th byte */
  527. __raw_writel(((ecc16[2]) >> 8) | ((((ecc16[3])) << 8) & 0x300),
  528. &davinci_emif_regs->nand4biteccload);
  529. /*Take 2 bits from 3rd byte and 8 bits from 4th byte */
  530. __raw_writel((((ecc16[1]) >> 14) & 0x3) | ((((ecc16[2])) << 2) & 0x3FC),
  531. &davinci_emif_regs->nand4biteccload);
  532. /* Take 4 bits form 2nd bytes and 6 bits from 3rd bytes */
  533. __raw_writel(((ecc16[1]) >> 4) & 0x3FF,
  534. &davinci_emif_regs->nand4biteccload);
  535. /* Take 6 bits from 1st byte and 4 bits from 2nd byte */
  536. __raw_writel((((ecc16[0]) >> 10) & 0x3F) | (((ecc16[1]) << 6) & 0x3C0),
  537. &davinci_emif_regs->nand4biteccload);
  538. /* Take 10 bits from 0th and 1st bytes */
  539. __raw_writel((ecc16[0]) & 0x3FF,
  540. &davinci_emif_regs->nand4biteccload);
  541. /*
  542. * Perform a dummy read to the EMIF Revision Code and Status register.
  543. * This is required to ensure time for syndrome calculation after
  544. * writing the ECC values in previous step.
  545. */
  546. val = __raw_readl(&davinci_emif_regs->nandfsr);
  547. /*
  548. * Read the syndrome from the NAND Flash 4-Bit ECC 1-4 registers.
  549. * A syndrome value of 0 means no bit errors. If the syndrome is
  550. * non-zero then go further otherwise return.
  551. */
  552. nand_davinci_4bit_readecc(mtd, hw_4ecc);
  553. if (!(hw_4ecc[0] | hw_4ecc[1] | hw_4ecc[2] | hw_4ecc[3]))
  554. return 0;
  555. /*
  556. * Clear any previous address calculation by doing a dummy read of an
  557. * error address register.
  558. */
  559. val = __raw_readl(&davinci_emif_regs->nanderradd1);
  560. /*
  561. * Set the addr_calc_st bit(bit no 13) in the NAND Flash Control
  562. * register to 1.
  563. */
  564. __raw_writel(DAVINCI_NANDFCR_4BIT_CALC_START,
  565. &davinci_emif_regs->nandfcr);
  566. /*
  567. * Wait for the corr_state field (bits 8 to 11) in the
  568. * NAND Flash Status register to be not equal to 0x0, 0x1, 0x2, or 0x3.
  569. * Otherwise ECC calculation has not even begun and the next loop might
  570. * fail because of a false positive!
  571. */
  572. i = NAND_TIMEOUT;
  573. do {
  574. val = __raw_readl(&davinci_emif_regs->nandfsr);
  575. val &= 0xc00;
  576. i--;
  577. } while ((i > 0) && !val);
  578. /*
  579. * Wait for the corr_state field (bits 8 to 11) in the
  580. * NAND Flash Status register to be equal to 0x0, 0x1, 0x2, or 0x3.
  581. */
  582. i = NAND_TIMEOUT;
  583. do {
  584. val = __raw_readl(&davinci_emif_regs->nandfsr);
  585. val &= 0xc00;
  586. i--;
  587. } while ((i > 0) && val);
  588. iserror = __raw_readl(&davinci_emif_regs->nandfsr);
  589. iserror &= EMIF_NANDFSR_ECC_STATE_MASK;
  590. iserror = iserror >> 8;
  591. /*
  592. * ECC_STATE_TOO_MANY_ERRS (0x1) means errors cannot be
  593. * corrected (five or more errors). The number of errors
  594. * calculated (err_num field) differs from the number of errors
  595. * searched. ECC_STATE_ERR_CORR_COMP_P (0x2) means error
  596. * correction complete (errors on bit 8 or 9).
  597. * ECC_STATE_ERR_CORR_COMP_N (0x3) means error correction
  598. * complete (error exists).
  599. */
  600. if (iserror == ECC_STATE_NO_ERR) {
  601. val = __raw_readl(&davinci_emif_regs->nanderrval1);
  602. return 0;
  603. } else if (iserror == ECC_STATE_TOO_MANY_ERRS) {
  604. val = __raw_readl(&davinci_emif_regs->nanderrval1);
  605. return -1;
  606. }
  607. numerrors = ((__raw_readl(&davinci_emif_regs->nandfsr) >> 16)
  608. & 0x3) + 1;
  609. /* Read the error address, error value and correct */
  610. for (i = 0; i < numerrors; i++) {
  611. if (i > 1) {
  612. erroraddress =
  613. ((__raw_readl(&davinci_emif_regs->nanderradd2) >>
  614. (16 * (i & 1))) & 0x3FF);
  615. erroraddress = ((512 + 7) - erroraddress);
  616. errorvalue =
  617. ((__raw_readl(&davinci_emif_regs->nanderrval2) >>
  618. (16 * (i & 1))) & 0xFF);
  619. } else {
  620. erroraddress =
  621. ((__raw_readl(&davinci_emif_regs->nanderradd1) >>
  622. (16 * (i & 1))) & 0x3FF);
  623. erroraddress = ((512 + 7) - erroraddress);
  624. errorvalue =
  625. ((__raw_readl(&davinci_emif_regs->nanderrval1) >>
  626. (16 * (i & 1))) & 0xFF);
  627. }
  628. /* xor the corrupt data with error value */
  629. if (erroraddress < 512)
  630. dat[erroraddress] ^= errorvalue;
  631. }
  632. return numerrors;
  633. }
  634. #endif /* CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST */
  635. static int nand_davinci_dev_ready(struct mtd_info *mtd)
  636. {
  637. return __raw_readl(&davinci_emif_regs->nandfsr) & 0x1;
  638. }
  639. static void nand_flash_init(void)
  640. {
  641. /* This is for DM6446 EVM and *very* similar. DO NOT GROW THIS!
  642. * Instead, have your board_init() set EMIF timings, based on its
  643. * knowledge of the clocks and what devices are hooked up ... and
  644. * don't even do that unless no UBL handled it.
  645. */
  646. #ifdef CONFIG_SOC_DM644X
  647. u_int32_t acfg1 = 0x3ffffffc;
  648. /*------------------------------------------------------------------*
  649. * NAND FLASH CHIP TIMEOUT @ 459 MHz *
  650. * *
  651. * AEMIF.CLK freq = PLL1/6 = 459/6 = 76.5 MHz *
  652. * AEMIF.CLK period = 1/76.5 MHz = 13.1 ns *
  653. * *
  654. *------------------------------------------------------------------*/
  655. acfg1 = 0
  656. | (0 << 31) /* selectStrobe */
  657. | (0 << 30) /* extWait */
  658. | (1 << 26) /* writeSetup 10 ns */
  659. | (3 << 20) /* writeStrobe 40 ns */
  660. | (1 << 17) /* writeHold 10 ns */
  661. | (1 << 13) /* readSetup 10 ns */
  662. | (5 << 7) /* readStrobe 60 ns */
  663. | (1 << 4) /* readHold 10 ns */
  664. | (3 << 2) /* turnAround ?? ns */
  665. | (0 << 0) /* asyncSize 8-bit bus */
  666. ;
  667. __raw_writel(acfg1, &davinci_emif_regs->ab1cr); /* CS2 */
  668. /* NAND flash on CS2 */
  669. __raw_writel(0x00000101, &davinci_emif_regs->nandfcr);
  670. #endif
  671. }
  672. void davinci_nand_init(struct nand_chip *nand)
  673. {
  674. #if defined CONFIG_KEYSTONE_RBL_NAND
  675. int i;
  676. struct nand_ecclayout *layout;
  677. layout = &nand_keystone_rbl_4bit_layout_oobfirst;
  678. layout->oobavail = 0;
  679. for (i = 0; layout->oobfree[i].length &&
  680. i < ARRAY_SIZE(layout->oobfree); i++)
  681. layout->oobavail += layout->oobfree[i].length;
  682. nand->write_page = nand_davinci_write_page;
  683. nand->ecc.read_page = nand_davinci_read_page_hwecc;
  684. #endif
  685. nand->chip_delay = 0;
  686. #ifdef CONFIG_SYS_NAND_USE_FLASH_BBT
  687. nand->bbt_options |= NAND_BBT_USE_FLASH;
  688. #endif
  689. #ifdef CONFIG_SYS_NAND_NO_SUBPAGE_WRITE
  690. nand->options |= NAND_NO_SUBPAGE_WRITE;
  691. #endif
  692. #ifdef CONFIG_SYS_NAND_HW_ECC
  693. nand->ecc.mode = NAND_ECC_HW;
  694. nand->ecc.size = 512;
  695. nand->ecc.bytes = 3;
  696. nand->ecc.strength = 1;
  697. nand->ecc.calculate = nand_davinci_calculate_ecc;
  698. nand->ecc.correct = nand_davinci_correct_data;
  699. nand->ecc.hwctl = nand_davinci_enable_hwecc;
  700. #else
  701. nand->ecc.mode = NAND_ECC_SOFT;
  702. #endif /* CONFIG_SYS_NAND_HW_ECC */
  703. #ifdef CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST
  704. nand->ecc.mode = NAND_ECC_HW_OOB_FIRST;
  705. nand->ecc.size = 512;
  706. nand->ecc.bytes = 10;
  707. nand->ecc.strength = 4;
  708. nand->ecc.calculate = nand_davinci_4bit_calculate_ecc;
  709. nand->ecc.correct = nand_davinci_4bit_correct_data;
  710. nand->ecc.hwctl = nand_davinci_4bit_enable_hwecc;
  711. nand->ecc.layout = &nand_davinci_4bit_layout_oobfirst;
  712. #endif
  713. /* Set address of hardware control function */
  714. nand->cmd_ctrl = nand_davinci_hwcontrol;
  715. nand->read_buf = nand_davinci_read_buf;
  716. nand->write_buf = nand_davinci_write_buf;
  717. nand->dev_ready = nand_davinci_dev_ready;
  718. nand_flash_init();
  719. }
  720. int board_nand_init(struct nand_chip *chip) __attribute__((weak));
  721. int board_nand_init(struct nand_chip *chip)
  722. {
  723. davinci_nand_init(chip);
  724. return 0;
  725. }