arasan_nfc.c 31 KB

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  1. /*
  2. * Arasan NAND Flash Controller Driver
  3. *
  4. * Copyright (C) 2014 - 2015 Xilinx, Inc.
  5. *
  6. * SPDX-License-Identifier: GPL-2.0+
  7. */
  8. #include <common.h>
  9. #include <malloc.h>
  10. #include <asm/io.h>
  11. #include <asm/errno.h>
  12. #include <linux/mtd/mtd.h>
  13. #include <linux/mtd/nand.h>
  14. #include <linux/mtd/partitions.h>
  15. #include <linux/mtd/nand_ecc.h>
  16. #include <asm/arch/hardware.h>
  17. #include <asm/arch/sys_proto.h>
  18. #include <nand.h>
  19. struct arasan_nand_info {
  20. void __iomem *nand_base;
  21. u32 page;
  22. };
  23. struct nand_regs {
  24. u32 pkt_reg;
  25. u32 memadr_reg1;
  26. u32 memadr_reg2;
  27. u32 cmd_reg;
  28. u32 pgm_reg;
  29. u32 intsts_enr;
  30. u32 intsig_enr;
  31. u32 intsts_reg;
  32. u32 rdy_busy;
  33. u32 cms_sysadr_reg;
  34. u32 flash_sts_reg;
  35. u32 tmg_reg;
  36. u32 buf_dataport;
  37. u32 ecc_reg;
  38. u32 ecc_errcnt_reg;
  39. u32 ecc_sprcmd_reg;
  40. u32 errcnt_1bitreg;
  41. u32 errcnt_2bitreg;
  42. u32 errcnt_3bitreg;
  43. u32 errcnt_4bitreg;
  44. u32 dma_sysadr0_reg;
  45. u32 dma_bufbdry_reg;
  46. u32 cpu_rls_reg;
  47. u32 errcnt_5bitreg;
  48. u32 errcnt_6bitreg;
  49. u32 errcnt_7bitreg;
  50. u32 errcnt_8bitreg;
  51. u32 data_if_reg;
  52. };
  53. #define arasan_nand_base ((struct nand_regs __iomem *)ARASAN_NAND_BASEADDR)
  54. struct arasan_nand_command_format {
  55. u8 cmd1;
  56. u8 cmd2;
  57. u8 addr_cycles;
  58. u32 pgm;
  59. };
  60. #define ONDIE_ECC_FEATURE_ADDR 0x90
  61. #define ARASAN_PROG_RD_MASK 0x00000001
  62. #define ARASAN_PROG_BLK_ERS_MASK 0x00000004
  63. #define ARASAN_PROG_RD_ID_MASK 0x00000040
  64. #define ARASAN_PROG_RD_STS_MASK 0x00000008
  65. #define ARASAN_PROG_PG_PROG_MASK 0x00000010
  66. #define ARASAN_PROG_RD_PARAM_PG_MASK 0x00000080
  67. #define ARASAN_PROG_RST_MASK 0x00000100
  68. #define ARASAN_PROG_GET_FTRS_MASK 0x00000200
  69. #define ARASAN_PROG_SET_FTRS_MASK 0x00000400
  70. #define ARASAN_PROG_CHNG_ROWADR_END_MASK 0x00400000
  71. #define ARASAN_NAND_CMD_ECC_ON_MASK 0x80000000
  72. #define ARASAN_NAND_CMD_CMD12_MASK 0xFFFF
  73. #define ARASAN_NAND_CMD_PG_SIZE_MASK 0x3800000
  74. #define ARASAN_NAND_CMD_PG_SIZE_SHIFT 23
  75. #define ARASAN_NAND_CMD_CMD2_SHIFT 8
  76. #define ARASAN_NAND_CMD_ADDR_CYCL_MASK 0x70000000
  77. #define ARASAN_NAND_CMD_ADDR_CYCL_SHIFT 28
  78. #define ARASAN_NAND_MEM_ADDR1_PAGE_MASK 0xFFFF0000
  79. #define ARASAN_NAND_MEM_ADDR1_COL_MASK 0xFFFF
  80. #define ARASAN_NAND_MEM_ADDR1_PAGE_SHIFT 16
  81. #define ARASAN_NAND_MEM_ADDR2_PAGE_MASK 0xFF
  82. #define ARASAN_NAND_MEM_ADDR2_CS_MASK 0xC0000000
  83. #define ARASAN_NAND_MEM_ADDR2_BCH_MASK 0xE000000
  84. #define ARASAN_NAND_MEM_ADDR2_BCH_SHIFT 25
  85. #define ARASAN_NAND_INT_STS_ERR_EN_MASK 0x10
  86. #define ARASAN_NAND_INT_STS_MUL_BIT_ERR_MASK 0x08
  87. #define ARASAN_NAND_INT_STS_BUF_RD_RDY_MASK 0x02
  88. #define ARASAN_NAND_INT_STS_BUF_WR_RDY_MASK 0x01
  89. #define ARASAN_NAND_INT_STS_XFR_CMPLT_MASK 0x04
  90. #define ARASAN_NAND_PKT_REG_PKT_CNT_MASK 0xFFF000
  91. #define ARASAN_NAND_PKT_REG_PKT_SIZE_MASK 0x7FF
  92. #define ARASAN_NAND_PKT_REG_PKT_CNT_SHFT 12
  93. #define ARASAN_NAND_ROW_ADDR_CYCL_MASK 0x0F
  94. #define ARASAN_NAND_COL_ADDR_CYCL_MASK 0xF0
  95. #define ARASAN_NAND_COL_ADDR_CYCL_SHIFT 4
  96. #define ARASAN_NAND_ECC_SIZE_SHIFT 16
  97. #define ARASAN_NAND_ECC_BCH_SHIFT 27
  98. #define ARASAN_NAND_PKTSIZE_1K 1024
  99. #define ARASAN_NAND_PKTSIZE_512 512
  100. #define ARASAN_NAND_POLL_TIMEOUT 1000000
  101. #define ARASAN_NAND_INVALID_ADDR_CYCL 0xFF
  102. #define ERR_ADDR_CYCLE -1
  103. #define READ_BUFF_SIZE 0x4000
  104. static struct arasan_nand_command_format *curr_cmd;
  105. enum addr_cycles {
  106. NAND_ADDR_CYCL_NONE,
  107. NAND_ADDR_CYCL_ONE,
  108. NAND_ADDR_CYCL_ROW,
  109. NAND_ADDR_CYCL_COL,
  110. NAND_ADDR_CYCL_BOTH,
  111. };
  112. static struct arasan_nand_command_format arasan_nand_commands[] = {
  113. {NAND_CMD_READ0, NAND_CMD_READSTART, NAND_ADDR_CYCL_BOTH,
  114. ARASAN_PROG_RD_MASK},
  115. {NAND_CMD_RNDOUT, NAND_CMD_RNDOUTSTART, NAND_ADDR_CYCL_COL,
  116. ARASAN_PROG_RD_MASK},
  117. {NAND_CMD_READID, NAND_CMD_NONE, NAND_ADDR_CYCL_ONE,
  118. ARASAN_PROG_RD_ID_MASK},
  119. {NAND_CMD_STATUS, NAND_CMD_NONE, NAND_ADDR_CYCL_NONE,
  120. ARASAN_PROG_RD_STS_MASK},
  121. {NAND_CMD_SEQIN, NAND_CMD_PAGEPROG, NAND_ADDR_CYCL_BOTH,
  122. ARASAN_PROG_PG_PROG_MASK},
  123. {NAND_CMD_RNDIN, NAND_CMD_NONE, NAND_ADDR_CYCL_COL,
  124. ARASAN_PROG_CHNG_ROWADR_END_MASK},
  125. {NAND_CMD_ERASE1, NAND_CMD_ERASE2, NAND_ADDR_CYCL_ROW,
  126. ARASAN_PROG_BLK_ERS_MASK},
  127. {NAND_CMD_RESET, NAND_CMD_NONE, NAND_ADDR_CYCL_NONE,
  128. ARASAN_PROG_RST_MASK},
  129. {NAND_CMD_PARAM, NAND_CMD_NONE, NAND_ADDR_CYCL_ONE,
  130. ARASAN_PROG_RD_PARAM_PG_MASK},
  131. {NAND_CMD_GET_FEATURES, NAND_CMD_NONE, NAND_ADDR_CYCL_ONE,
  132. ARASAN_PROG_GET_FTRS_MASK},
  133. {NAND_CMD_SET_FEATURES, NAND_CMD_NONE, NAND_ADDR_CYCL_ONE,
  134. ARASAN_PROG_SET_FTRS_MASK},
  135. {NAND_CMD_NONE, NAND_CMD_NONE, NAND_ADDR_CYCL_NONE, 0},
  136. };
  137. struct arasan_ecc_matrix {
  138. u32 pagesize;
  139. u32 ecc_codeword_size;
  140. u8 eccbits;
  141. u8 bch;
  142. u8 bchval;
  143. u16 eccaddr;
  144. u16 eccsize;
  145. };
  146. static const struct arasan_ecc_matrix ecc_matrix[] = {
  147. {512, 512, 1, 0, 0, 0x20D, 0x3},
  148. {512, 512, 4, 1, 3, 0x209, 0x7},
  149. {512, 512, 8, 1, 2, 0x203, 0xD},
  150. /*
  151. * 2K byte page
  152. */
  153. {2048, 512, 1, 0, 0, 0x834, 0xC},
  154. {2048, 512, 4, 1, 3, 0x826, 0x1A},
  155. {2048, 512, 8, 1, 2, 0x80c, 0x34},
  156. {2048, 512, 12, 1, 1, 0x822, 0x4E},
  157. {2048, 512, 16, 1, 0, 0x808, 0x68},
  158. {2048, 1024, 24, 1, 4, 0x81c, 0x54},
  159. /*
  160. * 4K byte page
  161. */
  162. {4096, 512, 1, 0, 0, 0x1068, 0x18},
  163. {4096, 512, 4, 1, 3, 0x104c, 0x34},
  164. {4096, 512, 8, 1, 2, 0x1018, 0x68},
  165. {4096, 512, 12, 1, 1, 0x1044, 0x9C},
  166. {4096, 512, 16, 1, 0, 0x1010, 0xD0},
  167. {4096, 1024, 24, 1, 4, 0x1038, 0xA8},
  168. /*
  169. * 8K byte page
  170. */
  171. {8192, 512, 1, 0, 0, 0x20d0, 0x30},
  172. {8192, 512, 4, 1, 3, 0x2098, 0x68},
  173. {8192, 512, 8, 1, 2, 0x2030, 0xD0},
  174. {8192, 512, 12, 1, 1, 0x2088, 0x138},
  175. {8192, 512, 16, 1, 0, 0x2020, 0x1A0},
  176. {8192, 1024, 24, 1, 4, 0x2070, 0x150},
  177. /*
  178. * 16K byte page
  179. */
  180. {16384, 512, 1, 0, 0, 0x4460, 0x60},
  181. {16384, 512, 4, 1, 3, 0x43f0, 0xD0},
  182. {16384, 512, 8, 1, 2, 0x4320, 0x1A0},
  183. {16384, 512, 12, 1, 1, 0x4250, 0x270},
  184. {16384, 512, 16, 1, 0, 0x4180, 0x340},
  185. {16384, 1024, 24, 1, 4, 0x4220, 0x2A0}
  186. };
  187. static u8 buf_data[READ_BUFF_SIZE];
  188. static u32 buf_index;
  189. static struct nand_ecclayout nand_oob;
  190. static struct nand_chip nand_chip[CONFIG_SYS_MAX_NAND_DEVICE];
  191. static void arasan_nand_select_chip(struct mtd_info *mtd, int chip)
  192. {
  193. }
  194. static void arasan_nand_enable_ecc(void)
  195. {
  196. u32 reg_val;
  197. reg_val = readl(&arasan_nand_base->cmd_reg);
  198. reg_val |= ARASAN_NAND_CMD_ECC_ON_MASK;
  199. writel(reg_val, &arasan_nand_base->cmd_reg);
  200. }
  201. static u8 arasan_nand_get_addrcycle(struct mtd_info *mtd)
  202. {
  203. u8 addrcycles;
  204. struct nand_chip *chip = mtd_to_nand(mtd);
  205. switch (curr_cmd->addr_cycles) {
  206. case NAND_ADDR_CYCL_NONE:
  207. addrcycles = 0;
  208. break;
  209. case NAND_ADDR_CYCL_ONE:
  210. addrcycles = 1;
  211. break;
  212. case NAND_ADDR_CYCL_ROW:
  213. addrcycles = chip->onfi_params.addr_cycles &
  214. ARASAN_NAND_ROW_ADDR_CYCL_MASK;
  215. break;
  216. case NAND_ADDR_CYCL_COL:
  217. addrcycles = (chip->onfi_params.addr_cycles &
  218. ARASAN_NAND_COL_ADDR_CYCL_MASK) >>
  219. ARASAN_NAND_COL_ADDR_CYCL_SHIFT;
  220. break;
  221. case NAND_ADDR_CYCL_BOTH:
  222. addrcycles = chip->onfi_params.addr_cycles &
  223. ARASAN_NAND_ROW_ADDR_CYCL_MASK;
  224. addrcycles += (chip->onfi_params.addr_cycles &
  225. ARASAN_NAND_COL_ADDR_CYCL_MASK) >>
  226. ARASAN_NAND_COL_ADDR_CYCL_SHIFT;
  227. break;
  228. default:
  229. addrcycles = ARASAN_NAND_INVALID_ADDR_CYCL;
  230. break;
  231. }
  232. return addrcycles;
  233. }
  234. static int arasan_nand_read_page(struct mtd_info *mtd, u8 *buf, u32 size)
  235. {
  236. struct nand_chip *chip = mtd_to_nand(mtd);
  237. u32 reg_val, i, pktsize, pktnum;
  238. u32 *bufptr = (u32 *)buf;
  239. u32 timeout;
  240. u32 rdcount = 0;
  241. u8 addr_cycles;
  242. if (chip->ecc_step_ds >= ARASAN_NAND_PKTSIZE_1K)
  243. pktsize = ARASAN_NAND_PKTSIZE_1K;
  244. else
  245. pktsize = ARASAN_NAND_PKTSIZE_512;
  246. if (size % pktsize)
  247. pktnum = size/pktsize + 1;
  248. else
  249. pktnum = size/pktsize;
  250. reg_val = readl(&arasan_nand_base->intsts_enr);
  251. reg_val |= ARASAN_NAND_INT_STS_ERR_EN_MASK |
  252. ARASAN_NAND_INT_STS_MUL_BIT_ERR_MASK;
  253. writel(reg_val, &arasan_nand_base->intsts_enr);
  254. reg_val = readl(&arasan_nand_base->pkt_reg);
  255. reg_val &= ~(ARASAN_NAND_PKT_REG_PKT_CNT_MASK |
  256. ARASAN_NAND_PKT_REG_PKT_SIZE_MASK);
  257. reg_val |= (pktnum << ARASAN_NAND_PKT_REG_PKT_CNT_SHFT) |
  258. pktsize;
  259. writel(reg_val, &arasan_nand_base->pkt_reg);
  260. arasan_nand_enable_ecc();
  261. addr_cycles = arasan_nand_get_addrcycle(mtd);
  262. if (addr_cycles == ARASAN_NAND_INVALID_ADDR_CYCL)
  263. return ERR_ADDR_CYCLE;
  264. writel((NAND_CMD_RNDOUTSTART << ARASAN_NAND_CMD_CMD2_SHIFT) |
  265. NAND_CMD_RNDOUT | (addr_cycles <<
  266. ARASAN_NAND_CMD_ADDR_CYCL_SHIFT),
  267. &arasan_nand_base->ecc_sprcmd_reg);
  268. writel(curr_cmd->pgm, &arasan_nand_base->pgm_reg);
  269. while (rdcount < pktnum) {
  270. timeout = ARASAN_NAND_POLL_TIMEOUT;
  271. while (!(readl(&arasan_nand_base->intsts_reg) &
  272. ARASAN_NAND_INT_STS_BUF_RD_RDY_MASK) && timeout) {
  273. udelay(1);
  274. timeout--;
  275. }
  276. if (!timeout) {
  277. puts("arasan_read_page: timedout:Buff RDY\n");
  278. return -ETIMEDOUT;
  279. }
  280. rdcount++;
  281. if (pktnum == rdcount) {
  282. reg_val = readl(&arasan_nand_base->intsts_enr);
  283. reg_val |= ARASAN_NAND_INT_STS_XFR_CMPLT_MASK;
  284. writel(reg_val, &arasan_nand_base->intsts_enr);
  285. } else {
  286. reg_val = readl(&arasan_nand_base->intsts_enr);
  287. writel(reg_val | ARASAN_NAND_INT_STS_BUF_RD_RDY_MASK,
  288. &arasan_nand_base->intsts_enr);
  289. }
  290. reg_val = readl(&arasan_nand_base->intsts_reg);
  291. writel(reg_val | ARASAN_NAND_INT_STS_BUF_RD_RDY_MASK,
  292. &arasan_nand_base->intsts_reg);
  293. for (i = 0; i < pktsize/4; i++)
  294. bufptr[i] = readl(&arasan_nand_base->buf_dataport);
  295. bufptr += pktsize/4;
  296. if (rdcount >= pktnum)
  297. break;
  298. writel(ARASAN_NAND_INT_STS_BUF_RD_RDY_MASK,
  299. &arasan_nand_base->intsts_enr);
  300. }
  301. timeout = ARASAN_NAND_POLL_TIMEOUT;
  302. while (!(readl(&arasan_nand_base->intsts_reg) &
  303. ARASAN_NAND_INT_STS_XFR_CMPLT_MASK) && timeout) {
  304. udelay(1);
  305. timeout--;
  306. }
  307. if (!timeout) {
  308. puts("arasan rd_page timedout:Xfer CMPLT\n");
  309. return -ETIMEDOUT;
  310. }
  311. reg_val = readl(&arasan_nand_base->intsts_enr);
  312. writel(reg_val | ARASAN_NAND_INT_STS_XFR_CMPLT_MASK,
  313. &arasan_nand_base->intsts_enr);
  314. reg_val = readl(&arasan_nand_base->intsts_reg);
  315. writel(reg_val | ARASAN_NAND_INT_STS_XFR_CMPLT_MASK,
  316. &arasan_nand_base->intsts_reg);
  317. if (readl(&arasan_nand_base->intsts_reg) &
  318. ARASAN_NAND_INT_STS_MUL_BIT_ERR_MASK) {
  319. printf("arasan rd_page:sbiterror\n");
  320. return -1;
  321. }
  322. if (readl(&arasan_nand_base->intsts_reg) &
  323. ARASAN_NAND_INT_STS_ERR_EN_MASK) {
  324. mtd->ecc_stats.failed++;
  325. printf("arasan rd_page:multibiterror\n");
  326. return -1;
  327. }
  328. return 0;
  329. }
  330. static int arasan_nand_read_page_hwecc(struct mtd_info *mtd,
  331. struct nand_chip *chip, u8 *buf, int oob_required, int page)
  332. {
  333. int status;
  334. status = arasan_nand_read_page(mtd, buf, (mtd->writesize));
  335. if (oob_required)
  336. chip->ecc.read_oob(mtd, chip, page);
  337. return status;
  338. }
  339. static void arasan_nand_fill_tx(const u8 *buf, int len)
  340. {
  341. u32 __iomem *nand = &arasan_nand_base->buf_dataport;
  342. if (((unsigned long)buf & 0x3) != 0) {
  343. if (((unsigned long)buf & 0x1) != 0) {
  344. if (len) {
  345. writeb(*buf, nand);
  346. buf += 1;
  347. len--;
  348. }
  349. }
  350. if (((unsigned long)buf & 0x3) != 0) {
  351. if (len >= 2) {
  352. writew(*(u16 *)buf, nand);
  353. buf += 2;
  354. len -= 2;
  355. }
  356. }
  357. }
  358. while (len >= 4) {
  359. writel(*(u32 *)buf, nand);
  360. buf += 4;
  361. len -= 4;
  362. }
  363. if (len) {
  364. if (len >= 2) {
  365. writew(*(u16 *)buf, nand);
  366. buf += 2;
  367. len -= 2;
  368. }
  369. if (len)
  370. writeb(*buf, nand);
  371. }
  372. }
  373. static int arasan_nand_write_page_hwecc(struct mtd_info *mtd,
  374. struct nand_chip *chip, const u8 *buf, int oob_required)
  375. {
  376. u32 reg_val, i, pktsize, pktnum;
  377. const u32 *bufptr = (const u32 *)buf;
  378. u32 timeout = ARASAN_NAND_POLL_TIMEOUT;
  379. u32 size = mtd->writesize;
  380. u32 rdcount = 0;
  381. u8 column_addr_cycles;
  382. struct arasan_nand_info *nand = nand_get_controller_data(chip);
  383. if (chip->ecc_step_ds >= ARASAN_NAND_PKTSIZE_1K)
  384. pktsize = ARASAN_NAND_PKTSIZE_1K;
  385. else
  386. pktsize = ARASAN_NAND_PKTSIZE_512;
  387. if (size % pktsize)
  388. pktnum = size/pktsize + 1;
  389. else
  390. pktnum = size/pktsize;
  391. reg_val = readl(&arasan_nand_base->pkt_reg);
  392. reg_val &= ~(ARASAN_NAND_PKT_REG_PKT_CNT_MASK |
  393. ARASAN_NAND_PKT_REG_PKT_SIZE_MASK);
  394. reg_val |= (pktnum << ARASAN_NAND_PKT_REG_PKT_CNT_SHFT) | pktsize;
  395. writel(reg_val, &arasan_nand_base->pkt_reg);
  396. arasan_nand_enable_ecc();
  397. column_addr_cycles = (chip->onfi_params.addr_cycles &
  398. ARASAN_NAND_COL_ADDR_CYCL_MASK) >>
  399. ARASAN_NAND_COL_ADDR_CYCL_SHIFT;
  400. writel((NAND_CMD_RNDIN | (column_addr_cycles << 28)),
  401. &arasan_nand_base->ecc_sprcmd_reg);
  402. writel(curr_cmd->pgm, &arasan_nand_base->pgm_reg);
  403. while (rdcount < pktnum) {
  404. timeout = ARASAN_NAND_POLL_TIMEOUT;
  405. while (!(readl(&arasan_nand_base->intsts_reg) &
  406. ARASAN_NAND_INT_STS_BUF_WR_RDY_MASK) && timeout) {
  407. udelay(1);
  408. timeout--;
  409. }
  410. if (!timeout) {
  411. puts("arasan_write_page: timedout:Buff RDY\n");
  412. return -ETIMEDOUT;
  413. }
  414. rdcount++;
  415. if (pktnum == rdcount) {
  416. reg_val = readl(&arasan_nand_base->intsts_enr);
  417. reg_val |= ARASAN_NAND_INT_STS_XFR_CMPLT_MASK;
  418. writel(reg_val, &arasan_nand_base->intsts_enr);
  419. } else {
  420. reg_val = readl(&arasan_nand_base->intsts_enr);
  421. writel(reg_val | ARASAN_NAND_INT_STS_BUF_WR_RDY_MASK,
  422. &arasan_nand_base->intsts_enr);
  423. }
  424. reg_val = readl(&arasan_nand_base->intsts_reg);
  425. writel(reg_val | ARASAN_NAND_INT_STS_BUF_WR_RDY_MASK,
  426. &arasan_nand_base->intsts_reg);
  427. for (i = 0; i < pktsize/4; i++)
  428. writel(bufptr[i], &arasan_nand_base->buf_dataport);
  429. bufptr += pktsize/4;
  430. if (rdcount >= pktnum)
  431. break;
  432. writel(ARASAN_NAND_INT_STS_BUF_WR_RDY_MASK,
  433. &arasan_nand_base->intsts_enr);
  434. }
  435. timeout = ARASAN_NAND_POLL_TIMEOUT;
  436. while (!(readl(&arasan_nand_base->intsts_reg) &
  437. ARASAN_NAND_INT_STS_XFR_CMPLT_MASK) && timeout) {
  438. udelay(1);
  439. timeout--;
  440. }
  441. if (!timeout) {
  442. puts("arasan write_page timedout:Xfer CMPLT\n");
  443. return -ETIMEDOUT;
  444. }
  445. reg_val = readl(&arasan_nand_base->intsts_enr);
  446. writel(reg_val | ARASAN_NAND_INT_STS_XFR_CMPLT_MASK,
  447. &arasan_nand_base->intsts_enr);
  448. reg_val = readl(&arasan_nand_base->intsts_reg);
  449. writel(reg_val | ARASAN_NAND_INT_STS_XFR_CMPLT_MASK,
  450. &arasan_nand_base->intsts_reg);
  451. if (oob_required)
  452. chip->ecc.write_oob(mtd, chip, nand->page);
  453. return 0;
  454. }
  455. static int arasan_nand_read_oob(struct mtd_info *mtd, struct nand_chip *chip,
  456. int page)
  457. {
  458. chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page);
  459. chip->read_buf(mtd, chip->oob_poi, (mtd->oobsize));
  460. return 0;
  461. }
  462. static int arasan_nand_write_oob(struct mtd_info *mtd, struct nand_chip *chip,
  463. int page)
  464. {
  465. int status = 0;
  466. const u8 *buf = chip->oob_poi;
  467. chip->cmdfunc(mtd, NAND_CMD_SEQIN, mtd->writesize, page);
  468. chip->write_buf(mtd, buf, mtd->oobsize);
  469. return status;
  470. }
  471. static int arasan_nand_reset(struct arasan_nand_command_format *curr_cmd)
  472. {
  473. u32 timeout = ARASAN_NAND_POLL_TIMEOUT;
  474. u32 cmd_reg = 0;
  475. writel(ARASAN_NAND_INT_STS_XFR_CMPLT_MASK,
  476. &arasan_nand_base->intsts_enr);
  477. cmd_reg = readl(&arasan_nand_base->cmd_reg);
  478. cmd_reg &= ~ARASAN_NAND_CMD_CMD12_MASK;
  479. cmd_reg |= curr_cmd->cmd1 |
  480. (curr_cmd->cmd2 << ARASAN_NAND_CMD_CMD2_SHIFT);
  481. writel(cmd_reg, &arasan_nand_base->cmd_reg);
  482. writel(curr_cmd->pgm, &arasan_nand_base->pgm_reg);
  483. while (!(readl(&arasan_nand_base->intsts_reg) &
  484. ARASAN_NAND_INT_STS_XFR_CMPLT_MASK) && timeout) {
  485. udelay(1);
  486. timeout--;
  487. }
  488. if (!timeout) {
  489. printf("ERROR:%s timedout\n", __func__);
  490. return -ETIMEDOUT;
  491. }
  492. writel(ARASAN_NAND_INT_STS_XFR_CMPLT_MASK,
  493. &arasan_nand_base->intsts_enr);
  494. writel(ARASAN_NAND_INT_STS_XFR_CMPLT_MASK,
  495. &arasan_nand_base->intsts_reg);
  496. return 0;
  497. }
  498. static u8 arasan_nand_page(struct mtd_info *mtd)
  499. {
  500. u8 page_val = 0;
  501. switch (mtd->writesize) {
  502. case 512:
  503. page_val = 0;
  504. break;
  505. case 2048:
  506. page_val = 1;
  507. break;
  508. case 4096:
  509. page_val = 2;
  510. break;
  511. case 8192:
  512. page_val = 3;
  513. break;
  514. case 16384:
  515. page_val = 4;
  516. break;
  517. case 1024:
  518. page_val = 5;
  519. break;
  520. default:
  521. printf("%s:Pagesize>16K\n", __func__);
  522. break;
  523. }
  524. return page_val;
  525. }
  526. static int arasan_nand_send_wrcmd(struct arasan_nand_command_format *curr_cmd,
  527. int column, int page_addr, struct mtd_info *mtd)
  528. {
  529. u32 reg_val, page;
  530. u8 page_val, addr_cycles;
  531. writel(ARASAN_NAND_INT_STS_BUF_WR_RDY_MASK,
  532. &arasan_nand_base->intsts_enr);
  533. reg_val = readl(&arasan_nand_base->cmd_reg);
  534. reg_val &= ~ARASAN_NAND_CMD_CMD12_MASK;
  535. reg_val |= curr_cmd->cmd1 |
  536. (curr_cmd->cmd2 << ARASAN_NAND_CMD_CMD2_SHIFT);
  537. if (curr_cmd->cmd1 == NAND_CMD_SEQIN) {
  538. reg_val &= ~ARASAN_NAND_CMD_PG_SIZE_MASK;
  539. page_val = arasan_nand_page(mtd);
  540. reg_val |= (page_val << ARASAN_NAND_CMD_PG_SIZE_SHIFT);
  541. }
  542. reg_val &= ~ARASAN_NAND_CMD_ADDR_CYCL_MASK;
  543. addr_cycles = arasan_nand_get_addrcycle(mtd);
  544. if (addr_cycles == ARASAN_NAND_INVALID_ADDR_CYCL)
  545. return ERR_ADDR_CYCLE;
  546. reg_val |= (addr_cycles <<
  547. ARASAN_NAND_CMD_ADDR_CYCL_SHIFT);
  548. writel(reg_val, &arasan_nand_base->cmd_reg);
  549. if (page_addr == -1)
  550. page_addr = 0;
  551. page = (page_addr << ARASAN_NAND_MEM_ADDR1_PAGE_SHIFT) &
  552. ARASAN_NAND_MEM_ADDR1_PAGE_MASK;
  553. column &= ARASAN_NAND_MEM_ADDR1_COL_MASK;
  554. writel(page|column, &arasan_nand_base->memadr_reg1);
  555. reg_val = readl(&arasan_nand_base->memadr_reg2);
  556. reg_val &= ~ARASAN_NAND_MEM_ADDR2_PAGE_MASK;
  557. reg_val |= (page_addr >> ARASAN_NAND_MEM_ADDR1_PAGE_SHIFT);
  558. writel(reg_val, &arasan_nand_base->memadr_reg2);
  559. reg_val = readl(&arasan_nand_base->memadr_reg2);
  560. reg_val &= ~ARASAN_NAND_MEM_ADDR2_CS_MASK;
  561. writel(reg_val, &arasan_nand_base->memadr_reg2);
  562. return 0;
  563. }
  564. static void arasan_nand_write_buf(struct mtd_info *mtd, const u8 *buf, int len)
  565. {
  566. u32 reg_val;
  567. u32 timeout = ARASAN_NAND_POLL_TIMEOUT;
  568. reg_val = readl(&arasan_nand_base->pkt_reg);
  569. reg_val &= ~(ARASAN_NAND_PKT_REG_PKT_CNT_MASK |
  570. ARASAN_NAND_PKT_REG_PKT_SIZE_MASK);
  571. reg_val |= (1 << ARASAN_NAND_PKT_REG_PKT_CNT_SHFT) | len;
  572. writel(reg_val, &arasan_nand_base->pkt_reg);
  573. writel(curr_cmd->pgm, &arasan_nand_base->pgm_reg);
  574. while (!(readl(&arasan_nand_base->intsts_reg) &
  575. ARASAN_NAND_INT_STS_BUF_WR_RDY_MASK) && timeout) {
  576. udelay(1);
  577. timeout--;
  578. }
  579. if (!timeout)
  580. puts("ERROR:arasan_nand_write_buf timedout:Buff RDY\n");
  581. reg_val = readl(&arasan_nand_base->intsts_enr);
  582. reg_val |= ARASAN_NAND_INT_STS_XFR_CMPLT_MASK;
  583. writel(reg_val, &arasan_nand_base->intsts_enr);
  584. writel(reg_val | ARASAN_NAND_INT_STS_BUF_WR_RDY_MASK,
  585. &arasan_nand_base->intsts_enr);
  586. reg_val = readl(&arasan_nand_base->intsts_reg);
  587. writel(reg_val | ARASAN_NAND_INT_STS_BUF_WR_RDY_MASK,
  588. &arasan_nand_base->intsts_reg);
  589. arasan_nand_fill_tx(buf, len);
  590. timeout = ARASAN_NAND_POLL_TIMEOUT;
  591. while (!(readl(&arasan_nand_base->intsts_reg) &
  592. ARASAN_NAND_INT_STS_XFR_CMPLT_MASK) && timeout) {
  593. udelay(1);
  594. timeout--;
  595. }
  596. if (!timeout)
  597. puts("ERROR:arasan_nand_write_buf timedout:Xfer CMPLT\n");
  598. writel(readl(&arasan_nand_base->intsts_enr) |
  599. ARASAN_NAND_INT_STS_XFR_CMPLT_MASK,
  600. &arasan_nand_base->intsts_enr);
  601. writel(readl(&arasan_nand_base->intsts_reg) |
  602. ARASAN_NAND_INT_STS_XFR_CMPLT_MASK,
  603. &arasan_nand_base->intsts_reg);
  604. }
  605. static int arasan_nand_erase(struct arasan_nand_command_format *curr_cmd,
  606. int column, int page_addr, struct mtd_info *mtd)
  607. {
  608. u32 reg_val, page;
  609. u32 timeout = ARASAN_NAND_POLL_TIMEOUT;
  610. u8 row_addr_cycles;
  611. writel(ARASAN_NAND_INT_STS_XFR_CMPLT_MASK,
  612. &arasan_nand_base->intsts_enr);
  613. reg_val = readl(&arasan_nand_base->cmd_reg);
  614. reg_val &= ~ARASAN_NAND_CMD_CMD12_MASK;
  615. reg_val |= curr_cmd->cmd1 |
  616. (curr_cmd->cmd2 << ARASAN_NAND_CMD_CMD2_SHIFT);
  617. row_addr_cycles = arasan_nand_get_addrcycle(mtd);
  618. if (row_addr_cycles == ARASAN_NAND_INVALID_ADDR_CYCL)
  619. return ERR_ADDR_CYCLE;
  620. reg_val &= ~ARASAN_NAND_CMD_ADDR_CYCL_MASK;
  621. reg_val |= (row_addr_cycles <<
  622. ARASAN_NAND_CMD_ADDR_CYCL_SHIFT);
  623. writel(reg_val, &arasan_nand_base->cmd_reg);
  624. page = (page_addr << ARASAN_NAND_MEM_ADDR1_PAGE_SHIFT) &
  625. ARASAN_NAND_MEM_ADDR1_PAGE_MASK;
  626. column = page_addr & ARASAN_NAND_MEM_ADDR1_COL_MASK;
  627. writel(page | column, &arasan_nand_base->memadr_reg1);
  628. reg_val = readl(&arasan_nand_base->memadr_reg2);
  629. reg_val &= ~ARASAN_NAND_MEM_ADDR2_PAGE_MASK;
  630. reg_val |= (page_addr >> ARASAN_NAND_MEM_ADDR1_PAGE_SHIFT);
  631. writel(reg_val, &arasan_nand_base->memadr_reg2);
  632. reg_val = readl(&arasan_nand_base->memadr_reg2);
  633. reg_val &= ~ARASAN_NAND_MEM_ADDR2_CS_MASK;
  634. writel(reg_val, &arasan_nand_base->memadr_reg2);
  635. writel(curr_cmd->pgm, &arasan_nand_base->pgm_reg);
  636. while (!(readl(&arasan_nand_base->intsts_reg) &
  637. ARASAN_NAND_INT_STS_XFR_CMPLT_MASK) && timeout) {
  638. udelay(1);
  639. timeout--;
  640. }
  641. if (!timeout) {
  642. printf("ERROR:%s timedout:Xfer CMPLT\n", __func__);
  643. return -ETIMEDOUT;
  644. }
  645. reg_val = readl(&arasan_nand_base->intsts_enr);
  646. writel(reg_val | ARASAN_NAND_INT_STS_XFR_CMPLT_MASK,
  647. &arasan_nand_base->intsts_enr);
  648. reg_val = readl(&arasan_nand_base->intsts_reg);
  649. writel(reg_val | ARASAN_NAND_INT_STS_XFR_CMPLT_MASK,
  650. &arasan_nand_base->intsts_reg);
  651. return 0;
  652. }
  653. static int arasan_nand_read_status(struct arasan_nand_command_format *curr_cmd,
  654. int column, int page_addr, struct mtd_info *mtd)
  655. {
  656. u32 reg_val;
  657. u32 timeout = ARASAN_NAND_POLL_TIMEOUT;
  658. u8 addr_cycles;
  659. writel(ARASAN_NAND_INT_STS_XFR_CMPLT_MASK,
  660. &arasan_nand_base->intsts_enr);
  661. reg_val = readl(&arasan_nand_base->cmd_reg);
  662. reg_val &= ~ARASAN_NAND_CMD_CMD12_MASK;
  663. reg_val |= curr_cmd->cmd1 |
  664. (curr_cmd->cmd2 << ARASAN_NAND_CMD_CMD2_SHIFT);
  665. addr_cycles = arasan_nand_get_addrcycle(mtd);
  666. if (addr_cycles == ARASAN_NAND_INVALID_ADDR_CYCL)
  667. return ERR_ADDR_CYCLE;
  668. reg_val &= ~ARASAN_NAND_CMD_ADDR_CYCL_MASK;
  669. reg_val |= (addr_cycles <<
  670. ARASAN_NAND_CMD_ADDR_CYCL_SHIFT);
  671. writel(reg_val, &arasan_nand_base->cmd_reg);
  672. reg_val = readl(&arasan_nand_base->pkt_reg);
  673. reg_val &= ~(ARASAN_NAND_PKT_REG_PKT_CNT_MASK |
  674. ARASAN_NAND_PKT_REG_PKT_SIZE_MASK);
  675. reg_val |= (1 << ARASAN_NAND_PKT_REG_PKT_CNT_SHFT) | 1;
  676. writel(reg_val, &arasan_nand_base->pkt_reg);
  677. reg_val = readl(&arasan_nand_base->memadr_reg2);
  678. reg_val &= ~ARASAN_NAND_MEM_ADDR2_CS_MASK;
  679. writel(reg_val, &arasan_nand_base->memadr_reg2);
  680. writel(curr_cmd->pgm, &arasan_nand_base->pgm_reg);
  681. while (!(readl(&arasan_nand_base->intsts_reg) &
  682. ARASAN_NAND_INT_STS_XFR_CMPLT_MASK) && timeout) {
  683. udelay(1);
  684. timeout--;
  685. }
  686. if (!timeout) {
  687. printf("ERROR:%s: timedout:Xfer CMPLT\n", __func__);
  688. return -ETIMEDOUT;
  689. }
  690. reg_val = readl(&arasan_nand_base->intsts_enr);
  691. writel(reg_val | ARASAN_NAND_INT_STS_XFR_CMPLT_MASK,
  692. &arasan_nand_base->intsts_enr);
  693. reg_val = readl(&arasan_nand_base->intsts_reg);
  694. writel(reg_val | ARASAN_NAND_INT_STS_XFR_CMPLT_MASK,
  695. &arasan_nand_base->intsts_reg);
  696. return 0;
  697. }
  698. static int arasan_nand_send_rdcmd(struct arasan_nand_command_format *curr_cmd,
  699. int column, int page_addr, struct mtd_info *mtd)
  700. {
  701. u32 reg_val, addr_cycles, page;
  702. u8 page_val;
  703. reg_val = readl(&arasan_nand_base->intsts_enr);
  704. writel(reg_val | ARASAN_NAND_INT_STS_BUF_RD_RDY_MASK,
  705. &arasan_nand_base->intsts_enr);
  706. reg_val = readl(&arasan_nand_base->cmd_reg);
  707. reg_val &= ~ARASAN_NAND_CMD_CMD12_MASK;
  708. reg_val |= curr_cmd->cmd1 |
  709. (curr_cmd->cmd2 << ARASAN_NAND_CMD_CMD2_SHIFT);
  710. if (curr_cmd->cmd1 == NAND_CMD_RNDOUT ||
  711. curr_cmd->cmd1 == NAND_CMD_READ0) {
  712. reg_val &= ~ARASAN_NAND_CMD_PG_SIZE_MASK;
  713. page_val = arasan_nand_page(mtd);
  714. reg_val |= (page_val << ARASAN_NAND_CMD_PG_SIZE_SHIFT);
  715. }
  716. reg_val &= ~ARASAN_NAND_CMD_ADDR_CYCL_MASK;
  717. addr_cycles = arasan_nand_get_addrcycle(mtd);
  718. if (addr_cycles == ARASAN_NAND_INVALID_ADDR_CYCL)
  719. return ERR_ADDR_CYCLE;
  720. reg_val |= (addr_cycles << 28);
  721. writel(reg_val, &arasan_nand_base->cmd_reg);
  722. if (page_addr == -1)
  723. page_addr = 0;
  724. page = (page_addr << ARASAN_NAND_MEM_ADDR1_PAGE_SHIFT) &
  725. ARASAN_NAND_MEM_ADDR1_PAGE_MASK;
  726. column &= ARASAN_NAND_MEM_ADDR1_COL_MASK;
  727. writel(page | column, &arasan_nand_base->memadr_reg1);
  728. reg_val = readl(&arasan_nand_base->memadr_reg2);
  729. reg_val &= ~ARASAN_NAND_MEM_ADDR2_PAGE_MASK;
  730. reg_val |= (page_addr >> ARASAN_NAND_MEM_ADDR1_PAGE_SHIFT);
  731. writel(reg_val, &arasan_nand_base->memadr_reg2);
  732. reg_val = readl(&arasan_nand_base->memadr_reg2);
  733. reg_val &= ~ARASAN_NAND_MEM_ADDR2_CS_MASK;
  734. writel(reg_val, &arasan_nand_base->memadr_reg2);
  735. buf_index = 0;
  736. return 0;
  737. }
  738. static void arasan_nand_read_buf(struct mtd_info *mtd, u8 *buf, int size)
  739. {
  740. u32 reg_val, i;
  741. u32 *bufptr = (u32 *)buf;
  742. u32 timeout = ARASAN_NAND_POLL_TIMEOUT;
  743. reg_val = readl(&arasan_nand_base->pkt_reg);
  744. reg_val &= ~(ARASAN_NAND_PKT_REG_PKT_CNT_MASK |
  745. ARASAN_NAND_PKT_REG_PKT_SIZE_MASK);
  746. reg_val |= (1 << ARASAN_NAND_PKT_REG_PKT_CNT_SHFT) | size;
  747. writel(reg_val, &arasan_nand_base->pkt_reg);
  748. writel(curr_cmd->pgm, &arasan_nand_base->pgm_reg);
  749. while (!(readl(&arasan_nand_base->intsts_reg) &
  750. ARASAN_NAND_INT_STS_BUF_RD_RDY_MASK) && timeout) {
  751. udelay(1);
  752. timeout--;
  753. }
  754. if (!timeout)
  755. puts("ERROR:arasan_nand_read_buf timedout:Buff RDY\n");
  756. reg_val = readl(&arasan_nand_base->intsts_enr);
  757. reg_val |= ARASAN_NAND_INT_STS_XFR_CMPLT_MASK;
  758. writel(reg_val, &arasan_nand_base->intsts_enr);
  759. writel(reg_val | ARASAN_NAND_INT_STS_BUF_RD_RDY_MASK,
  760. &arasan_nand_base->intsts_enr);
  761. reg_val = readl(&arasan_nand_base->intsts_reg);
  762. writel(reg_val | ARASAN_NAND_INT_STS_BUF_RD_RDY_MASK,
  763. &arasan_nand_base->intsts_reg);
  764. buf_index = 0;
  765. for (i = 0; i < size / 4; i++)
  766. bufptr[i] = readl(&arasan_nand_base->buf_dataport);
  767. if (size & 0x03)
  768. bufptr[i] = readl(&arasan_nand_base->buf_dataport);
  769. timeout = ARASAN_NAND_POLL_TIMEOUT;
  770. while (!(readl(&arasan_nand_base->intsts_reg) &
  771. ARASAN_NAND_INT_STS_XFR_CMPLT_MASK) && timeout) {
  772. udelay(1);
  773. timeout--;
  774. }
  775. if (!timeout)
  776. puts("ERROR:arasan_nand_read_buf timedout:Xfer CMPLT\n");
  777. reg_val = readl(&arasan_nand_base->intsts_enr);
  778. writel(reg_val | ARASAN_NAND_INT_STS_XFR_CMPLT_MASK,
  779. &arasan_nand_base->intsts_enr);
  780. reg_val = readl(&arasan_nand_base->intsts_reg);
  781. writel(reg_val | ARASAN_NAND_INT_STS_XFR_CMPLT_MASK,
  782. &arasan_nand_base->intsts_reg);
  783. }
  784. static u8 arasan_nand_read_byte(struct mtd_info *mtd)
  785. {
  786. struct nand_chip *chip = mtd_to_nand(mtd);
  787. u32 size;
  788. u8 val;
  789. struct nand_onfi_params *p;
  790. if (buf_index == 0) {
  791. p = &chip->onfi_params;
  792. if (curr_cmd->cmd1 == NAND_CMD_READID)
  793. size = 4;
  794. else if (curr_cmd->cmd1 == NAND_CMD_PARAM)
  795. size = sizeof(struct nand_onfi_params);
  796. else if (curr_cmd->cmd1 == NAND_CMD_RNDOUT)
  797. size = le16_to_cpu(p->ext_param_page_length) * 16;
  798. else if (curr_cmd->cmd1 == NAND_CMD_GET_FEATURES)
  799. size = 4;
  800. else if (curr_cmd->cmd1 == NAND_CMD_STATUS)
  801. return readb(&arasan_nand_base->flash_sts_reg);
  802. else
  803. size = 8;
  804. chip->read_buf(mtd, &buf_data[0], size);
  805. }
  806. val = *(&buf_data[0] + buf_index);
  807. buf_index++;
  808. return val;
  809. }
  810. static void arasan_nand_cmd_function(struct mtd_info *mtd, unsigned int command,
  811. int column, int page_addr)
  812. {
  813. u32 i, ret = 0;
  814. struct nand_chip *chip = mtd_to_nand(mtd);
  815. struct arasan_nand_info *nand = nand_get_controller_data(chip);
  816. curr_cmd = NULL;
  817. writel(ARASAN_NAND_INT_STS_XFR_CMPLT_MASK,
  818. &arasan_nand_base->intsts_enr);
  819. if ((command == NAND_CMD_READOOB) &&
  820. (mtd->writesize > 512)) {
  821. column += mtd->writesize;
  822. command = NAND_CMD_READ0;
  823. }
  824. /* Get the command format */
  825. for (i = 0; (arasan_nand_commands[i].cmd1 != NAND_CMD_NONE ||
  826. arasan_nand_commands[i].cmd2 != NAND_CMD_NONE); i++) {
  827. if (command == arasan_nand_commands[i].cmd1) {
  828. curr_cmd = &arasan_nand_commands[i];
  829. break;
  830. }
  831. }
  832. if (curr_cmd == NULL) {
  833. printf("Unsupported Command; 0x%x\n", command);
  834. return;
  835. }
  836. if (curr_cmd->cmd1 == NAND_CMD_RESET)
  837. ret = arasan_nand_reset(curr_cmd);
  838. if ((curr_cmd->cmd1 == NAND_CMD_READID) ||
  839. (curr_cmd->cmd1 == NAND_CMD_PARAM) ||
  840. (curr_cmd->cmd1 == NAND_CMD_RNDOUT) ||
  841. (curr_cmd->cmd1 == NAND_CMD_GET_FEATURES) ||
  842. (curr_cmd->cmd1 == NAND_CMD_READ0))
  843. ret = arasan_nand_send_rdcmd(curr_cmd, column, page_addr, mtd);
  844. if ((curr_cmd->cmd1 == NAND_CMD_SET_FEATURES) ||
  845. (curr_cmd->cmd1 == NAND_CMD_SEQIN)) {
  846. nand->page = page_addr;
  847. ret = arasan_nand_send_wrcmd(curr_cmd, column, page_addr, mtd);
  848. }
  849. if (curr_cmd->cmd1 == NAND_CMD_ERASE1)
  850. ret = arasan_nand_erase(curr_cmd, column, page_addr, mtd);
  851. if (curr_cmd->cmd1 == NAND_CMD_STATUS)
  852. ret = arasan_nand_read_status(curr_cmd, column, page_addr, mtd);
  853. if (ret != 0)
  854. printf("ERROR:%s:command:0x%x\n", __func__, curr_cmd->cmd1);
  855. }
  856. static int arasan_nand_ecc_init(struct mtd_info *mtd)
  857. {
  858. int found = -1;
  859. u32 regval, eccpos_start, i;
  860. struct nand_chip *nand_chip = mtd_to_nand(mtd);
  861. nand_chip->ecc.mode = NAND_ECC_HW;
  862. nand_chip->ecc.hwctl = NULL;
  863. nand_chip->ecc.read_page = arasan_nand_read_page_hwecc;
  864. nand_chip->ecc.write_page = arasan_nand_write_page_hwecc;
  865. nand_chip->ecc.read_oob = arasan_nand_read_oob;
  866. nand_chip->ecc.write_oob = arasan_nand_write_oob;
  867. for (i = 0; i < ARRAY_SIZE(ecc_matrix); i++) {
  868. if ((ecc_matrix[i].pagesize == mtd->writesize) &&
  869. (ecc_matrix[i].ecc_codeword_size >=
  870. nand_chip->ecc_step_ds)) {
  871. if (ecc_matrix[i].eccbits >=
  872. nand_chip->ecc_strength_ds) {
  873. found = i;
  874. break;
  875. }
  876. found = i;
  877. }
  878. }
  879. if (found < 0)
  880. return 1;
  881. regval = ecc_matrix[found].eccaddr |
  882. (ecc_matrix[found].eccsize << ARASAN_NAND_ECC_SIZE_SHIFT) |
  883. (ecc_matrix[found].bch << ARASAN_NAND_ECC_BCH_SHIFT);
  884. writel(regval, &arasan_nand_base->ecc_reg);
  885. if (ecc_matrix[found].bch) {
  886. regval = readl(&arasan_nand_base->memadr_reg2);
  887. regval &= ~ARASAN_NAND_MEM_ADDR2_BCH_MASK;
  888. regval |= (ecc_matrix[found].bchval <<
  889. ARASAN_NAND_MEM_ADDR2_BCH_SHIFT);
  890. writel(regval, &arasan_nand_base->memadr_reg2);
  891. }
  892. nand_oob.eccbytes = ecc_matrix[found].eccsize;
  893. eccpos_start = mtd->oobsize - nand_oob.eccbytes;
  894. for (i = 0; i < nand_oob.eccbytes; i++)
  895. nand_oob.eccpos[i] = eccpos_start + i;
  896. nand_oob.oobfree[0].offset = 2;
  897. nand_oob.oobfree[0].length = eccpos_start - 2;
  898. nand_chip->ecc.size = ecc_matrix[found].ecc_codeword_size;
  899. nand_chip->ecc.strength = ecc_matrix[found].eccbits;
  900. nand_chip->ecc.bytes = ecc_matrix[found].eccsize;
  901. nand_chip->ecc.layout = &nand_oob;
  902. return 0;
  903. }
  904. static int arasan_nand_init(struct nand_chip *nand_chip, int devnum)
  905. {
  906. struct arasan_nand_info *nand;
  907. struct mtd_info *mtd;
  908. int err = -1;
  909. nand = calloc(1, sizeof(struct arasan_nand_info));
  910. if (!nand) {
  911. printf("%s: failed to allocate\n", __func__);
  912. return err;
  913. }
  914. nand->nand_base = arasan_nand_base;
  915. mtd = nand_to_mtd(nand_chip);
  916. nand_set_controller_data(nand_chip, nand);
  917. /* Set the driver entry points for MTD */
  918. nand_chip->cmdfunc = arasan_nand_cmd_function;
  919. nand_chip->select_chip = arasan_nand_select_chip;
  920. nand_chip->read_byte = arasan_nand_read_byte;
  921. /* Buffer read/write routines */
  922. nand_chip->read_buf = arasan_nand_read_buf;
  923. nand_chip->write_buf = arasan_nand_write_buf;
  924. nand_chip->bbt_options = NAND_BBT_USE_FLASH;
  925. writel(0x0, &arasan_nand_base->cmd_reg);
  926. writel(0x0, &arasan_nand_base->pgm_reg);
  927. /* first scan to find the device and get the page size */
  928. if (nand_scan_ident(mtd, 1, NULL)) {
  929. printf("%s: nand_scan_ident failed\n", __func__);
  930. goto fail;
  931. }
  932. if (arasan_nand_ecc_init(mtd)) {
  933. printf("%s: nand_ecc_init failed\n", __func__);
  934. goto fail;
  935. }
  936. if (nand_scan_tail(mtd)) {
  937. printf("%s: nand_scan_tail failed\n", __func__);
  938. goto fail;
  939. }
  940. if (nand_register(devnum, mtd)) {
  941. printf("Nand Register Fail\n");
  942. goto fail;
  943. }
  944. return 0;
  945. fail:
  946. free(nand);
  947. return err;
  948. }
  949. void board_nand_init(void)
  950. {
  951. struct nand_chip *nand = &nand_chip[0];
  952. if (arasan_nand_init(nand, 0))
  953. puts("NAND init failed\n");
  954. }