am335x_spl_bch.c 5.9 KB

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  1. /*
  2. * (C) Copyright 2012
  3. * Konstantin Kozhevnikov, Cogent Embedded
  4. *
  5. * based on nand_spl_simple code
  6. *
  7. * (C) Copyright 2006-2008
  8. * Stefan Roese, DENX Software Engineering, sr@denx.de.
  9. *
  10. * SPDX-License-Identifier: GPL-2.0+
  11. */
  12. #include <common.h>
  13. #include <nand.h>
  14. #include <asm/io.h>
  15. #include <linux/mtd/nand_ecc.h>
  16. static int nand_ecc_pos[] = CONFIG_SYS_NAND_ECCPOS;
  17. static struct mtd_info *mtd;
  18. static struct nand_chip nand_chip;
  19. #define ECCSTEPS (CONFIG_SYS_NAND_PAGE_SIZE / \
  20. CONFIG_SYS_NAND_ECCSIZE)
  21. #define ECCTOTAL (ECCSTEPS * CONFIG_SYS_NAND_ECCBYTES)
  22. /*
  23. * NAND command for large page NAND devices (2k)
  24. */
  25. static int nand_command(int block, int page, uint32_t offs,
  26. u8 cmd)
  27. {
  28. struct nand_chip *this = mtd_to_nand(mtd);
  29. int page_addr = page + block * CONFIG_SYS_NAND_PAGE_COUNT;
  30. void (*hwctrl)(struct mtd_info *mtd, int cmd,
  31. unsigned int ctrl) = this->cmd_ctrl;
  32. while (!this->dev_ready(mtd))
  33. ;
  34. /* Emulate NAND_CMD_READOOB */
  35. if (cmd == NAND_CMD_READOOB) {
  36. offs += CONFIG_SYS_NAND_PAGE_SIZE;
  37. cmd = NAND_CMD_READ0;
  38. }
  39. /* Begin command latch cycle */
  40. hwctrl(mtd, cmd, NAND_CTRL_CLE | NAND_CTRL_CHANGE);
  41. if (cmd == NAND_CMD_RESET) {
  42. hwctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
  43. while (!this->dev_ready(mtd))
  44. ;
  45. return 0;
  46. }
  47. /* Shift the offset from byte addressing to word addressing. */
  48. if ((this->options & NAND_BUSWIDTH_16) && !nand_opcode_8bits(cmd))
  49. offs >>= 1;
  50. /* Set ALE and clear CLE to start address cycle */
  51. /* Column address */
  52. hwctrl(mtd, offs & 0xff,
  53. NAND_CTRL_ALE | NAND_CTRL_CHANGE); /* A[7:0] */
  54. hwctrl(mtd, (offs >> 8) & 0xff, NAND_CTRL_ALE); /* A[11:9] */
  55. /* Row address */
  56. if (cmd != NAND_CMD_RNDOUT) {
  57. hwctrl(mtd, (page_addr & 0xff),
  58. NAND_CTRL_ALE); /* A[19:12] */
  59. hwctrl(mtd, ((page_addr >> 8) & 0xff),
  60. NAND_CTRL_ALE); /* A[27:20] */
  61. #ifdef CONFIG_SYS_NAND_5_ADDR_CYCLE
  62. /* One more address cycle for devices > 128MiB */
  63. hwctrl(mtd, (page_addr >> 16) & 0x0f,
  64. NAND_CTRL_ALE); /* A[31:28] */
  65. #endif
  66. }
  67. hwctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
  68. if (cmd == NAND_CMD_READ0) {
  69. /* Latch in address */
  70. hwctrl(mtd, NAND_CMD_READSTART,
  71. NAND_CTRL_CLE | NAND_CTRL_CHANGE);
  72. hwctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
  73. /*
  74. * Wait a while for the data to be ready
  75. */
  76. while (!this->dev_ready(mtd))
  77. ;
  78. } else if (cmd == NAND_CMD_RNDOUT) {
  79. hwctrl(mtd, NAND_CMD_RNDOUTSTART, NAND_CTRL_CLE |
  80. NAND_CTRL_CHANGE);
  81. hwctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
  82. }
  83. return 0;
  84. }
  85. static int nand_is_bad_block(int block)
  86. {
  87. struct nand_chip *this = mtd_to_nand(mtd);
  88. nand_command(block, 0, CONFIG_SYS_NAND_BAD_BLOCK_POS,
  89. NAND_CMD_READOOB);
  90. /*
  91. * Read one byte (or two if it's a 16 bit chip).
  92. */
  93. if (this->options & NAND_BUSWIDTH_16) {
  94. if (readw(this->IO_ADDR_R) != 0xffff)
  95. return 1;
  96. } else {
  97. if (readb(this->IO_ADDR_R) != 0xff)
  98. return 1;
  99. }
  100. return 0;
  101. }
  102. static int nand_read_page(int block, int page, void *dst)
  103. {
  104. struct nand_chip *this = mtd_to_nand(mtd);
  105. u_char ecc_calc[ECCTOTAL];
  106. u_char ecc_code[ECCTOTAL];
  107. u_char oob_data[CONFIG_SYS_NAND_OOBSIZE];
  108. int i;
  109. int eccsize = CONFIG_SYS_NAND_ECCSIZE;
  110. int eccbytes = CONFIG_SYS_NAND_ECCBYTES;
  111. int eccsteps = ECCSTEPS;
  112. uint8_t *p = dst;
  113. uint32_t data_pos = 0;
  114. uint8_t *oob = &oob_data[0] + nand_ecc_pos[0];
  115. uint32_t oob_pos = eccsize * eccsteps + nand_ecc_pos[0];
  116. nand_command(block, page, 0, NAND_CMD_READ0);
  117. for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
  118. this->ecc.hwctl(mtd, NAND_ECC_READ);
  119. nand_command(block, page, data_pos, NAND_CMD_RNDOUT);
  120. this->read_buf(mtd, p, eccsize);
  121. nand_command(block, page, oob_pos, NAND_CMD_RNDOUT);
  122. this->read_buf(mtd, oob, eccbytes);
  123. this->ecc.calculate(mtd, p, &ecc_calc[i]);
  124. data_pos += eccsize;
  125. oob_pos += eccbytes;
  126. oob += eccbytes;
  127. }
  128. /* Pick the ECC bytes out of the oob data */
  129. for (i = 0; i < ECCTOTAL; i++)
  130. ecc_code[i] = oob_data[nand_ecc_pos[i]];
  131. eccsteps = ECCSTEPS;
  132. p = dst;
  133. for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
  134. /* No chance to do something with the possible error message
  135. * from correct_data(). We just hope that all possible errors
  136. * are corrected by this routine.
  137. */
  138. this->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
  139. }
  140. return 0;
  141. }
  142. int nand_spl_load_image(uint32_t offs, unsigned int size, void *dst)
  143. {
  144. unsigned int block, lastblock;
  145. unsigned int page, page_offset;
  146. /*
  147. * offs has to be aligned to a page address!
  148. */
  149. block = offs / CONFIG_SYS_NAND_BLOCK_SIZE;
  150. lastblock = (offs + size - 1) / CONFIG_SYS_NAND_BLOCK_SIZE;
  151. page = (offs % CONFIG_SYS_NAND_BLOCK_SIZE) / CONFIG_SYS_NAND_PAGE_SIZE;
  152. page_offset = offs % CONFIG_SYS_NAND_PAGE_SIZE;
  153. while (block <= lastblock) {
  154. if (!nand_is_bad_block(block)) {
  155. /*
  156. * Skip bad blocks
  157. */
  158. while (page < CONFIG_SYS_NAND_PAGE_COUNT) {
  159. nand_read_page(block, page, dst);
  160. /*
  161. * When offs is not aligned to page address the
  162. * extra offset is copied to dst as well. Copy
  163. * the image such that its first byte will be
  164. * at the dst.
  165. */
  166. if (unlikely(page_offset)) {
  167. memmove(dst, dst + page_offset,
  168. CONFIG_SYS_NAND_PAGE_SIZE);
  169. dst = (void *)((int)dst - page_offset);
  170. page_offset = 0;
  171. }
  172. dst += CONFIG_SYS_NAND_PAGE_SIZE;
  173. page++;
  174. }
  175. page = 0;
  176. } else {
  177. lastblock++;
  178. }
  179. block++;
  180. }
  181. return 0;
  182. }
  183. /* nand_init() - initialize data to make nand usable by SPL */
  184. void nand_init(void)
  185. {
  186. /*
  187. * Init board specific nand support
  188. */
  189. mtd = &nand_chip.mtd;
  190. nand_chip.IO_ADDR_R = nand_chip.IO_ADDR_W =
  191. (void __iomem *)CONFIG_SYS_NAND_BASE;
  192. board_nand_init(&nand_chip);
  193. if (nand_chip.select_chip)
  194. nand_chip.select_chip(mtd, 0);
  195. /* NAND chip may require reset after power-on */
  196. nand_command(0, 0, 0, NAND_CMD_RESET);
  197. }
  198. /* Unselect after operation */
  199. void nand_deselect(void)
  200. {
  201. if (nand_chip.select_chip)
  202. nand_chip.select_chip(mtd, -1);
  203. }