actl_nand.c 1.1 KB

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  1. /*
  2. * Copyright 2008 Extreme Engineering Solutions, Inc.
  3. *
  4. * This driver support NAND devices which have address lines
  5. * connected as ALE and CLE inputs.
  6. *
  7. * SPDX-License-Identifier: GPL-2.0+
  8. */
  9. #include <common.h>
  10. #include <nand.h>
  11. #include <asm/io.h>
  12. /*
  13. * Hardware specific access to control-lines
  14. */
  15. static void nand_addr_hwcontrol(struct mtd_info *mtd, int cmd, uint ctrl)
  16. {
  17. struct nand_chip *this = mtd_to_nand(mtd);
  18. ulong IO_ADDR_W;
  19. if (ctrl & NAND_CTRL_CHANGE) {
  20. IO_ADDR_W = (ulong)this->IO_ADDR_W;
  21. IO_ADDR_W &= ~(CONFIG_SYS_NAND_ACTL_CLE |
  22. CONFIG_SYS_NAND_ACTL_ALE |
  23. CONFIG_SYS_NAND_ACTL_NCE);
  24. if (ctrl & NAND_CLE)
  25. IO_ADDR_W |= CONFIG_SYS_NAND_ACTL_CLE;
  26. if (ctrl & NAND_ALE)
  27. IO_ADDR_W |= CONFIG_SYS_NAND_ACTL_ALE;
  28. if (ctrl & NAND_NCE)
  29. IO_ADDR_W |= CONFIG_SYS_NAND_ACTL_NCE;
  30. this->IO_ADDR_W = (void *)IO_ADDR_W;
  31. }
  32. if (cmd != NAND_CMD_NONE)
  33. writeb(cmd, this->IO_ADDR_W);
  34. }
  35. int board_nand_init(struct nand_chip *nand)
  36. {
  37. nand->ecc.mode = NAND_ECC_SOFT;
  38. nand->cmd_ctrl = nand_addr_hwcontrol;
  39. nand->chip_delay = CONFIG_SYS_NAND_ACTL_DELAY;
  40. return 0;
  41. }