nand.c 1.6 KB

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  1. /*
  2. * (C) Copyright 2000-2003
  3. * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  4. *
  5. * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc.
  6. * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
  7. *
  8. * SPDX-License-Identifier: GPL-2.0+
  9. */
  10. #include <config.h>
  11. #include <common.h>
  12. #include <asm/io.h>
  13. #include <asm/immap.h>
  14. DECLARE_GLOBAL_DATA_PTR;
  15. #if defined(CONFIG_CMD_NAND)
  16. #include <nand.h>
  17. #include <linux/mtd/mtd.h>
  18. #define SET_CLE 0x10
  19. #define SET_ALE 0x08
  20. static void nand_hwcontrol(struct mtd_info *mtdinfo, int cmd, unsigned int ctrl)
  21. {
  22. struct nand_chip *this = mtd_to_nand(mtdinfo);
  23. volatile u16 *nCE = (u16 *) CONFIG_SYS_LATCH_ADDR;
  24. if (ctrl & NAND_CTRL_CHANGE) {
  25. ulong IO_ADDR_W = (ulong) this->IO_ADDR_W;
  26. IO_ADDR_W &= ~(SET_ALE | SET_CLE);
  27. if (ctrl & NAND_NCE)
  28. *nCE &= 0xFFFB;
  29. else
  30. *nCE |= 0x0004;
  31. if (ctrl & NAND_CLE)
  32. IO_ADDR_W |= SET_CLE;
  33. if (ctrl & NAND_ALE)
  34. IO_ADDR_W |= SET_ALE;
  35. this->IO_ADDR_W = (void *)IO_ADDR_W;
  36. }
  37. if (cmd != NAND_CMD_NONE)
  38. writeb(cmd, this->IO_ADDR_W);
  39. }
  40. int board_nand_init(struct nand_chip *nand)
  41. {
  42. gpio_t *gpio = (gpio_t *) MMAP_GPIO;
  43. /*
  44. * set up pin configuration - enabled 2nd output buffer's signals
  45. * (nand_ngpio - nCE USB1/2_PWR_EN, LATCH_GPIOs, LCD_VEEEN, etc)
  46. * to use nCE signal
  47. */
  48. clrbits_8(&gpio->par_timer, GPIO_PAR_TIN3_TIN3);
  49. setbits_8(&gpio->pddr_timer, 0x08);
  50. setbits_8(&gpio->ppd_timer, 0x08);
  51. out_8(&gpio->pclrr_timer, 0);
  52. out_8(&gpio->podr_timer, 0);
  53. nand->chip_delay = 60;
  54. nand->ecc.mode = NAND_ECC_SOFT;
  55. nand->cmd_ctrl = nand_hwcontrol;
  56. return 0;
  57. }
  58. #endif