init.S 3.3 KB

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  1. /*
  2. *
  3. * See file CREDITS for list of people who contributed to this
  4. * project.
  5. *
  6. * This program is free software; you can redistribute it and/or
  7. * modify it under the terms of the GNU General Public License as
  8. * published by the Free Software Foundation; either version 2 of
  9. * the License, or (at your option) any later version.
  10. *
  11. * This program is distributed in the hope that it will be useful,
  12. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  14. * GNU General Public License for more details.
  15. *
  16. * You should have received a copy of the GNU General Public License
  17. * along with this program; if not, write to the Free Software
  18. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  19. * MA 02111-1307 USA
  20. */
  21. #include <ppc_asm.tmpl>
  22. #include <config.h>
  23. #include <asm/mmu.h>
  24. /**************************************************************************
  25. * TLB TABLE
  26. *
  27. * This table is used by the cpu boot code to setup the initial tlb
  28. * entries. Rather than make broad assumptions in the cpu source tree,
  29. * this table lets each board set things up however they like.
  30. *
  31. * Pointer to the table is returned in r1
  32. *
  33. *************************************************************************/
  34. .section .bootpg,"ax"
  35. .globl tlbtab
  36. tlbtab:
  37. tlbtab_start
  38. /* TLB#0: vxWorks needs this entry for the Machine Check interrupt, */
  39. tlbentry( 0x40000000, SZ_256M, 0, 0, AC_RWX | SA_IG )
  40. /* TLB#1: TLB-entry for DDR SDRAM (Up to 2GB) */
  41. tlbentry( CONFIG_SYS_SDRAM_BASE, SZ_256M, CONFIG_SYS_SDRAM_BASE, 0,
  42. AC_RWX | SA_IG )
  43. /* TLB#2: TLB-entry for EBC */
  44. tlbentry( 0x80000000, SZ_256M, 0x80000000, 1, AC_RWX | SA_IG)
  45. /*
  46. * TLB#3: BOOT_CS (FLASH) must be forth. Before relocation SA_I can be
  47. * off to use the speed up boot process. It is patched after relocation
  48. * to enable SA_I
  49. */
  50. tlbentry( CONFIG_SYS_BOOT_BASE_ADDR, SZ_1M, CONFIG_SYS_BOOT_BASE_ADDR, 1,
  51. AC_RWX | SA_G)
  52. /*
  53. * TLB entries for SDRAM are not needed on this platform.
  54. * They are dynamically generated in the SPD DDR(2) detection
  55. * routine.
  56. */
  57. /* TLB#4: */
  58. tlbentry( CONFIG_SYS_PCI_MEMBASE1, SZ_256M, CONFIG_SYS_PCI_MEMBASE1, 1,
  59. AC_RW | SA_IG )
  60. /* TLB#5: */
  61. tlbentry( CONFIG_SYS_PCI_MEMBASE2, SZ_256M, CONFIG_SYS_PCI_MEMBASE2, 1,
  62. AC_RW | SA_IG )
  63. /* TLB#6: */
  64. tlbentry( CONFIG_SYS_PCI_MEMBASE3, SZ_256M, CONFIG_SYS_PCI_MEMBASE3, 1,
  65. AC_RW | SA_IG )
  66. /* TLB-entry for Internal Registers & OCM */
  67. /* TLB#7: */
  68. tlbentry( 0xe0000000, SZ_16M, 0xe0000000, 0,
  69. AC_RWX | SA_IG )
  70. /*TLB-entry PCI registers*/
  71. /* TLB#8: */
  72. tlbentry( 0xEEC00000, SZ_1K, 0xEEC00000, 1, AC_RWX | SA_IG )
  73. /* TLB-entry for peripherals */
  74. /* TLB#9: */
  75. tlbentry( 0xEF000000, SZ_16M, 0xEF000000, 1, AC_RWX | SA_IG)
  76. /* CAN */
  77. /* TLB#10: */
  78. tlbentry( CONFIG_SYS_CS_1, SZ_1K, CONFIG_SYS_CS_1, 1, AC_RWX | SA_IG )
  79. /* TLB#11: CPLD and IMC-Standard 32 MB */
  80. tlbentry( CONFIG_SYS_CS_2, SZ_16M, CONFIG_SYS_CS_2, 1, AC_RWX | SA_IG )
  81. /* TLB#12: */
  82. tlbentry( CONFIG_SYS_CS_2 + 0x1000000, SZ_16M, CONFIG_SYS_CS_2 + 0x1000000, 1,
  83. AC_RWX | SA_IG )
  84. /* IMC-Fast 32 MB */
  85. /* TLB#13: */
  86. tlbentry( CONFIG_SYS_CS_3, SZ_16M, CONFIG_SYS_CS_3, 1, AC_RWX | SA_IG )
  87. /* TLB#14: */
  88. tlbentry( CONFIG_SYS_CS_3 + 0x1000000, SZ_16M, CONFIG_SYS_CS_3, 1,
  89. AC_RWX | SA_IG )
  90. tlbtab_end