hcu5.c 11 KB

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  1. /*
  2. *(C) Copyright 2005-2008 Netstal Maschinen AG
  3. * Niklaus Giger (Niklaus.Giger@netstal.com)
  4. *
  5. * This source code is free software; you can redistribute it
  6. * and/or modify it in source code form under the terms of the GNU
  7. * General Public License as published by the Free Software
  8. * Foundation; either version 2 of the License, or (at your option)
  9. * any later version.
  10. *
  11. * This program is distributed in the hope that it will be useful,
  12. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  14. * GNU General Public License for more details.
  15. *
  16. * You should have received a copy of the GNU General Public License
  17. * along with this program; if not, write to the Free Software
  18. * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
  19. */
  20. #include <common.h>
  21. #include <asm/processor.h>
  22. #include <asm/ppc440.h>
  23. #include <asm/io.h>
  24. #include <asm/4xx_pci.h>
  25. #include "../common/nm.h"
  26. DECLARE_GLOBAL_DATA_PTR;
  27. extern flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];
  28. #undef BOOTSTRAP_OPTION_A_ACTIVE
  29. #define SDR0_CP440 0x0180
  30. #define SYSTEM_RESET 0x30000000
  31. #define CHIP_RESET 0x20000000
  32. #define SDR0_ECID0 0x0080
  33. #define SDR0_ECID1 0x0081
  34. #define SDR0_ECID2 0x0082
  35. #define SDR0_ECID3 0x0083
  36. #define SYS_IO_ADDRESS (CONFIG_SYS_CS_2 + 0x00e00000)
  37. #define SYS_SLOT_ADDRESS (CONFIG_SYS_CPLD + 0x00400000)
  38. #define HCU_DIGITAL_IO_REGISTER (CONFIG_SYS_CPLD + 0x0500000)
  39. #define HCU_SW_INSTALL_REQUESTED 0x10
  40. /*
  41. * This function is run very early, out of flash, and before devices are
  42. * initialized. It is called by arch/powerpc/lib/board.c:board_init_f by virtue
  43. * of being in the init_sequence array.
  44. *
  45. * The SDRAM has been initialized already -- start.S:start called
  46. * init.S:init_sdram early on -- but it is not yet being used for
  47. * anything, not even stack. So be careful.
  48. */
  49. int board_early_init_f(void)
  50. {
  51. #ifdef BOOTSTRAP_OPTION_A_ACTIVE
  52. /* Booting with Bootstrap Option A
  53. * First boot, with CPR0_ICFG_RLI_MASK == 0
  54. * no we setup varios boot strapping register,
  55. * then we do reset the PPC440 using a chip reset
  56. * Unfortunately, we cannot use this option, as Nto1 is not set
  57. * with Bootstrap Option A and cannot be changed later on by SW
  58. * There are no other possible boostrap options with a 8 bit ROM
  59. * See Errata (Version 1.04) CHIP_9
  60. */
  61. u32 cpr0icfg;
  62. u32 dbcr;
  63. mfcpr(CPR0_ICFG, cpr0icfg);
  64. if (!(cpr0icfg & CPR0_ICFG_RLI_MASK)) {
  65. mtcpr(CPR0_MALD, 0x02000000);
  66. mtcpr(CPR0_OPBD, 0x02000000);
  67. mtcpr(CPR0_PERD, 0x05000000); /* 1:5 */
  68. mtcpr(CPR0_PLLC, 0x40000238);
  69. mtcpr(CPR0_PLLD, 0x01010414);
  70. mtcpr(CPR0_PRIMAD, 0x01000000);
  71. mtcpr(CPR0_PRIMBD, 0x01000000);
  72. mtcpr(CPR0_SPCID, 0x03000000);
  73. mtsdr(SDR0_PFC0, 0x00003E00); /* [CTE] = 0 */
  74. mtsdr(SDR0_CP440, 0x0EAAEA02); /* [Nto1] = 1*/
  75. mtcpr(CPR0_ICFG, cpr0icfg | CPR0_ICFG_RLI_MASK);
  76. /*
  77. * Initiate system reset in debug control register DBCR
  78. */
  79. dbcr = mfspr(SPRN_DBCR0);
  80. mtspr(SPRN_DBCR0, dbcr | CHIP_RESET);
  81. }
  82. mtsdr(SDR0_CP440, 0x0EAAEA02); /* [Nto1] = 1*/
  83. #endif
  84. mtdcr(EBC0_CFGADDR, EBC0_CFG);
  85. mtdcr(EBC0_CFGDATA, 0xb8400000);
  86. /*
  87. * Setup the GPIO pins
  88. */
  89. out32(GPIO0_OR, 0x00000000);
  90. out32(GPIO0_TCR, 0x7C2FF1CF);
  91. out32(GPIO0_OSRL, 0x40055000);
  92. out32(GPIO0_OSRH, 0x00000000);
  93. out32(GPIO0_TSRL, 0x40055000);
  94. out32(GPIO0_TSRH, 0x00000400);
  95. out32(GPIO0_ISR1L, 0x40000000);
  96. out32(GPIO0_ISR1H, 0x00000000);
  97. out32(GPIO0_ISR2L, 0x00000000);
  98. out32(GPIO0_ISR2H, 0x00000000);
  99. out32(GPIO0_ISR3L, 0x00000000);
  100. out32(GPIO0_ISR3H, 0x00000000);
  101. out32(GPIO1_OR, 0x00000000);
  102. out32(GPIO1_TCR, 0xC6007FFF);
  103. out32(GPIO1_OSRL, 0x00140000);
  104. out32(GPIO1_OSRH, 0x00000000);
  105. out32(GPIO1_TSRL, 0x00000000);
  106. out32(GPIO1_TSRH, 0x00000000);
  107. out32(GPIO1_ISR1L, 0x05415555);
  108. out32(GPIO1_ISR1H, 0x40000000);
  109. out32(GPIO1_ISR2L, 0x00000000);
  110. out32(GPIO1_ISR2H, 0x00000000);
  111. out32(GPIO1_ISR3L, 0x00000000);
  112. out32(GPIO1_ISR3H, 0x00000000);
  113. /*
  114. * Setup the interrupt controller polarities, triggers, etc.
  115. */
  116. mtdcr(UIC0SR, 0xffffffff); /* clear all */
  117. mtdcr(UIC0ER, 0x00000000); /* disable all */
  118. mtdcr(UIC0CR, 0x00000005); /* ATI & UIC1 crit are critical */
  119. mtdcr(UIC0PR, 0xfffff7ff); /* per ref-board manual */
  120. mtdcr(UIC0TR, 0x00000000); /* per ref-board manual */
  121. mtdcr(UIC0VR, 0x00000000); /* int31 highest, base=0x000 */
  122. mtdcr(UIC0SR, 0xffffffff); /* clear all */
  123. mtdcr(UIC1SR, 0xffffffff); /* clear all */
  124. mtdcr(UIC1ER, 0x00000000); /* disable all */
  125. mtdcr(UIC1CR, 0x00000000); /* all non-critical */
  126. mtdcr(UIC1PR, 0xffffffff); /* per ref-board manual */
  127. mtdcr(UIC1TR, 0x00000000); /* per ref-board manual */
  128. mtdcr(UIC1VR, 0x00000000); /* int31 highest, base=0x000 */
  129. mtdcr(UIC1SR, 0xffffffff); /* clear all */
  130. mtdcr(UIC2SR, 0xffffffff); /* clear all */
  131. mtdcr(UIC2ER, 0x00000000); /* disable all */
  132. mtdcr(UIC2CR, 0x00000000); /* all non-critical */
  133. mtdcr(UIC2PR, 0xffffffff); /* per ref-board manual */
  134. mtdcr(UIC2TR, 0x00000000); /* per ref-board manual */
  135. mtdcr(UIC2VR, 0x00000000); /* int31 highest, base=0x000 */
  136. mtdcr(UIC2SR, 0xffffffff); /* clear all */
  137. mtsdr(SDR0_PFC0, 0x00003E00); /* Pin function: */
  138. mtsdr(SDR0_PFC1, 0x00848000); /* Pin function: UART0 has 4 pins */
  139. /* setup BOOT FLASH */
  140. mtsdr(SDR0_CUST0, 0xC0082350);
  141. return 0;
  142. }
  143. #ifdef CONFIG_BOARD_PRE_INIT
  144. int board_pre_init(void)
  145. {
  146. return board_early_init_f();
  147. }
  148. #endif
  149. int sys_install_requested(void)
  150. {
  151. u16 *ioValuePtr = (u16 *)HCU_DIGITAL_IO_REGISTER;
  152. return (in_be16(ioValuePtr) & HCU_SW_INSTALL_REQUESTED) != 0;
  153. }
  154. int checkboard(void)
  155. {
  156. u16 *hwVersReg = (u16 *) HCU_HW_VERSION_REGISTER;
  157. u16 *boardVersReg = (u16 *) HCU_CPLD_VERSION_REGISTER;
  158. u16 generation = in_be16(boardVersReg) & 0xf0;
  159. u16 index = in_be16(boardVersReg) & 0x0f;
  160. u32 ecid0, ecid1, ecid2, ecid3;
  161. nm_show_print(generation, index, in_be16(hwVersReg) & 0xff);
  162. mfsdr(SDR0_ECID0, ecid0);
  163. mfsdr(SDR0_ECID1, ecid1);
  164. mfsdr(SDR0_ECID2, ecid2);
  165. mfsdr(SDR0_ECID3, ecid3);
  166. printf("Chip ID 0x%x 0x%x 0x%x 0x%x\n", ecid0, ecid1, ecid2, ecid3);
  167. return 0;
  168. }
  169. u32 hcu_led_get(void)
  170. {
  171. return in16(SYS_IO_ADDRESS) & 0x3f;
  172. }
  173. /*
  174. * hcu_led_set value to be placed into the LEDs (max 6 bit)
  175. */
  176. void hcu_led_set(u32 value)
  177. {
  178. out16(SYS_IO_ADDRESS, value);
  179. }
  180. /*
  181. * get_serial_number
  182. */
  183. u32 get_serial_number(void)
  184. {
  185. u32 *serial = (u32 *)CONFIG_SYS_FLASH_BASE;
  186. if (in_be32(serial) == 0xffffffff)
  187. return 0;
  188. return in_be32(serial);
  189. }
  190. /*
  191. * hcu_get_slot
  192. */
  193. u32 hcu_get_slot(void)
  194. {
  195. u16 *slot = (u16 *)SYS_SLOT_ADDRESS;
  196. return in_be16(slot) & 0x7f;
  197. }
  198. /*
  199. * misc_init_r.
  200. */
  201. int misc_init_r(void)
  202. {
  203. unsigned long usb2d0cr = 0;
  204. unsigned long usb2phy0cr, usb2h0cr = 0;
  205. unsigned long sdr0_pfc1;
  206. #ifdef CONFIG_ENV_IS_IN_FLASH
  207. /* Monitor protection ON by default */
  208. (void)flash_protect(FLAG_PROTECT_SET,
  209. -CONFIG_SYS_MONITOR_LEN,
  210. 0xffffffff,
  211. &flash_info[0]);
  212. #ifdef CONFIG_ENV_ADDR_REDUND
  213. /* Env protection ON by default */
  214. (void)flash_protect(FLAG_PROTECT_SET,
  215. CONFIG_ENV_ADDR_REDUND,
  216. CONFIG_ENV_ADDR_REDUND + 2*CONFIG_ENV_SECT_SIZE - 1,
  217. &flash_info[0]);
  218. #endif
  219. #endif
  220. /*
  221. * USB stuff...
  222. */
  223. /* SDR Setting */
  224. mfsdr(SDR0_PFC1, sdr0_pfc1);
  225. mfsdr(SDR0_USB2D0CR, usb2d0cr);
  226. mfsdr(SDR0_USB2PHY0CR, usb2phy0cr);
  227. mfsdr(SDR0_USB2H0CR, usb2h0cr);
  228. usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_XOCLK_MASK;
  229. usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL; /*0*/
  230. usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_WDINT_MASK;
  231. usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_WDINT_16BIT_30MHZ; /*1*/
  232. usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DVBUS_MASK;
  233. usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PURDIS; /*0*/
  234. usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DWNSTR_MASK;
  235. usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_HOST; /*1*/
  236. usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_UTMICN_MASK;
  237. usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_HOST; /*1*/
  238. /* An 8-bit/60MHz interface is the only possible alternative
  239. * when connecting the Device to the PHY
  240. */
  241. usb2h0cr = usb2h0cr &~SDR0_USB2H0CR_WDINT_MASK;
  242. usb2h0cr = usb2h0cr | SDR0_USB2H0CR_WDINT_16BIT_30MHZ; /*1*/
  243. /* To enable the USB 2.0 Device function through the UTMI interface */
  244. usb2d0cr = usb2d0cr &~SDR0_USB2D0CR_USB2DEV_EBC_SEL_MASK;
  245. usb2d0cr = usb2d0cr | SDR0_USB2D0CR_USB2DEV_SELECTION; /*1*/
  246. sdr0_pfc1 = sdr0_pfc1 &~SDR0_PFC1_UES_MASK;
  247. sdr0_pfc1 = sdr0_pfc1 | SDR0_PFC1_UES_USB2D_SEL; /*0*/
  248. mtsdr(SDR0_PFC1, sdr0_pfc1);
  249. mtsdr(SDR0_USB2D0CR, usb2d0cr);
  250. mtsdr(SDR0_USB2PHY0CR, usb2phy0cr);
  251. mtsdr(SDR0_USB2H0CR, usb2h0cr);
  252. /*clear resets*/
  253. udelay(1000);
  254. mtsdr(SDR0_SRST1, 0x00000000);
  255. udelay(1000);
  256. mtsdr(SDR0_SRST0, 0x00000000);
  257. printf("USB: Host(int phy) Device(ext phy)\n");
  258. common_misc_init_r();
  259. set_params_for_sw_install( sys_install_requested(), "hcu5" );
  260. /* We cannot easily enable trace before, as there are other
  261. * routines messing around with sdr0_pfc1. And I do not need it.
  262. */
  263. if (mfspr(SPRN_DBCR0) & 0x80000000) {
  264. /* External debugger alive
  265. * enable trace facilty for Lauterbach
  266. * CCR0[DTB]=0 Enable broadcast of trace information
  267. * SDR0_PFC0[TRE] Trace signals are enabled instead of
  268. * GPIO49-63
  269. */
  270. mtspr(SPRN_CCR0, mfspr(SPRN_CCR0) &~ (CCR0_DTB));
  271. mtsdr(SDR0_PFC0, sdr0_pfc1 | SDR0_PFC0_TRE_ENABLE);
  272. }
  273. return 0;
  274. }
  275. #ifdef CONFIG_PCI
  276. int board_with_pci(void)
  277. {
  278. u32 reg;
  279. mfsdr(SDR0_PCI0, reg);
  280. return (reg & SDR0_PCI0_PAE_MASK);
  281. }
  282. /*
  283. * pci_pre_init
  284. *
  285. * This routine is called just prior to registering the hose and gives
  286. * the board the opportunity to check things. Returning a value of zero
  287. * indicates that things are bad & PCI initialization should be aborted.
  288. *
  289. * Different boards may wish to customize the pci controller structure
  290. * (add regions, override default access routines, etc) or perform
  291. * certain pre-initialization actions.
  292. *
  293. */
  294. int pci_pre_init(struct pci_controller *hose)
  295. {
  296. unsigned long addr;
  297. if (!board_with_pci()) { return 0; }
  298. /*
  299. * Set priority for all PLB3 devices to 0.
  300. * Set PLB3 arbiter to fair mode.
  301. */
  302. mfsdr(SDR0_AMP1, addr);
  303. mtsdr(SDR0_AMP1, (addr & 0x000000FF) | 0x0000FF00);
  304. addr = mfdcr(PLB3A0_ACR);
  305. mtdcr(PLB3A0_ACR, addr | 0x80000000); /* Sequoia */
  306. /*
  307. * Set priority for all PLB4 devices to 0.
  308. */
  309. mfsdr(SDR0_AMP0, addr);
  310. mtsdr(SDR0_AMP0, (addr & 0x000000FF) | 0x0000FF00);
  311. addr = mfdcr(PLB4A0_ACR) | 0xa0000000; /* Was 0x8---- */
  312. mtdcr(PLB4A0_ACR, addr); /* Sequoia */
  313. /*
  314. * As of errata version 0.4, CHIP_8: Incorrect Write to DDR SDRAM.
  315. * Workaround: Disable write pipelining to DDR SDRAM by setting
  316. * PLB4A0_ACR[WRP] = 0.
  317. */
  318. mtdcr(PLB4A0_ACR, 0); /* PATCH HAB: WRITE PIPELINING OFF */
  319. /* Segment1 */
  320. mtdcr(PLB4A1_ACR, 0); /* PATCH HAB: WRITE PIPELINING OFF */
  321. return board_with_pci();
  322. }
  323. /*
  324. * Override weak default pci_master_init()
  325. */
  326. void pci_master_init(struct pci_controller *hose)
  327. {
  328. if (!board_with_pci())
  329. return;
  330. __pci_master_init(hose);
  331. }
  332. #endif /* defined(CONFIG_PCI) */
  333. #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
  334. void ft_board_setup(void *blob, bd_t *bd)
  335. {
  336. ft_cpu_setup(blob, bd);
  337. }
  338. #endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */
  339. /*
  340. * Hardcoded flash setup:
  341. * Flash 0 is a non-CFI AMD AM29F040 flash, 8 bit flash / 8 bit bus.
  342. */
  343. ulong board_flash_get_legacy (ulong base, int banknum, flash_info_t * info)
  344. {
  345. if (banknum == 0) { /* non-CFI boot flash */
  346. info->portwidth = 1;
  347. info->chipwidth = 1;
  348. info->interface = FLASH_CFI_X8;
  349. return 1;
  350. } else
  351. return 0;
  352. }