README.txt 1.3 KB

1234567891011121314151617181920212223242526272829303132333435363738394041424344454647484950515253545556575859
  1. HCU4 Configuration Details
  2. Memory Bank 0 -- Flash chip
  3. ---------------------------
  4. 0xfff00000 - 0xffffffff
  5. The flash chip is really only 512Kbytes, but the high address bit of
  6. the 1Meg region is ignored, so the flash is replicated through the
  7. region. Thus, this is consistent with a flash base address 0xfff80000.
  8. The placement at the end is to be consistent with reset behavior,
  9. where the processor itself initially uses this bus to load the branch
  10. vector and start running.
  11. On-Chip Memory
  12. --------------
  13. 0xf4000000 - 0xf4000fff
  14. The 405GPr includes a 4K on-chip memory that can be placed however
  15. software chooses. I choose to place the memory at this address, to
  16. keep it out of the cachable areas.
  17. Internal Peripherals
  18. --------------------
  19. 0xef600300 - 0xef6008ff
  20. These are scattered various peripherals internal to the PPC405GPr
  21. chip.
  22. Chip-Select 2: Flash Memory
  23. ---------------------------
  24. 0x70000000
  25. Chip-Select 3: CAN Interface
  26. ----------------------------
  27. 0x7800000
  28. Chip-Select 4: IMC-bus standard
  29. -------------------------------
  30. Our IO-Bus (slow version)
  31. Chip-Select 5: IMC-bus fast (inactive)
  32. --------------------------------------
  33. Our IO-Bus (fast, but not yet use)
  34. Memory Bank 1 -- SDRAM
  35. -------------------------------------
  36. 0x00000000 - 0x1ffffff # Default 32 MB