hihope-rzg2.c 2.9 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * board/hoperun/hihope-rzg2/hihope-rzg2.c
  4. * This file is HiHope RZ/G2[HMN] board support.
  5. *
  6. * Copyright (C) 2021 Renesas Electronics Corporation
  7. */
  8. #include <common.h>
  9. #include <asm/global_data.h>
  10. #include <asm/io.h>
  11. #include <asm/processor.h>
  12. #include <asm/arch/rmobile.h>
  13. #include <asm/arch/rcar-mstp.h>
  14. #include <linux/bitops.h>
  15. #include <linux/delay.h>
  16. #include <linux/libfdt.h>
  17. #define RST_BASE 0xE6160000
  18. #define RST_CA57RESCNT (RST_BASE + 0x40)
  19. #define RST_CA53RESCNT (RST_BASE + 0x44)
  20. #define RST_CA57_CODE 0xA5A5000F
  21. #define RST_CA53_CODE 0x5A5A000F
  22. DECLARE_GLOBAL_DATA_PTR;
  23. #define HSUSB_MSTP704 BIT(4) /* HSUSB */
  24. /* HSUSB block registers */
  25. #define HSUSB_REG_LPSTS 0xE6590102
  26. #define HSUSB_REG_LPSTS_SUSPM_NORMAL BIT(14)
  27. #define HSUSB_REG_UGCTRL2 0xE6590184
  28. #define HSUSB_REG_UGCTRL2_USB0SEL_EHCI 0x10
  29. #define HSUSB_REG_UGCTRL2_RESERVED_3 0x1 /* bit[3:0] should be B'0001 */
  30. #define PRR_REGISTER (0xFFF00044)
  31. int board_init(void)
  32. {
  33. u32 i;
  34. /* address of boot parameters */
  35. gd->bd->bi_boot_params = CONFIG_SYS_TEXT_BASE + 0x50000;
  36. /* Configure the HSUSB block */
  37. mstp_clrbits_le32(SMSTPCR7, SMSTPCR7, HSUSB_MSTP704);
  38. /*
  39. * We need to add a barrier instruction after HSUSB module stop release.
  40. * This barrier instruction can be either reading back the same MSTP
  41. * register or any other register in the same IP block. So like linux
  42. * adding check for MSTPSR register, which indicates the clock has been
  43. * started.
  44. */
  45. for (i = 1000; i > 0; --i) {
  46. if (!(readl(MSTPSR7) & HSUSB_MSTP704))
  47. break;
  48. cpu_relax();
  49. }
  50. /* Select EHCI/OHCI host module for USB2.0 ch0 */
  51. writel(HSUSB_REG_UGCTRL2_USB0SEL_EHCI | HSUSB_REG_UGCTRL2_RESERVED_3,
  52. HSUSB_REG_UGCTRL2);
  53. /* low power status */
  54. setbits_le16(HSUSB_REG_LPSTS, HSUSB_REG_LPSTS_SUSPM_NORMAL);
  55. return 0;
  56. }
  57. void reset_cpu(void)
  58. {
  59. unsigned long midr, cputype;
  60. asm volatile("mrs %0, midr_el1" : "=r" (midr));
  61. cputype = (midr >> 4) & 0xfff;
  62. if (cputype == 0xd03)
  63. writel(RST_CA53_CODE, RST_CA53RESCNT);
  64. else
  65. writel(RST_CA57_CODE, RST_CA57RESCNT);
  66. }
  67. #if defined(CONFIG_MULTI_DTB_FIT)
  68. /* If the firmware passed a device tree, use it for board identification. */
  69. extern u64 rcar_atf_boot_args[];
  70. static bool is_hoperun_hihope_rzg2_board(const char *board_name)
  71. {
  72. void *atf_fdt_blob = (void *)(rcar_atf_boot_args[1]);
  73. bool ret = false;
  74. if ((fdt_magic(atf_fdt_blob) == FDT_MAGIC) &&
  75. (fdt_node_check_compatible(atf_fdt_blob, 0, board_name) == 0))
  76. ret = true;
  77. return ret;
  78. }
  79. int board_fit_config_name_match(const char *name)
  80. {
  81. if (is_hoperun_hihope_rzg2_board("hoperun,hihope-rzg2m") &&
  82. !strcmp(name, "r8a774a1-hihope-rzg2m-u-boot"))
  83. return 0;
  84. if (is_hoperun_hihope_rzg2_board("hoperun,hihope-rzg2n") &&
  85. !strcmp(name, "r8a774b1-hihope-rzg2n-u-boot"))
  86. return 0;
  87. if (is_hoperun_hihope_rzg2_board("hoperun,hihope-rzg2h") &&
  88. !strcmp(name, "r8a774e1-hihope-rzg2h-u-boot"))
  89. return 0;
  90. return -1;
  91. }
  92. #endif