atcspi200_spi.c 9.1 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Andestech ATCSPI200 SPI controller driver.
  4. *
  5. * Copyright 2017 Andes Technology, Inc.
  6. * Author: Rick Chen (rick@andestech.com)
  7. */
  8. #include <common.h>
  9. #include <clk.h>
  10. #include <log.h>
  11. #include <malloc.h>
  12. #include <spi.h>
  13. #include <asm/global_data.h>
  14. #include <asm/io.h>
  15. #include <dm.h>
  16. DECLARE_GLOBAL_DATA_PTR;
  17. #define MAX_TRANSFER_LEN 512
  18. #define CHUNK_SIZE 1
  19. #define SPI_TIMEOUT 0x100000
  20. #define SPI0_BUS 0
  21. #define SPI1_BUS 1
  22. #define SPI0_BASE 0xf0b00000
  23. #define SPI1_BASE 0xf0f00000
  24. #define NSPI_MAX_CS_NUM 1
  25. struct atcspi200_spi_regs {
  26. u32 rev;
  27. u32 reserve1[3];
  28. u32 format; /* 0x10 */
  29. #define DATA_LENGTH(x) ((x-1)<<8)
  30. u32 pio;
  31. u32 reserve2[2];
  32. u32 tctrl; /* 0x20 */
  33. #define TRAMODE_OFFSET 24
  34. #define TRAMODE_MASK (0x0F<<TRAMODE_OFFSET)
  35. #define TRAMODE_WR_SYNC (0<<TRAMODE_OFFSET)
  36. #define TRAMODE_WO (1<<TRAMODE_OFFSET)
  37. #define TRAMODE_RO (2<<TRAMODE_OFFSET)
  38. #define TRAMODE_WR (3<<TRAMODE_OFFSET)
  39. #define TRAMODE_RW (4<<TRAMODE_OFFSET)
  40. #define TRAMODE_WDR (5<<TRAMODE_OFFSET)
  41. #define TRAMODE_RDW (6<<TRAMODE_OFFSET)
  42. #define TRAMODE_NONE (7<<TRAMODE_OFFSET)
  43. #define TRAMODE_DW (8<<TRAMODE_OFFSET)
  44. #define TRAMODE_DR (9<<TRAMODE_OFFSET)
  45. #define WCNT_OFFSET 12
  46. #define WCNT_MASK (0x1FF<<WCNT_OFFSET)
  47. #define RCNT_OFFSET 0
  48. #define RCNT_MASK (0x1FF<<RCNT_OFFSET)
  49. u32 cmd;
  50. u32 addr;
  51. u32 data;
  52. u32 ctrl; /* 0x30 */
  53. #define TXFTH_OFFSET 16
  54. #define RXFTH_OFFSET 8
  55. #define TXDMAEN (1<<4)
  56. #define RXDMAEN (1<<3)
  57. #define TXFRST (1<<2)
  58. #define RXFRST (1<<1)
  59. #define SPIRST (1<<0)
  60. u32 status;
  61. #define TXFFL (1<<23)
  62. #define TXEPTY (1<<22)
  63. #define TXFVE_MASK (0x1F<<16)
  64. #define RXFEM (1<<14)
  65. #define RXFVE_OFFSET (8)
  66. #define RXFVE_MASK (0x1F<<RXFVE_OFFSET)
  67. #define SPIBSY (1<<0)
  68. u32 inten;
  69. u32 intsta;
  70. u32 timing; /* 0x40 */
  71. #define SCLK_DIV_MASK 0xFF
  72. };
  73. struct nds_spi_slave {
  74. volatile struct atcspi200_spi_regs *regs;
  75. int to;
  76. unsigned int freq;
  77. ulong clock;
  78. unsigned int mode;
  79. u8 num_cs;
  80. unsigned int mtiming;
  81. size_t cmd_len;
  82. u8 cmd_buf[16];
  83. size_t data_len;
  84. size_t tran_len;
  85. u8 *din;
  86. u8 *dout;
  87. unsigned int max_transfer_length;
  88. };
  89. static int __atcspi200_spi_set_speed(struct nds_spi_slave *ns)
  90. {
  91. u32 tm;
  92. u8 div;
  93. tm = ns->regs->timing;
  94. tm &= ~SCLK_DIV_MASK;
  95. if(ns->freq >= ns->clock)
  96. div =0xff;
  97. else{
  98. for (div = 0; div < 0xff; div++) {
  99. if (ns->freq >= ns->clock / (2 * (div + 1)))
  100. break;
  101. }
  102. }
  103. tm |= div;
  104. ns->regs->timing = tm;
  105. return 0;
  106. }
  107. static int __atcspi200_spi_claim_bus(struct nds_spi_slave *ns)
  108. {
  109. unsigned int format=0;
  110. ns->regs->ctrl |= (TXFRST|RXFRST|SPIRST);
  111. while((ns->regs->ctrl &(TXFRST|RXFRST|SPIRST))&&(ns->to--))
  112. if(!ns->to)
  113. return -EINVAL;
  114. ns->cmd_len = 0;
  115. format = ns->mode|DATA_LENGTH(8);
  116. ns->regs->format = format;
  117. __atcspi200_spi_set_speed(ns);
  118. return 0;
  119. }
  120. static int __atcspi200_spi_release_bus(struct nds_spi_slave *ns)
  121. {
  122. /* do nothing */
  123. return 0;
  124. }
  125. static int __atcspi200_spi_start(struct nds_spi_slave *ns)
  126. {
  127. int i,olen=0;
  128. int tc = ns->regs->tctrl;
  129. tc &= ~(WCNT_MASK|RCNT_MASK|TRAMODE_MASK);
  130. if ((ns->din)&&(ns->cmd_len))
  131. tc |= TRAMODE_WR;
  132. else if (ns->din)
  133. tc |= TRAMODE_RO;
  134. else
  135. tc |= TRAMODE_WO;
  136. if(ns->dout)
  137. olen = ns->tran_len;
  138. tc |= (ns->cmd_len+olen-1) << WCNT_OFFSET;
  139. if(ns->din)
  140. tc |= (ns->tran_len-1) << RCNT_OFFSET;
  141. ns->regs->tctrl = tc;
  142. ns->regs->cmd = 1;
  143. for (i=0;i<ns->cmd_len;i++)
  144. ns->regs->data = ns->cmd_buf[i];
  145. return 0;
  146. }
  147. static int __atcspi200_spi_stop(struct nds_spi_slave *ns)
  148. {
  149. ns->regs->timing = ns->mtiming;
  150. while ((ns->regs->status & SPIBSY)&&(ns->to--))
  151. if (!ns->to)
  152. return -EINVAL;
  153. return 0;
  154. }
  155. static void __nspi_espi_tx(struct nds_spi_slave *ns, const void *dout)
  156. {
  157. ns->regs->data = *(u8 *)dout;
  158. }
  159. static int __nspi_espi_rx(struct nds_spi_slave *ns, void *din, unsigned int bytes)
  160. {
  161. *(u8 *)din = ns->regs->data;
  162. return bytes;
  163. }
  164. static int __atcspi200_spi_xfer(struct nds_spi_slave *ns,
  165. unsigned int bitlen, const void *data_out, void *data_in,
  166. unsigned long flags)
  167. {
  168. unsigned int event, rx_bytes;
  169. const void *dout = NULL;
  170. void *din = NULL;
  171. int num_blks, num_chunks, max_tran_len, tran_len;
  172. int num_bytes;
  173. u8 *cmd_buf = ns->cmd_buf;
  174. size_t cmd_len = ns->cmd_len;
  175. unsigned long data_len = bitlen / 8;
  176. int rf_cnt;
  177. int ret = 0, timeout = 0;
  178. max_tran_len = ns->max_transfer_length;
  179. switch (flags) {
  180. case SPI_XFER_BEGIN:
  181. cmd_len = ns->cmd_len = data_len;
  182. memcpy(cmd_buf, data_out, cmd_len);
  183. return 0;
  184. case 0:
  185. case SPI_XFER_END:
  186. if (bitlen == 0) {
  187. return 0;
  188. }
  189. ns->data_len = data_len;
  190. ns->din = (u8 *)data_in;
  191. ns->dout = (u8 *)data_out;
  192. break;
  193. case SPI_XFER_BEGIN | SPI_XFER_END:
  194. ns->data_len = 0;
  195. ns->din = 0;
  196. ns->dout = 0;
  197. cmd_len = ns->cmd_len = data_len;
  198. memcpy(cmd_buf, data_out, cmd_len);
  199. data_out = 0;
  200. data_len = 0;
  201. __atcspi200_spi_start(ns);
  202. break;
  203. }
  204. if (data_out)
  205. debug("spi_xfer: data_out %08X(%p) data_in %08X(%p) data_len %lu\n",
  206. *(uint *)data_out, data_out, *(uint *)data_in,
  207. data_in, data_len);
  208. num_chunks = DIV_ROUND_UP(data_len, max_tran_len);
  209. din = data_in;
  210. dout = data_out;
  211. while (num_chunks--) {
  212. tran_len = min((size_t)data_len, (size_t)max_tran_len);
  213. ns->tran_len = tran_len;
  214. num_blks = DIV_ROUND_UP(tran_len , CHUNK_SIZE);
  215. num_bytes = (tran_len) % CHUNK_SIZE;
  216. timeout = SPI_TIMEOUT;
  217. if(num_bytes == 0)
  218. num_bytes = CHUNK_SIZE;
  219. __atcspi200_spi_start(ns);
  220. while (num_blks && (timeout--)) {
  221. event = in_le32(&ns->regs->status);
  222. if ((event & TXEPTY) && (data_out)) {
  223. __nspi_espi_tx(ns, dout);
  224. num_blks -= CHUNK_SIZE;
  225. dout += CHUNK_SIZE;
  226. }
  227. if ((event & RXFVE_MASK) && (data_in)) {
  228. rf_cnt = ((event & RXFVE_MASK)>> RXFVE_OFFSET);
  229. if (rf_cnt >= CHUNK_SIZE)
  230. rx_bytes = CHUNK_SIZE;
  231. else if (num_blks == 1 && rf_cnt == num_bytes)
  232. rx_bytes = num_bytes;
  233. else
  234. continue;
  235. if (__nspi_espi_rx(ns, din, rx_bytes) == rx_bytes) {
  236. num_blks -= CHUNK_SIZE;
  237. din = (unsigned char *)din + rx_bytes;
  238. }
  239. }
  240. if (!timeout) {
  241. debug("spi_xfer: %s() timeout\n", __func__);
  242. break;
  243. }
  244. }
  245. data_len -= tran_len;
  246. if(data_len)
  247. {
  248. ns->cmd_buf[1] += ((tran_len>>16)&0xff);
  249. ns->cmd_buf[2] += ((tran_len>>8)&0xff);
  250. ns->cmd_buf[3] += ((tran_len)&0xff);
  251. ns->data_len = data_len;
  252. }
  253. ret = __atcspi200_spi_stop(ns);
  254. }
  255. ret = __atcspi200_spi_stop(ns);
  256. return ret;
  257. }
  258. static int atcspi200_spi_set_speed(struct udevice *bus, uint max_hz)
  259. {
  260. struct nds_spi_slave *ns = dev_get_priv(bus);
  261. debug("%s speed %u\n", __func__, max_hz);
  262. ns->freq = max_hz;
  263. __atcspi200_spi_set_speed(ns);
  264. return 0;
  265. }
  266. static int atcspi200_spi_set_mode(struct udevice *bus, uint mode)
  267. {
  268. struct nds_spi_slave *ns = dev_get_priv(bus);
  269. debug("%s mode %u\n", __func__, mode);
  270. ns->mode = mode;
  271. return 0;
  272. }
  273. static int atcspi200_spi_claim_bus(struct udevice *dev)
  274. {
  275. struct dm_spi_slave_plat *slave_plat =
  276. dev_get_parent_plat(dev);
  277. struct udevice *bus = dev->parent;
  278. struct nds_spi_slave *ns = dev_get_priv(bus);
  279. if (slave_plat->cs >= ns->num_cs) {
  280. printf("Invalid SPI chipselect\n");
  281. return -EINVAL;
  282. }
  283. return __atcspi200_spi_claim_bus(ns);
  284. }
  285. static int atcspi200_spi_release_bus(struct udevice *dev)
  286. {
  287. struct nds_spi_slave *ns = dev_get_priv(dev->parent);
  288. return __atcspi200_spi_release_bus(ns);
  289. }
  290. static int atcspi200_spi_xfer(struct udevice *dev, unsigned int bitlen,
  291. const void *dout, void *din,
  292. unsigned long flags)
  293. {
  294. struct udevice *bus = dev->parent;
  295. struct nds_spi_slave *ns = dev_get_priv(bus);
  296. return __atcspi200_spi_xfer(ns, bitlen, dout, din, flags);
  297. }
  298. static int atcspi200_spi_get_clk(struct udevice *bus)
  299. {
  300. struct nds_spi_slave *ns = dev_get_priv(bus);
  301. struct clk clk;
  302. ulong clk_rate;
  303. int ret;
  304. ret = clk_get_by_index(bus, 0, &clk);
  305. if (ret)
  306. return -EINVAL;
  307. clk_rate = clk_get_rate(&clk);
  308. if (!clk_rate)
  309. return -EINVAL;
  310. ns->clock = clk_rate;
  311. clk_free(&clk);
  312. return 0;
  313. }
  314. static int atcspi200_spi_probe(struct udevice *bus)
  315. {
  316. struct nds_spi_slave *ns = dev_get_priv(bus);
  317. ns->to = SPI_TIMEOUT;
  318. ns->max_transfer_length = MAX_TRANSFER_LEN;
  319. ns->mtiming = ns->regs->timing;
  320. atcspi200_spi_get_clk(bus);
  321. return 0;
  322. }
  323. static int atcspi200_ofdata_to_platadata(struct udevice *bus)
  324. {
  325. struct nds_spi_slave *ns = dev_get_priv(bus);
  326. const void *blob = gd->fdt_blob;
  327. int node = dev_of_offset(bus);
  328. ns->regs = map_physmem(dev_read_addr(bus),
  329. sizeof(struct atcspi200_spi_regs),
  330. MAP_NOCACHE);
  331. if (!ns->regs) {
  332. printf("%s: could not map device address\n", __func__);
  333. return -EINVAL;
  334. }
  335. ns->num_cs = fdtdec_get_int(blob, node, "num-cs", 4);
  336. return 0;
  337. }
  338. static const struct dm_spi_ops atcspi200_spi_ops = {
  339. .claim_bus = atcspi200_spi_claim_bus,
  340. .release_bus = atcspi200_spi_release_bus,
  341. .xfer = atcspi200_spi_xfer,
  342. .set_speed = atcspi200_spi_set_speed,
  343. .set_mode = atcspi200_spi_set_mode,
  344. };
  345. static const struct udevice_id atcspi200_spi_ids[] = {
  346. { .compatible = "andestech,atcspi200" },
  347. { }
  348. };
  349. U_BOOT_DRIVER(atcspi200_spi) = {
  350. .name = "atcspi200_spi",
  351. .id = UCLASS_SPI,
  352. .of_match = atcspi200_spi_ids,
  353. .ops = &atcspi200_spi_ops,
  354. .of_to_plat = atcspi200_ofdata_to_platadata,
  355. .priv_auto = sizeof(struct nds_spi_slave),
  356. .probe = atcspi200_spi_probe,
  357. };