tsc_timer.c 12 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (c) 2012 The Chromium OS Authors.
  4. *
  5. * TSC calibration codes are adapted from Linux kernel
  6. * arch/x86/kernel/tsc_msr.c and arch/x86/kernel/tsc.c
  7. */
  8. #include <common.h>
  9. #include <dm.h>
  10. #include <malloc.h>
  11. #include <time.h>
  12. #include <timer.h>
  13. #include <asm/cpu.h>
  14. #include <asm/io.h>
  15. #include <asm/i8254.h>
  16. #include <asm/ibmpc.h>
  17. #include <asm/msr.h>
  18. #include <asm/u-boot-x86.h>
  19. #define MAX_NUM_FREQS 9
  20. #define INTEL_FAM6_SKYLAKE_MOBILE 0x4E
  21. #define INTEL_FAM6_ATOM_GOLDMONT 0x5C /* Apollo Lake */
  22. #define INTEL_FAM6_SKYLAKE_DESKTOP 0x5E
  23. #define INTEL_FAM6_ATOM_GOLDMONT_X 0x5F /* Denverton */
  24. #define INTEL_FAM6_KABYLAKE_MOBILE 0x8E
  25. #define INTEL_FAM6_KABYLAKE_DESKTOP 0x9E
  26. DECLARE_GLOBAL_DATA_PTR;
  27. /*
  28. * native_calibrate_tsc
  29. * Determine TSC frequency via CPUID, else return 0.
  30. */
  31. static unsigned long native_calibrate_tsc(void)
  32. {
  33. struct cpuid_result tsc_info;
  34. unsigned int crystal_freq;
  35. if (gd->arch.x86_vendor != X86_VENDOR_INTEL)
  36. return 0;
  37. if (cpuid_eax(0) < 0x15)
  38. return 0;
  39. tsc_info = cpuid(0x15);
  40. if (tsc_info.ebx == 0 || tsc_info.eax == 0)
  41. return 0;
  42. crystal_freq = tsc_info.ecx / 1000;
  43. if (!crystal_freq) {
  44. switch (gd->arch.x86_model) {
  45. case INTEL_FAM6_SKYLAKE_MOBILE:
  46. case INTEL_FAM6_SKYLAKE_DESKTOP:
  47. case INTEL_FAM6_KABYLAKE_MOBILE:
  48. case INTEL_FAM6_KABYLAKE_DESKTOP:
  49. crystal_freq = 24000; /* 24.0 MHz */
  50. break;
  51. case INTEL_FAM6_ATOM_GOLDMONT_X:
  52. crystal_freq = 25000; /* 25.0 MHz */
  53. break;
  54. case INTEL_FAM6_ATOM_GOLDMONT:
  55. crystal_freq = 19200; /* 19.2 MHz */
  56. break;
  57. default:
  58. return 0;
  59. }
  60. }
  61. return (crystal_freq * tsc_info.ebx / tsc_info.eax) / 1000;
  62. }
  63. static unsigned long cpu_mhz_from_cpuid(void)
  64. {
  65. if (gd->arch.x86_vendor != X86_VENDOR_INTEL)
  66. return 0;
  67. if (cpuid_eax(0) < 0x16)
  68. return 0;
  69. return cpuid_eax(0x16);
  70. }
  71. /*
  72. * According to Intel 64 and IA-32 System Programming Guide,
  73. * if MSR_PERF_STAT[31] is set, the maximum resolved bus ratio can be
  74. * read in MSR_PLATFORM_ID[12:8], otherwise in MSR_PERF_STAT[44:40].
  75. * Unfortunately some Intel Atom SoCs aren't quite compliant to this,
  76. * so we need manually differentiate SoC families. This is what the
  77. * field msr_plat does.
  78. */
  79. struct freq_desc {
  80. u8 x86_family; /* CPU family */
  81. u8 x86_model; /* model */
  82. /* 2: use 100MHz, 1: use MSR_PLATFORM_INFO, 0: MSR_IA32_PERF_STATUS */
  83. u8 msr_plat;
  84. u32 freqs[MAX_NUM_FREQS];
  85. };
  86. static struct freq_desc freq_desc_tables[] = {
  87. /* PNW */
  88. { 6, 0x27, 0, { 0, 0, 0, 0, 0, 99840, 0, 83200, 0 } },
  89. /* CLV+ */
  90. { 6, 0x35, 0, { 0, 133200, 0, 0, 0, 99840, 0, 83200, 0 } },
  91. /* TNG - Intel Atom processor Z3400 series */
  92. { 6, 0x4a, 1, { 0, 100000, 133300, 0, 0, 0, 0, 0, 0 } },
  93. /* VLV2 - Intel Atom processor E3000, Z3600, Z3700 series */
  94. { 6, 0x37, 1, { 83300, 100000, 133300, 116700, 80000, 0, 0, 0, 0 } },
  95. /* ANN - Intel Atom processor Z3500 series */
  96. { 6, 0x5a, 1, { 83300, 100000, 133300, 100000, 0, 0, 0, 0, 0 } },
  97. /* AMT - Intel Atom processor X7-Z8000 and X5-Z8000 series */
  98. { 6, 0x4c, 1, { 83300, 100000, 133300, 116700,
  99. 80000, 93300, 90000, 88900, 87500 } },
  100. /* Ivybridge */
  101. { 6, 0x3a, 2, { 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
  102. };
  103. static int match_cpu(u8 family, u8 model)
  104. {
  105. int i;
  106. for (i = 0; i < ARRAY_SIZE(freq_desc_tables); i++) {
  107. if ((family == freq_desc_tables[i].x86_family) &&
  108. (model == freq_desc_tables[i].x86_model))
  109. return i;
  110. }
  111. return -1;
  112. }
  113. /* Map CPU reference clock freq ID(0-7) to CPU reference clock freq(KHz) */
  114. #define id_to_freq(cpu_index, freq_id) \
  115. (freq_desc_tables[cpu_index].freqs[freq_id])
  116. /*
  117. * TSC on Intel Atom SoCs capable of determining TSC frequency by MSR is
  118. * reliable and the frequency is known (provided by HW).
  119. *
  120. * On these platforms PIT/HPET is generally not available so calibration won't
  121. * work at all and there is no other clocksource to act as a watchdog for the
  122. * TSC, so we have no other choice than to trust it.
  123. *
  124. * Returns the TSC frequency in MHz or 0 if HW does not provide it.
  125. */
  126. static unsigned long __maybe_unused cpu_mhz_from_msr(void)
  127. {
  128. u32 lo, hi, ratio, freq_id, freq;
  129. unsigned long res;
  130. int cpu_index;
  131. if (gd->arch.x86_vendor != X86_VENDOR_INTEL)
  132. return 0;
  133. cpu_index = match_cpu(gd->arch.x86, gd->arch.x86_model);
  134. if (cpu_index < 0)
  135. return 0;
  136. if (freq_desc_tables[cpu_index].msr_plat) {
  137. rdmsr(MSR_PLATFORM_INFO, lo, hi);
  138. ratio = (lo >> 8) & 0xff;
  139. } else {
  140. rdmsr(MSR_IA32_PERF_STATUS, lo, hi);
  141. ratio = (hi >> 8) & 0x1f;
  142. }
  143. debug("Maximum core-clock to bus-clock ratio: 0x%x\n", ratio);
  144. if (freq_desc_tables[cpu_index].msr_plat == 2) {
  145. /* TODO: Figure out how best to deal with this */
  146. freq = 100000;
  147. debug("Using frequency: %u KHz\n", freq);
  148. } else {
  149. /* Get FSB FREQ ID */
  150. rdmsr(MSR_FSB_FREQ, lo, hi);
  151. freq_id = lo & 0x7;
  152. freq = id_to_freq(cpu_index, freq_id);
  153. debug("Resolved frequency ID: %u, frequency: %u KHz\n",
  154. freq_id, freq);
  155. }
  156. /* TSC frequency = maximum resolved freq * maximum resolved bus ratio */
  157. res = freq * ratio / 1000;
  158. debug("TSC runs at %lu MHz\n", res);
  159. return res;
  160. }
  161. /*
  162. * This reads the current MSB of the PIT counter, and
  163. * checks if we are running on sufficiently fast and
  164. * non-virtualized hardware.
  165. *
  166. * Our expectations are:
  167. *
  168. * - the PIT is running at roughly 1.19MHz
  169. *
  170. * - each IO is going to take about 1us on real hardware,
  171. * but we allow it to be much faster (by a factor of 10) or
  172. * _slightly_ slower (ie we allow up to a 2us read+counter
  173. * update - anything else implies a unacceptably slow CPU
  174. * or PIT for the fast calibration to work.
  175. *
  176. * - with 256 PIT ticks to read the value, we have 214us to
  177. * see the same MSB (and overhead like doing a single TSC
  178. * read per MSB value etc).
  179. *
  180. * - We're doing 2 reads per loop (LSB, MSB), and we expect
  181. * them each to take about a microsecond on real hardware.
  182. * So we expect a count value of around 100. But we'll be
  183. * generous, and accept anything over 50.
  184. *
  185. * - if the PIT is stuck, and we see *many* more reads, we
  186. * return early (and the next caller of pit_expect_msb()
  187. * then consider it a failure when they don't see the
  188. * next expected value).
  189. *
  190. * These expectations mean that we know that we have seen the
  191. * transition from one expected value to another with a fairly
  192. * high accuracy, and we didn't miss any events. We can thus
  193. * use the TSC value at the transitions to calculate a pretty
  194. * good value for the TSC frequencty.
  195. */
  196. static inline int pit_verify_msb(unsigned char val)
  197. {
  198. /* Ignore LSB */
  199. inb(0x42);
  200. return inb(0x42) == val;
  201. }
  202. static inline int pit_expect_msb(unsigned char val, u64 *tscp,
  203. unsigned long *deltap)
  204. {
  205. int count;
  206. u64 tsc = 0, prev_tsc = 0;
  207. for (count = 0; count < 50000; count++) {
  208. if (!pit_verify_msb(val))
  209. break;
  210. prev_tsc = tsc;
  211. tsc = rdtsc();
  212. }
  213. *deltap = rdtsc() - prev_tsc;
  214. *tscp = tsc;
  215. /*
  216. * We require _some_ success, but the quality control
  217. * will be based on the error terms on the TSC values.
  218. */
  219. return count > 5;
  220. }
  221. /*
  222. * How many MSB values do we want to see? We aim for
  223. * a maximum error rate of 500ppm (in practice the
  224. * real error is much smaller), but refuse to spend
  225. * more than 50ms on it.
  226. */
  227. #define MAX_QUICK_PIT_MS 50
  228. #define MAX_QUICK_PIT_ITERATIONS (MAX_QUICK_PIT_MS * PIT_TICK_RATE / 1000 / 256)
  229. static unsigned long __maybe_unused quick_pit_calibrate(void)
  230. {
  231. int i;
  232. u64 tsc, delta;
  233. unsigned long d1, d2;
  234. /* Set the Gate high, disable speaker */
  235. outb((inb(0x61) & ~0x02) | 0x01, 0x61);
  236. /*
  237. * Counter 2, mode 0 (one-shot), binary count
  238. *
  239. * NOTE! Mode 2 decrements by two (and then the
  240. * output is flipped each time, giving the same
  241. * final output frequency as a decrement-by-one),
  242. * so mode 0 is much better when looking at the
  243. * individual counts.
  244. */
  245. outb(0xb0, 0x43);
  246. /* Start at 0xffff */
  247. outb(0xff, 0x42);
  248. outb(0xff, 0x42);
  249. /*
  250. * The PIT starts counting at the next edge, so we
  251. * need to delay for a microsecond. The easiest way
  252. * to do that is to just read back the 16-bit counter
  253. * once from the PIT.
  254. */
  255. pit_verify_msb(0);
  256. if (pit_expect_msb(0xff, &tsc, &d1)) {
  257. for (i = 1; i <= MAX_QUICK_PIT_ITERATIONS; i++) {
  258. if (!pit_expect_msb(0xff-i, &delta, &d2))
  259. break;
  260. /*
  261. * Iterate until the error is less than 500 ppm
  262. */
  263. delta -= tsc;
  264. if (d1+d2 >= delta >> 11)
  265. continue;
  266. /*
  267. * Check the PIT one more time to verify that
  268. * all TSC reads were stable wrt the PIT.
  269. *
  270. * This also guarantees serialization of the
  271. * last cycle read ('d2') in pit_expect_msb.
  272. */
  273. if (!pit_verify_msb(0xfe - i))
  274. break;
  275. goto success;
  276. }
  277. }
  278. debug("Fast TSC calibration failed\n");
  279. return 0;
  280. success:
  281. /*
  282. * Ok, if we get here, then we've seen the
  283. * MSB of the PIT decrement 'i' times, and the
  284. * error has shrunk to less than 500 ppm.
  285. *
  286. * As a result, we can depend on there not being
  287. * any odd delays anywhere, and the TSC reads are
  288. * reliable (within the error).
  289. *
  290. * kHz = ticks / time-in-seconds / 1000;
  291. * kHz = (t2 - t1) / (I * 256 / PIT_TICK_RATE) / 1000
  292. * kHz = ((t2 - t1) * PIT_TICK_RATE) / (I * 256 * 1000)
  293. */
  294. delta *= PIT_TICK_RATE;
  295. delta /= (i*256*1000);
  296. debug("Fast TSC calibration using PIT\n");
  297. return delta / 1000;
  298. }
  299. /* Get the speed of the TSC timer in MHz */
  300. unsigned notrace long get_tbclk_mhz(void)
  301. {
  302. return get_tbclk() / 1000000;
  303. }
  304. static ulong get_ms_timer(void)
  305. {
  306. return (get_ticks() * 1000) / get_tbclk();
  307. }
  308. ulong get_timer(ulong base)
  309. {
  310. return get_ms_timer() - base;
  311. }
  312. ulong notrace timer_get_us(void)
  313. {
  314. return get_ticks() / get_tbclk_mhz();
  315. }
  316. ulong timer_get_boot_us(void)
  317. {
  318. return timer_get_us();
  319. }
  320. void __udelay(unsigned long usec)
  321. {
  322. u64 now = get_ticks();
  323. u64 stop;
  324. stop = now + usec * get_tbclk_mhz();
  325. while ((int64_t)(stop - get_ticks()) > 0)
  326. #if defined(CONFIG_QEMU) && defined(CONFIG_SMP)
  327. /*
  328. * Add a 'pause' instruction on qemu target,
  329. * to give other VCPUs a chance to run.
  330. */
  331. asm volatile("pause");
  332. #else
  333. ;
  334. #endif
  335. }
  336. static int tsc_timer_get_count(struct udevice *dev, u64 *count)
  337. {
  338. u64 now_tick = rdtsc();
  339. *count = now_tick - gd->arch.tsc_base;
  340. return 0;
  341. }
  342. static void tsc_timer_ensure_setup(bool early)
  343. {
  344. if (gd->arch.tsc_inited)
  345. return;
  346. gd->arch.tsc_base = rdtsc();
  347. if (!gd->arch.clock_rate) {
  348. unsigned long fast_calibrate;
  349. fast_calibrate = native_calibrate_tsc();
  350. if (fast_calibrate)
  351. goto done;
  352. fast_calibrate = cpu_mhz_from_cpuid();
  353. if (fast_calibrate)
  354. goto done;
  355. fast_calibrate = cpu_mhz_from_msr();
  356. if (fast_calibrate)
  357. goto done;
  358. fast_calibrate = quick_pit_calibrate();
  359. if (fast_calibrate)
  360. goto done;
  361. if (early)
  362. fast_calibrate = CONFIG_X86_TSC_TIMER_EARLY_FREQ;
  363. else
  364. return;
  365. done:
  366. gd->arch.clock_rate = fast_calibrate * 1000000;
  367. }
  368. gd->arch.tsc_inited = true;
  369. }
  370. static int tsc_timer_probe(struct udevice *dev)
  371. {
  372. struct timer_dev_priv *uc_priv = dev_get_uclass_priv(dev);
  373. /* Try hardware calibration first */
  374. tsc_timer_ensure_setup(false);
  375. if (!gd->arch.clock_rate) {
  376. /*
  377. * Use the clock frequency specified in the
  378. * device tree as last resort
  379. */
  380. if (!uc_priv->clock_rate)
  381. panic("TSC frequency is ZERO");
  382. } else {
  383. uc_priv->clock_rate = gd->arch.clock_rate;
  384. }
  385. return 0;
  386. }
  387. unsigned long notrace timer_early_get_rate(void)
  388. {
  389. /*
  390. * When TSC timer is used as the early timer, be warned that the timer
  391. * clock rate can only be calibrated via some hardware ways. Specifying
  392. * it in the device tree won't work for the early timer.
  393. */
  394. tsc_timer_ensure_setup(true);
  395. return gd->arch.clock_rate;
  396. }
  397. u64 notrace timer_early_get_count(void)
  398. {
  399. tsc_timer_ensure_setup(true);
  400. return rdtsc() - gd->arch.tsc_base;
  401. }
  402. static const struct timer_ops tsc_timer_ops = {
  403. .get_count = tsc_timer_get_count,
  404. };
  405. static const struct udevice_id tsc_timer_ids[] = {
  406. { .compatible = "x86,tsc-timer", },
  407. { }
  408. };
  409. U_BOOT_DRIVER(tsc_timer) = {
  410. .name = "tsc_timer",
  411. .id = UCLASS_TIMER,
  412. .of_match = tsc_timer_ids,
  413. .probe = tsc_timer_probe,
  414. .ops = &tsc_timer_ops,
  415. };