pic32_eth.c 15 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (c) 2015 Purna Chandra Mandal <purna.mandal@microchip.com>
  4. *
  5. */
  6. #include <common.h>
  7. #include <errno.h>
  8. #include <dm.h>
  9. #include <net.h>
  10. #include <miiphy.h>
  11. #include <console.h>
  12. #include <time.h>
  13. #include <wait_bit.h>
  14. #include <asm/gpio.h>
  15. #include "pic32_eth.h"
  16. #define MAX_RX_BUF_SIZE 1536
  17. #define MAX_RX_DESCR PKTBUFSRX
  18. #define MAX_TX_DESCR 2
  19. DECLARE_GLOBAL_DATA_PTR;
  20. struct pic32eth_dev {
  21. struct eth_dma_desc rxd_ring[MAX_RX_DESCR];
  22. struct eth_dma_desc txd_ring[MAX_TX_DESCR];
  23. u32 rxd_idx; /* index of RX desc to read */
  24. /* regs */
  25. struct pic32_ectl_regs *ectl_regs;
  26. struct pic32_emac_regs *emac_regs;
  27. /* Phy */
  28. struct phy_device *phydev;
  29. phy_interface_t phyif;
  30. u32 phy_addr;
  31. struct gpio_desc rst_gpio;
  32. };
  33. void __weak board_netphy_reset(void *dev)
  34. {
  35. struct pic32eth_dev *priv = dev;
  36. if (!dm_gpio_is_valid(&priv->rst_gpio))
  37. return;
  38. /* phy reset */
  39. dm_gpio_set_value(&priv->rst_gpio, 0);
  40. udelay(300);
  41. dm_gpio_set_value(&priv->rst_gpio, 1);
  42. udelay(300);
  43. }
  44. /* Initialize mii(MDIO) interface, discover which PHY is
  45. * attached to the device, and configure it properly.
  46. */
  47. static int pic32_mii_init(struct pic32eth_dev *priv)
  48. {
  49. struct pic32_ectl_regs *ectl_p = priv->ectl_regs;
  50. struct pic32_emac_regs *emac_p = priv->emac_regs;
  51. /* board phy reset */
  52. board_netphy_reset(priv);
  53. /* disable RX, TX & all transactions */
  54. writel(ETHCON_ON | ETHCON_TXRTS | ETHCON_RXEN, &ectl_p->con1.clr);
  55. /* wait till busy */
  56. wait_for_bit_le32(&ectl_p->stat.raw, ETHSTAT_BUSY, false,
  57. CONFIG_SYS_HZ, false);
  58. /* turn controller ON to access PHY over MII */
  59. writel(ETHCON_ON, &ectl_p->con1.set);
  60. mdelay(10);
  61. /* reset MAC */
  62. writel(EMAC_SOFTRESET, &emac_p->cfg1.set); /* reset assert */
  63. mdelay(10);
  64. writel(EMAC_SOFTRESET, &emac_p->cfg1.clr); /* reset deassert */
  65. /* initialize MDIO/MII */
  66. if (priv->phyif == PHY_INTERFACE_MODE_RMII) {
  67. writel(EMAC_RMII_RESET, &emac_p->supp.set);
  68. mdelay(10);
  69. writel(EMAC_RMII_RESET, &emac_p->supp.clr);
  70. }
  71. return pic32_mdio_init(PIC32_MDIO_NAME, (ulong)&emac_p->mii);
  72. }
  73. static int pic32_phy_init(struct pic32eth_dev *priv, struct udevice *dev)
  74. {
  75. struct mii_dev *mii;
  76. mii = miiphy_get_dev_by_name(PIC32_MDIO_NAME);
  77. /* find & connect PHY */
  78. priv->phydev = phy_connect(mii, priv->phy_addr,
  79. dev, priv->phyif);
  80. if (!priv->phydev) {
  81. printf("%s: %s: Error, PHY connect\n", __FILE__, __func__);
  82. return 0;
  83. }
  84. /* Wait for phy to complete reset */
  85. mdelay(10);
  86. /* configure supported modes */
  87. priv->phydev->supported = SUPPORTED_10baseT_Half |
  88. SUPPORTED_10baseT_Full |
  89. SUPPORTED_100baseT_Half |
  90. SUPPORTED_100baseT_Full |
  91. SUPPORTED_Autoneg;
  92. priv->phydev->advertising = ADVERTISED_10baseT_Half |
  93. ADVERTISED_10baseT_Full |
  94. ADVERTISED_100baseT_Half |
  95. ADVERTISED_100baseT_Full |
  96. ADVERTISED_Autoneg;
  97. priv->phydev->autoneg = AUTONEG_ENABLE;
  98. return 0;
  99. }
  100. /* Configure MAC based on negotiated speed and duplex
  101. * reported by PHY.
  102. */
  103. static int pic32_mac_adjust_link(struct pic32eth_dev *priv)
  104. {
  105. struct phy_device *phydev = priv->phydev;
  106. struct pic32_emac_regs *emac_p = priv->emac_regs;
  107. if (!phydev->link) {
  108. printf("%s: No link.\n", phydev->dev->name);
  109. return -EINVAL;
  110. }
  111. if (phydev->duplex) {
  112. writel(EMAC_FULLDUP, &emac_p->cfg2.set);
  113. writel(FULLDUP_GAP_TIME, &emac_p->ipgt.raw);
  114. } else {
  115. writel(EMAC_FULLDUP, &emac_p->cfg2.clr);
  116. writel(HALFDUP_GAP_TIME, &emac_p->ipgt.raw);
  117. }
  118. switch (phydev->speed) {
  119. case SPEED_100:
  120. writel(EMAC_RMII_SPD100, &emac_p->supp.set);
  121. break;
  122. case SPEED_10:
  123. writel(EMAC_RMII_SPD100, &emac_p->supp.clr);
  124. break;
  125. default:
  126. printf("%s: Speed was bad\n", phydev->dev->name);
  127. return -EINVAL;
  128. }
  129. printf("pic32eth: PHY is %s with %dbase%s, %s\n",
  130. phydev->drv->name, phydev->speed,
  131. (phydev->port == PORT_TP) ? "T" : "X",
  132. (phydev->duplex) ? "full" : "half");
  133. return 0;
  134. }
  135. static void pic32_mac_init(struct pic32eth_dev *priv, u8 *macaddr)
  136. {
  137. struct pic32_emac_regs *emac_p = priv->emac_regs;
  138. u32 stat = 0, v;
  139. u64 expire;
  140. v = EMAC_TXPAUSE | EMAC_RXPAUSE | EMAC_RXENABLE;
  141. writel(v, &emac_p->cfg1.raw);
  142. v = EMAC_EXCESS | EMAC_AUTOPAD | EMAC_PADENABLE |
  143. EMAC_CRCENABLE | EMAC_LENGTHCK | EMAC_FULLDUP;
  144. writel(v, &emac_p->cfg2.raw);
  145. /* recommended back-to-back inter-packet gap for 10 Mbps half duplex */
  146. writel(HALFDUP_GAP_TIME, &emac_p->ipgt.raw);
  147. /* recommended non-back-to-back interpacket gap is 0xc12 */
  148. writel(0xc12, &emac_p->ipgr.raw);
  149. /* recommended collision window retry limit is 0x370F */
  150. writel(0x370f, &emac_p->clrt.raw);
  151. /* set maximum frame length: allow VLAN tagged frame */
  152. writel(0x600, &emac_p->maxf.raw);
  153. /* set the mac address */
  154. writel(macaddr[0] | (macaddr[1] << 8), &emac_p->sa2.raw);
  155. writel(macaddr[2] | (macaddr[3] << 8), &emac_p->sa1.raw);
  156. writel(macaddr[4] | (macaddr[5] << 8), &emac_p->sa0.raw);
  157. /* default, enable 10 Mbps operation */
  158. writel(EMAC_RMII_SPD100, &emac_p->supp.clr);
  159. /* wait until link status UP or deadline elapsed */
  160. expire = get_ticks() + get_tbclk() * 2;
  161. for (; get_ticks() < expire;) {
  162. stat = phy_read(priv->phydev, priv->phy_addr, MII_BMSR);
  163. if (stat & BMSR_LSTATUS)
  164. break;
  165. }
  166. if (!(stat & BMSR_LSTATUS))
  167. printf("MAC: Link is DOWN!\n");
  168. /* delay to stabilize before any tx/rx */
  169. mdelay(10);
  170. }
  171. static void pic32_mac_reset(struct pic32eth_dev *priv)
  172. {
  173. struct pic32_emac_regs *emac_p = priv->emac_regs;
  174. struct mii_dev *mii;
  175. /* Reset MAC */
  176. writel(EMAC_SOFTRESET, &emac_p->cfg1.raw);
  177. mdelay(10);
  178. /* clear reset */
  179. writel(0, &emac_p->cfg1.raw);
  180. /* Reset MII */
  181. mii = priv->phydev->bus;
  182. if (mii && mii->reset)
  183. mii->reset(mii);
  184. }
  185. /* initializes the MAC and PHY, then establishes a link */
  186. static void pic32_ctrl_reset(struct pic32eth_dev *priv)
  187. {
  188. struct pic32_ectl_regs *ectl_p = priv->ectl_regs;
  189. u32 v;
  190. /* disable RX, TX & any other transactions */
  191. writel(ETHCON_ON | ETHCON_TXRTS | ETHCON_RXEN, &ectl_p->con1.clr);
  192. /* wait till busy */
  193. wait_for_bit_le32(&ectl_p->stat.raw, ETHSTAT_BUSY, false,
  194. CONFIG_SYS_HZ, false);
  195. /* decrement received buffcnt to zero. */
  196. while (readl(&ectl_p->stat.raw) & ETHSTAT_BUFCNT)
  197. writel(ETHCON_BUFCDEC, &ectl_p->con1.set);
  198. /* clear any existing interrupt event */
  199. writel(0xffffffff, &ectl_p->irq.clr);
  200. /* clear RX/TX start address */
  201. writel(0xffffffff, &ectl_p->txst.clr);
  202. writel(0xffffffff, &ectl_p->rxst.clr);
  203. /* clear the receive filters */
  204. writel(0x00ff, &ectl_p->rxfc.clr);
  205. /* set the receive filters
  206. * ETH_FILT_CRC_ERR_REJECT
  207. * ETH_FILT_RUNT_REJECT
  208. * ETH_FILT_UCAST_ACCEPT
  209. * ETH_FILT_MCAST_ACCEPT
  210. * ETH_FILT_BCAST_ACCEPT
  211. */
  212. v = ETHRXFC_BCEN | ETHRXFC_MCEN | ETHRXFC_UCEN |
  213. ETHRXFC_RUNTEN | ETHRXFC_CRCOKEN;
  214. writel(v, &ectl_p->rxfc.set);
  215. /* turn controller ON to access PHY over MII */
  216. writel(ETHCON_ON, &ectl_p->con1.set);
  217. }
  218. static void pic32_rx_desc_init(struct pic32eth_dev *priv)
  219. {
  220. struct pic32_ectl_regs *ectl_p = priv->ectl_regs;
  221. struct eth_dma_desc *rxd;
  222. u32 idx, bufsz;
  223. priv->rxd_idx = 0;
  224. for (idx = 0; idx < MAX_RX_DESCR; idx++) {
  225. rxd = &priv->rxd_ring[idx];
  226. /* hw owned */
  227. rxd->hdr = EDH_NPV | EDH_EOWN | EDH_STICKY;
  228. /* packet buffer address */
  229. rxd->data_buff = virt_to_phys(net_rx_packets[idx]);
  230. /* link to next desc */
  231. rxd->next_ed = virt_to_phys(rxd + 1);
  232. /* reset status */
  233. rxd->stat1 = 0;
  234. rxd->stat2 = 0;
  235. /* decrement bufcnt */
  236. writel(ETHCON_BUFCDEC, &ectl_p->con1.set);
  237. }
  238. /* link last descr to beginning of list */
  239. rxd->next_ed = virt_to_phys(&priv->rxd_ring[0]);
  240. /* flush rx ring */
  241. flush_dcache_range((ulong)priv->rxd_ring,
  242. (ulong)priv->rxd_ring + sizeof(priv->rxd_ring));
  243. /* set rx desc-ring start address */
  244. writel((ulong)virt_to_phys(&priv->rxd_ring[0]), &ectl_p->rxst.raw);
  245. /* RX Buffer size */
  246. bufsz = readl(&ectl_p->con2.raw);
  247. bufsz &= ~(ETHCON_RXBUFSZ << ETHCON_RXBUFSZ_SHFT);
  248. bufsz |= ((MAX_RX_BUF_SIZE / 16) << ETHCON_RXBUFSZ_SHFT);
  249. writel(bufsz, &ectl_p->con2.raw);
  250. /* enable the receiver in hardware which allows hardware
  251. * to DMA received pkts to the descriptor pointer address.
  252. */
  253. writel(ETHCON_RXEN, &ectl_p->con1.set);
  254. }
  255. static int pic32_eth_start(struct udevice *dev)
  256. {
  257. struct eth_pdata *pdata = dev_get_platdata(dev);
  258. struct pic32eth_dev *priv = dev_get_priv(dev);
  259. /* controller */
  260. pic32_ctrl_reset(priv);
  261. /* reset MAC */
  262. pic32_mac_reset(priv);
  263. /* configure PHY */
  264. phy_config(priv->phydev);
  265. /* initialize MAC */
  266. pic32_mac_init(priv, &pdata->enetaddr[0]);
  267. /* init RX descriptor; TX descriptors are handled in xmit */
  268. pic32_rx_desc_init(priv);
  269. /* Start up & update link status of PHY */
  270. phy_startup(priv->phydev);
  271. /* adjust mac with phy link status */
  272. return pic32_mac_adjust_link(priv);
  273. }
  274. static void pic32_eth_stop(struct udevice *dev)
  275. {
  276. struct pic32eth_dev *priv = dev_get_priv(dev);
  277. struct pic32_ectl_regs *ectl_p = priv->ectl_regs;
  278. struct pic32_emac_regs *emac_p = priv->emac_regs;
  279. /* Reset the phy if the controller is enabled */
  280. if (readl(&ectl_p->con1.raw) & ETHCON_ON)
  281. phy_reset(priv->phydev);
  282. /* Shut down the PHY */
  283. phy_shutdown(priv->phydev);
  284. /* Stop rx/tx */
  285. writel(ETHCON_TXRTS | ETHCON_RXEN, &ectl_p->con1.clr);
  286. mdelay(10);
  287. /* reset MAC */
  288. writel(EMAC_SOFTRESET, &emac_p->cfg1.raw);
  289. /* clear reset */
  290. writel(0, &emac_p->cfg1.raw);
  291. mdelay(10);
  292. /* disable controller */
  293. writel(ETHCON_ON, &ectl_p->con1.clr);
  294. mdelay(10);
  295. /* wait until everything is down */
  296. wait_for_bit_le32(&ectl_p->stat.raw, ETHSTAT_BUSY, false,
  297. 2 * CONFIG_SYS_HZ, false);
  298. /* clear any existing interrupt event */
  299. writel(0xffffffff, &ectl_p->irq.clr);
  300. }
  301. static int pic32_eth_send(struct udevice *dev, void *packet, int length)
  302. {
  303. struct pic32eth_dev *priv = dev_get_priv(dev);
  304. struct pic32_ectl_regs *ectl_p = priv->ectl_regs;
  305. struct eth_dma_desc *txd;
  306. u64 deadline;
  307. txd = &priv->txd_ring[0];
  308. /* set proper flags & length in descriptor header */
  309. txd->hdr = EDH_SOP | EDH_EOP | EDH_EOWN | EDH_BCOUNT(length);
  310. /* pass buffer address to hardware */
  311. txd->data_buff = virt_to_phys(packet);
  312. debug("%s: %d / .hdr %x, .data_buff %x, .stat %x, .nexted %x\n",
  313. __func__, __LINE__, txd->hdr, txd->data_buff, txd->stat2,
  314. txd->next_ed);
  315. /* cache flush (packet) */
  316. flush_dcache_range((ulong)packet, (ulong)packet + length);
  317. /* cache flush (txd) */
  318. flush_dcache_range((ulong)txd, (ulong)txd + sizeof(*txd));
  319. /* pass descriptor table base to h/w */
  320. writel(virt_to_phys(txd), &ectl_p->txst.raw);
  321. /* ready to send enabled, hardware can now send the packet(s) */
  322. writel(ETHCON_TXRTS | ETHCON_ON, &ectl_p->con1.set);
  323. /* wait until tx has completed and h/w has released ownership
  324. * of the tx descriptor or timeout elapsed.
  325. */
  326. deadline = get_ticks() + get_tbclk();
  327. for (;;) {
  328. /* check timeout */
  329. if (get_ticks() > deadline)
  330. return -ETIMEDOUT;
  331. if (ctrlc())
  332. return -EINTR;
  333. /* tx completed ? */
  334. if (readl(&ectl_p->con1.raw) & ETHCON_TXRTS) {
  335. udelay(1);
  336. continue;
  337. }
  338. /* h/w not released ownership yet? */
  339. invalidate_dcache_range((ulong)txd, (ulong)txd + sizeof(*txd));
  340. if (!(txd->hdr & EDH_EOWN))
  341. break;
  342. }
  343. return 0;
  344. }
  345. static int pic32_eth_recv(struct udevice *dev, int flags, uchar **packetp)
  346. {
  347. struct pic32eth_dev *priv = dev_get_priv(dev);
  348. struct eth_dma_desc *rxd;
  349. u32 idx = priv->rxd_idx;
  350. u32 rx_count;
  351. /* find the next ready to receive */
  352. rxd = &priv->rxd_ring[idx];
  353. invalidate_dcache_range((ulong)rxd, (ulong)rxd + sizeof(*rxd));
  354. /* check if owned by MAC */
  355. if (rxd->hdr & EDH_EOWN)
  356. return -EAGAIN;
  357. /* Sanity check on header: SOP and EOP */
  358. if ((rxd->hdr & (EDH_SOP | EDH_EOP)) != (EDH_SOP | EDH_EOP)) {
  359. printf("%s: %s, rx pkt across multiple descr\n",
  360. __FILE__, __func__);
  361. return 0;
  362. }
  363. debug("%s: %d /idx %i, hdr=%x, data_buff %x, stat %x, nexted %x\n",
  364. __func__, __LINE__, idx, rxd->hdr,
  365. rxd->data_buff, rxd->stat2, rxd->next_ed);
  366. /* Sanity check on rx_stat: OK, CRC */
  367. if (!RSV_RX_OK(rxd->stat2) || RSV_CRC_ERR(rxd->stat2)) {
  368. debug("%s: %s: Error, rx problem detected\n",
  369. __FILE__, __func__);
  370. return 0;
  371. }
  372. /* invalidate dcache */
  373. rx_count = RSV_RX_COUNT(rxd->stat2);
  374. invalidate_dcache_range((ulong)net_rx_packets[idx],
  375. (ulong)net_rx_packets[idx] + rx_count);
  376. /* Pass the packet to protocol layer */
  377. *packetp = net_rx_packets[idx];
  378. /* increment number of bytes rcvd (ignore CRC) */
  379. return rx_count - 4;
  380. }
  381. static int pic32_eth_free_pkt(struct udevice *dev, uchar *packet, int length)
  382. {
  383. struct pic32eth_dev *priv = dev_get_priv(dev);
  384. struct pic32_ectl_regs *ectl_p = priv->ectl_regs;
  385. struct eth_dma_desc *rxd;
  386. int idx = priv->rxd_idx;
  387. /* sanity check */
  388. if (packet != net_rx_packets[idx]) {
  389. printf("rxd_id %d: packet is not matched,\n", idx);
  390. return -EAGAIN;
  391. }
  392. /* prepare for receive */
  393. rxd = &priv->rxd_ring[idx];
  394. rxd->hdr = EDH_STICKY | EDH_NPV | EDH_EOWN;
  395. flush_dcache_range((ulong)rxd, (ulong)rxd + sizeof(*rxd));
  396. /* decrement rx pkt count */
  397. writel(ETHCON_BUFCDEC, &ectl_p->con1.set);
  398. debug("%s: %d / idx %i, hdr %x, data_buff %x, stat %x, nexted %x\n",
  399. __func__, __LINE__, idx, rxd->hdr, rxd->data_buff,
  400. rxd->stat2, rxd->next_ed);
  401. priv->rxd_idx = (priv->rxd_idx + 1) % MAX_RX_DESCR;
  402. return 0;
  403. }
  404. static const struct eth_ops pic32_eth_ops = {
  405. .start = pic32_eth_start,
  406. .send = pic32_eth_send,
  407. .recv = pic32_eth_recv,
  408. .free_pkt = pic32_eth_free_pkt,
  409. .stop = pic32_eth_stop,
  410. };
  411. static int pic32_eth_probe(struct udevice *dev)
  412. {
  413. struct eth_pdata *pdata = dev_get_platdata(dev);
  414. struct pic32eth_dev *priv = dev_get_priv(dev);
  415. const char *phy_mode;
  416. void __iomem *iobase;
  417. fdt_addr_t addr;
  418. fdt_size_t size;
  419. int offset = 0;
  420. int phy_addr = -1;
  421. addr = fdtdec_get_addr_size(gd->fdt_blob, dev_of_offset(dev), "reg",
  422. &size);
  423. if (addr == FDT_ADDR_T_NONE)
  424. return -EINVAL;
  425. iobase = ioremap(addr, size);
  426. pdata->iobase = (phys_addr_t)addr;
  427. /* get phy mode */
  428. pdata->phy_interface = -1;
  429. phy_mode = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), "phy-mode",
  430. NULL);
  431. if (phy_mode)
  432. pdata->phy_interface = phy_get_interface_by_name(phy_mode);
  433. if (pdata->phy_interface == -1) {
  434. debug("%s: Invalid PHY interface '%s'\n", __func__, phy_mode);
  435. return -EINVAL;
  436. }
  437. /* get phy addr */
  438. offset = fdtdec_lookup_phandle(gd->fdt_blob, dev_of_offset(dev),
  439. "phy-handle");
  440. if (offset > 0)
  441. phy_addr = fdtdec_get_int(gd->fdt_blob, offset, "reg", -1);
  442. /* phy reset gpio */
  443. gpio_request_by_name_nodev(dev_ofnode(dev), "reset-gpios", 0,
  444. &priv->rst_gpio, GPIOD_IS_OUT);
  445. priv->phyif = pdata->phy_interface;
  446. priv->phy_addr = phy_addr;
  447. priv->ectl_regs = iobase;
  448. priv->emac_regs = iobase + PIC32_EMAC1CFG1;
  449. pic32_mii_init(priv);
  450. return pic32_phy_init(priv, dev);
  451. }
  452. static int pic32_eth_remove(struct udevice *dev)
  453. {
  454. struct pic32eth_dev *priv = dev_get_priv(dev);
  455. struct mii_dev *bus;
  456. dm_gpio_free(dev, &priv->rst_gpio);
  457. phy_shutdown(priv->phydev);
  458. free(priv->phydev);
  459. bus = miiphy_get_dev_by_name(PIC32_MDIO_NAME);
  460. mdio_unregister(bus);
  461. mdio_free(bus);
  462. iounmap(priv->ectl_regs);
  463. return 0;
  464. }
  465. static const struct udevice_id pic32_eth_ids[] = {
  466. { .compatible = "microchip,pic32mzda-eth" },
  467. { }
  468. };
  469. U_BOOT_DRIVER(pic32_ethernet) = {
  470. .name = "pic32_ethernet",
  471. .id = UCLASS_ETH,
  472. .of_match = pic32_eth_ids,
  473. .probe = pic32_eth_probe,
  474. .remove = pic32_eth_remove,
  475. .ops = &pic32_eth_ops,
  476. .priv_auto_alloc_size = sizeof(struct pic32eth_dev),
  477. .platdata_auto_alloc_size = sizeof(struct eth_pdata),
  478. };