board.c 4.5 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2014 - 2018 Xilinx, Inc.
  4. * Michal Simek <michal.simek@xilinx.com>
  5. */
  6. #include <common.h>
  7. #include <fdtdec.h>
  8. #include <malloc.h>
  9. #include <time.h>
  10. #include <asm/io.h>
  11. #include <asm/arch/hardware.h>
  12. #include <asm/arch/sys_proto.h>
  13. #include <dm/device.h>
  14. #include <dm/uclass.h>
  15. #include <versalpl.h>
  16. #include <linux/sizes.h>
  17. DECLARE_GLOBAL_DATA_PTR;
  18. #if defined(CONFIG_FPGA_VERSALPL)
  19. static xilinx_desc versalpl = XILINX_VERSAL_DESC;
  20. #endif
  21. int board_init(void)
  22. {
  23. printf("EL Level:\tEL%d\n", current_el());
  24. #if defined(CONFIG_FPGA_VERSALPL)
  25. fpga_init();
  26. fpga_add(fpga_xilinx, &versalpl);
  27. #endif
  28. return 0;
  29. }
  30. int board_early_init_r(void)
  31. {
  32. u32 val;
  33. if (current_el() != 3)
  34. return 0;
  35. debug("iou_switch ctrl div0 %x\n",
  36. readl(&crlapb_base->iou_switch_ctrl));
  37. writel(IOU_SWITCH_CTRL_CLKACT_BIT |
  38. (CONFIG_IOU_SWITCH_DIVISOR0 << IOU_SWITCH_CTRL_DIVISOR0_SHIFT),
  39. &crlapb_base->iou_switch_ctrl);
  40. /* Global timer init - Program time stamp reference clk */
  41. val = readl(&crlapb_base->timestamp_ref_ctrl);
  42. val |= CRL_APB_TIMESTAMP_REF_CTRL_CLKACT_BIT;
  43. writel(val, &crlapb_base->timestamp_ref_ctrl);
  44. debug("ref ctrl 0x%x\n",
  45. readl(&crlapb_base->timestamp_ref_ctrl));
  46. /* Clear reset of timestamp reg */
  47. writel(0, &crlapb_base->rst_timestamp);
  48. /*
  49. * Program freq register in System counter and
  50. * enable system counter.
  51. */
  52. writel(COUNTER_FREQUENCY,
  53. &iou_scntr_secure->base_frequency_id_register);
  54. debug("counter val 0x%x\n",
  55. readl(&iou_scntr_secure->base_frequency_id_register));
  56. writel(IOU_SCNTRS_CONTROL_EN,
  57. &iou_scntr_secure->counter_control_register);
  58. debug("scntrs control 0x%x\n",
  59. readl(&iou_scntr_secure->counter_control_register));
  60. debug("timer 0x%llx\n", get_ticks());
  61. debug("timer 0x%llx\n", get_ticks());
  62. return 0;
  63. }
  64. int board_late_init(void)
  65. {
  66. u32 reg = 0;
  67. u8 bootmode;
  68. struct udevice *dev;
  69. int bootseq = -1;
  70. int bootseq_len = 0;
  71. int env_targets_len = 0;
  72. const char *mode;
  73. char *new_targets;
  74. char *env_targets;
  75. ulong initrd_hi;
  76. if (!(gd->flags & GD_FLG_ENV_DEFAULT)) {
  77. debug("Saved variables - Skipping\n");
  78. return 0;
  79. }
  80. reg = readl(&crp_base->boot_mode_usr);
  81. if (reg >> BOOT_MODE_ALT_SHIFT)
  82. reg >>= BOOT_MODE_ALT_SHIFT;
  83. bootmode = reg & BOOT_MODES_MASK;
  84. puts("Bootmode: ");
  85. switch (bootmode) {
  86. case USB_MODE:
  87. puts("USB_MODE\n");
  88. mode = "dfu_usb";
  89. break;
  90. case JTAG_MODE:
  91. puts("JTAG_MODE\n");
  92. mode = "jtag pxe dhcp";
  93. break;
  94. case QSPI_MODE_24BIT:
  95. puts("QSPI_MODE_24\n");
  96. mode = "xspi0";
  97. break;
  98. case QSPI_MODE_32BIT:
  99. puts("QSPI_MODE_32\n");
  100. mode = "xspi0";
  101. break;
  102. case OSPI_MODE:
  103. puts("OSPI_MODE\n");
  104. mode = "xspi0";
  105. break;
  106. case EMMC_MODE:
  107. puts("EMMC_MODE\n");
  108. mode = "mmc0";
  109. break;
  110. case SD_MODE:
  111. puts("SD_MODE\n");
  112. if (uclass_get_device_by_name(UCLASS_MMC,
  113. "sdhci@f1040000", &dev)) {
  114. puts("Boot from SD0 but without SD0 enabled!\n");
  115. return -1;
  116. }
  117. debug("mmc0 device found at %p, seq %d\n", dev, dev->seq);
  118. mode = "mmc";
  119. bootseq = dev->seq;
  120. break;
  121. case SD1_LSHFT_MODE:
  122. puts("LVL_SHFT_");
  123. /* fall through */
  124. case SD_MODE1:
  125. puts("SD_MODE1\n");
  126. if (uclass_get_device_by_name(UCLASS_MMC,
  127. "sdhci@f1050000", &dev)) {
  128. puts("Boot from SD1 but without SD1 enabled!\n");
  129. return -1;
  130. }
  131. debug("mmc1 device found at %p, seq %d\n", dev, dev->seq);
  132. mode = "mmc";
  133. bootseq = dev->seq;
  134. break;
  135. default:
  136. mode = "";
  137. printf("Invalid Boot Mode:0x%x\n", bootmode);
  138. break;
  139. }
  140. if (bootseq >= 0) {
  141. bootseq_len = snprintf(NULL, 0, "%i", bootseq);
  142. debug("Bootseq len: %x\n", bootseq_len);
  143. }
  144. /*
  145. * One terminating char + one byte for space between mode
  146. * and default boot_targets
  147. */
  148. env_targets = env_get("boot_targets");
  149. if (env_targets)
  150. env_targets_len = strlen(env_targets);
  151. new_targets = calloc(1, strlen(mode) + env_targets_len + 2 +
  152. bootseq_len);
  153. if (!new_targets)
  154. return -ENOMEM;
  155. if (bootseq >= 0)
  156. sprintf(new_targets, "%s%x %s", mode, bootseq,
  157. env_targets ? env_targets : "");
  158. else
  159. sprintf(new_targets, "%s %s", mode,
  160. env_targets ? env_targets : "");
  161. env_set("boot_targets", new_targets);
  162. initrd_hi = gd->start_addr_sp - CONFIG_STACK_SIZE;
  163. initrd_hi = round_down(initrd_hi, SZ_16M);
  164. env_set_addr("initrd_high", (void *)initrd_hi);
  165. return 0;
  166. }
  167. int dram_init_banksize(void)
  168. {
  169. int ret;
  170. ret = fdtdec_setup_memory_banksize();
  171. if (ret)
  172. return ret;
  173. mem_map_fill();
  174. return 0;
  175. }
  176. int dram_init(void)
  177. {
  178. if (fdtdec_setup_mem_size_base() != 0)
  179. return -EINVAL;
  180. return 0;
  181. }
  182. void reset_cpu(ulong addr)
  183. {
  184. }