timer.c 6.6 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * JZ4780 timer
  4. *
  5. * Copyright (c) 2013 Imagination Technologies
  6. * Author: Paul Burton <paul.burton@imgtec.com>
  7. */
  8. #include <config.h>
  9. #include <common.h>
  10. #include <div64.h>
  11. #include <time.h>
  12. #include <asm/io.h>
  13. #include <asm/mipsregs.h>
  14. #include <mach/jz4780.h>
  15. #define TCU_TSR 0x1C /* Timer Stop Register */
  16. #define TCU_TSSR 0x2C /* Timer Stop Set Register */
  17. #define TCU_TSCR 0x3C /* Timer Stop Clear Register */
  18. #define TCU_TER 0x10 /* Timer Counter Enable Register */
  19. #define TCU_TESR 0x14 /* Timer Counter Enable Set Register */
  20. #define TCU_TECR 0x18 /* Timer Counter Enable Clear Register */
  21. #define TCU_TFR 0x20 /* Timer Flag Register */
  22. #define TCU_TFSR 0x24 /* Timer Flag Set Register */
  23. #define TCU_TFCR 0x28 /* Timer Flag Clear Register */
  24. #define TCU_TMR 0x30 /* Timer Mask Register */
  25. #define TCU_TMSR 0x34 /* Timer Mask Set Register */
  26. #define TCU_TMCR 0x38 /* Timer Mask Clear Register */
  27. /* n = 0,1,2,3,4,5 */
  28. #define TCU_TDFR(n) (0x40 + (n) * 0x10) /* Timer Data Full Reg */
  29. #define TCU_TDHR(n) (0x44 + (n) * 0x10) /* Timer Data Half Reg */
  30. #define TCU_TCNT(n) (0x48 + (n) * 0x10) /* Timer Counter Reg */
  31. #define TCU_TCSR(n) (0x4C + (n) * 0x10) /* Timer Control Reg */
  32. #define TCU_OSTCNTL 0xe4
  33. #define TCU_OSTCNTH 0xe8
  34. #define TCU_OSTCSR 0xec
  35. #define TCU_OSTCNTHBUF 0xfc
  36. /* Register definitions */
  37. #define TCU_TCSR_PWM_SD BIT(9)
  38. #define TCU_TCSR_PWM_INITL_HIGH BIT(8)
  39. #define TCU_TCSR_PWM_EN BIT(7)
  40. #define TCU_TCSR_PRESCALE_BIT 3
  41. #define TCU_TCSR_PRESCALE_MASK (0x7 << TCU_TCSR_PRESCALE_BIT)
  42. #define TCU_TCSR_PRESCALE1 (0x0 << TCU_TCSR_PRESCALE_BIT)
  43. #define TCU_TCSR_PRESCALE4 (0x1 << TCU_TCSR_PRESCALE_BIT)
  44. #define TCU_TCSR_PRESCALE16 (0x2 << TCU_TCSR_PRESCALE_BIT)
  45. #define TCU_TCSR_PRESCALE64 (0x3 << TCU_TCSR_PRESCALE_BIT)
  46. #define TCU_TCSR_PRESCALE256 (0x4 << TCU_TCSR_PRESCALE_BIT)
  47. #define TCU_TCSR_PRESCALE1024 (0x5 << TCU_TCSR_PRESCALE_BIT)
  48. #define TCU_TCSR_EXT_EN BIT(2)
  49. #define TCU_TCSR_RTC_EN BIT(1)
  50. #define TCU_TCSR_PCK_EN BIT(0)
  51. #define TCU_TER_TCEN5 BIT(5)
  52. #define TCU_TER_TCEN4 BIT(4)
  53. #define TCU_TER_TCEN3 BIT(3)
  54. #define TCU_TER_TCEN2 BIT(2)
  55. #define TCU_TER_TCEN1 BIT(1)
  56. #define TCU_TER_TCEN0 BIT(0)
  57. #define TCU_TESR_TCST5 BIT(5)
  58. #define TCU_TESR_TCST4 BIT(4)
  59. #define TCU_TESR_TCST3 BIT(3)
  60. #define TCU_TESR_TCST2 BIT(2)
  61. #define TCU_TESR_TCST1 BIT(1)
  62. #define TCU_TESR_TCST0 BIT(0)
  63. #define TCU_TECR_TCCL5 BIT(5)
  64. #define TCU_TECR_TCCL4 BIT(4)
  65. #define TCU_TECR_TCCL3 BIT(3)
  66. #define TCU_TECR_TCCL2 BIT(2)
  67. #define TCU_TECR_TCCL1 BIT(1)
  68. #define TCU_TECR_TCCL0 BIT(0)
  69. #define TCU_TFR_HFLAG5 BIT(21)
  70. #define TCU_TFR_HFLAG4 BIT(20)
  71. #define TCU_TFR_HFLAG3 BIT(19)
  72. #define TCU_TFR_HFLAG2 BIT(18)
  73. #define TCU_TFR_HFLAG1 BIT(17)
  74. #define TCU_TFR_HFLAG0 BIT(16)
  75. #define TCU_TFR_FFLAG5 BIT(5)
  76. #define TCU_TFR_FFLAG4 BIT(4)
  77. #define TCU_TFR_FFLAG3 BIT(3)
  78. #define TCU_TFR_FFLAG2 BIT(2)
  79. #define TCU_TFR_FFLAG1 BIT(1)
  80. #define TCU_TFR_FFLAG0 BIT(0)
  81. #define TCU_TFSR_HFLAG5 BIT(21)
  82. #define TCU_TFSR_HFLAG4 BIT(20)
  83. #define TCU_TFSR_HFLAG3 BIT(19)
  84. #define TCU_TFSR_HFLAG2 BIT(18)
  85. #define TCU_TFSR_HFLAG1 BIT(17)
  86. #define TCU_TFSR_HFLAG0 BIT(16)
  87. #define TCU_TFSR_FFLAG5 BIT(5)
  88. #define TCU_TFSR_FFLAG4 BIT(4)
  89. #define TCU_TFSR_FFLAG3 BIT(3)
  90. #define TCU_TFSR_FFLAG2 BIT(2)
  91. #define TCU_TFSR_FFLAG1 BIT(1)
  92. #define TCU_TFSR_FFLAG0 BIT(0)
  93. #define TCU_TFCR_HFLAG5 BIT(21)
  94. #define TCU_TFCR_HFLAG4 BIT(20)
  95. #define TCU_TFCR_HFLAG3 BIT(19)
  96. #define TCU_TFCR_HFLAG2 BIT(18)
  97. #define TCU_TFCR_HFLAG1 BIT(17)
  98. #define TCU_TFCR_HFLAG0 BIT(16)
  99. #define TCU_TFCR_FFLAG5 BIT(5)
  100. #define TCU_TFCR_FFLAG4 BIT(4)
  101. #define TCU_TFCR_FFLAG3 BIT(3)
  102. #define TCU_TFCR_FFLAG2 BIT(2)
  103. #define TCU_TFCR_FFLAG1 BIT(1)
  104. #define TCU_TFCR_FFLAG0 BIT(0)
  105. #define TCU_TMR_HMASK5 BIT(21)
  106. #define TCU_TMR_HMASK4 BIT(20)
  107. #define TCU_TMR_HMASK3 BIT(19)
  108. #define TCU_TMR_HMASK2 BIT(18)
  109. #define TCU_TMR_HMASK1 BIT(17)
  110. #define TCU_TMR_HMASK0 BIT(16)
  111. #define TCU_TMR_FMASK5 BIT(5)
  112. #define TCU_TMR_FMASK4 BIT(4)
  113. #define TCU_TMR_FMASK3 BIT(3)
  114. #define TCU_TMR_FMASK2 BIT(2)
  115. #define TCU_TMR_FMASK1 BIT(1)
  116. #define TCU_TMR_FMASK0 BIT(0)
  117. #define TCU_TMSR_HMST5 BIT(21)
  118. #define TCU_TMSR_HMST4 BIT(20)
  119. #define TCU_TMSR_HMST3 BIT(19)
  120. #define TCU_TMSR_HMST2 BIT(18)
  121. #define TCU_TMSR_HMST1 BIT(17)
  122. #define TCU_TMSR_HMST0 BIT(16)
  123. #define TCU_TMSR_FMST5 BIT(5)
  124. #define TCU_TMSR_FMST4 BIT(4)
  125. #define TCU_TMSR_FMST3 BIT(3)
  126. #define TCU_TMSR_FMST2 BIT(2)
  127. #define TCU_TMSR_FMST1 BIT(1)
  128. #define TCU_TMSR_FMST0 BIT(0)
  129. #define TCU_TMCR_HMCL5 BIT(21)
  130. #define TCU_TMCR_HMCL4 BIT(20)
  131. #define TCU_TMCR_HMCL3 BIT(19)
  132. #define TCU_TMCR_HMCL2 BIT(18)
  133. #define TCU_TMCR_HMCL1 BIT(17)
  134. #define TCU_TMCR_HMCL0 BIT(16)
  135. #define TCU_TMCR_FMCL5 BIT(5)
  136. #define TCU_TMCR_FMCL4 BIT(4)
  137. #define TCU_TMCR_FMCL3 BIT(3)
  138. #define TCU_TMCR_FMCL2 BIT(2)
  139. #define TCU_TMCR_FMCL1 BIT(1)
  140. #define TCU_TMCR_FMCL0 BIT(0)
  141. #define TCU_TSR_WDTS BIT(16)
  142. #define TCU_TSR_STOP5 BIT(5)
  143. #define TCU_TSR_STOP4 BIT(4)
  144. #define TCU_TSR_STOP3 BIT(3)
  145. #define TCU_TSR_STOP2 BIT(2)
  146. #define TCU_TSR_STOP1 BIT(1)
  147. #define TCU_TSR_STOP0 BIT(0)
  148. #define TCU_TSSR_WDTSS BIT(16)
  149. #define TCU_TSSR_STPS5 BIT(5)
  150. #define TCU_TSSR_STPS4 BIT(4)
  151. #define TCU_TSSR_STPS3 BIT(3)
  152. #define TCU_TSSR_STPS2 BIT(2)
  153. #define TCU_TSSR_STPS1 BIT(1)
  154. #define TCU_TSSR_STPS0 BIT(0)
  155. #define TCU_TSSR_WDTSC BIT(16)
  156. #define TCU_TSSR_STPC5 BIT(5)
  157. #define TCU_TSSR_STPC4 BIT(4)
  158. #define TCU_TSSR_STPC3 BIT(3)
  159. #define TCU_TSSR_STPC2 BIT(2)
  160. #define TCU_TSSR_STPC1 BIT(1)
  161. #define TCU_TSSR_STPC0 BIT(0)
  162. #define TER_OSTEN BIT(15)
  163. #define OSTCSR_CNT_MD BIT(15)
  164. #define OSTCSR_SD BIT(9)
  165. #define OSTCSR_PRESCALE_16 (0x2 << 3)
  166. #define OSTCSR_EXT_EN BIT(2)
  167. int timer_init(void)
  168. {
  169. void __iomem *regs = (void __iomem *)TCU_BASE;
  170. writel(OSTCSR_SD, regs + TCU_OSTCSR);
  171. reset_timer();
  172. writel(OSTCSR_CNT_MD | OSTCSR_EXT_EN | OSTCSR_PRESCALE_16,
  173. regs + TCU_OSTCSR);
  174. writew(TER_OSTEN, regs + TCU_TESR);
  175. return 0;
  176. }
  177. void reset_timer(void)
  178. {
  179. void __iomem *regs = (void __iomem *)TCU_BASE;
  180. writel(0, regs + TCU_OSTCNTH);
  181. writel(0, regs + TCU_OSTCNTL);
  182. }
  183. static u64 get_timer64(void)
  184. {
  185. void __iomem *regs = (void __iomem *)TCU_BASE;
  186. u32 low = readl(regs + TCU_OSTCNTL);
  187. u32 high = readl(regs + TCU_OSTCNTHBUF);
  188. return ((u64)high << 32) | low;
  189. }
  190. ulong get_timer(ulong base)
  191. {
  192. return lldiv(get_timer64(), 3000) - base;
  193. }
  194. void __udelay(unsigned long usec)
  195. {
  196. /* OST count increments at 3MHz */
  197. u64 end = get_timer64() + ((u64)usec * 3);
  198. while (get_timer64() < end)
  199. ;
  200. }
  201. unsigned long long get_ticks(void)
  202. {
  203. return get_timer64();
  204. }
  205. void jz4780_tcu_wdt_start(void)
  206. {
  207. void __iomem *tcu_regs = (void __iomem *)TCU_BASE;
  208. /* Enable WDT clock */
  209. writel(TCU_TSSR_WDTSC, tcu_regs + TCU_TSCR);
  210. }