rsb.c 3.9 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2014 Hans de Goede <hdegoede@redhat.com>
  4. *
  5. * Based on allwinner u-boot sources rsb code which is:
  6. * (C) Copyright 2007-2013
  7. * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
  8. * lixiang <lixiang@allwinnertech.com>
  9. */
  10. #include <common.h>
  11. #include <errno.h>
  12. #include <time.h>
  13. #include <asm/arch/cpu.h>
  14. #include <asm/arch/gpio.h>
  15. #include <asm/arch/prcm.h>
  16. #include <asm/arch/rsb.h>
  17. static int rsb_set_device_mode(void);
  18. static void rsb_cfg_io(void)
  19. {
  20. #ifdef CONFIG_MACH_SUN8I
  21. sunxi_gpio_set_cfgpin(SUNXI_GPL(0), SUN8I_GPL_R_RSB);
  22. sunxi_gpio_set_cfgpin(SUNXI_GPL(1), SUN8I_GPL_R_RSB);
  23. sunxi_gpio_set_pull(SUNXI_GPL(0), 1);
  24. sunxi_gpio_set_pull(SUNXI_GPL(1), 1);
  25. sunxi_gpio_set_drv(SUNXI_GPL(0), 2);
  26. sunxi_gpio_set_drv(SUNXI_GPL(1), 2);
  27. #elif defined CONFIG_MACH_SUN9I
  28. sunxi_gpio_set_cfgpin(SUNXI_GPN(0), SUN9I_GPN_R_RSB);
  29. sunxi_gpio_set_cfgpin(SUNXI_GPN(1), SUN9I_GPN_R_RSB);
  30. sunxi_gpio_set_pull(SUNXI_GPN(0), 1);
  31. sunxi_gpio_set_pull(SUNXI_GPN(1), 1);
  32. sunxi_gpio_set_drv(SUNXI_GPN(0), 2);
  33. sunxi_gpio_set_drv(SUNXI_GPN(1), 2);
  34. #else
  35. #error unsupported MACH_SUNXI
  36. #endif
  37. }
  38. static void rsb_set_clk(void)
  39. {
  40. struct sunxi_rsb_reg * const rsb =
  41. (struct sunxi_rsb_reg *)SUNXI_RSB_BASE;
  42. u32 div = 0;
  43. u32 cd_odly = 0;
  44. /* Source is Hosc24M, set RSB clk to 3Mhz */
  45. div = 24000000 / 3000000 / 2 - 1;
  46. cd_odly = div >> 1;
  47. if (!cd_odly)
  48. cd_odly = 1;
  49. writel((cd_odly << 8) | div, &rsb->ccr);
  50. }
  51. int rsb_init(void)
  52. {
  53. struct sunxi_rsb_reg * const rsb =
  54. (struct sunxi_rsb_reg *)SUNXI_RSB_BASE;
  55. /* Enable RSB and PIO clk, and de-assert their resets */
  56. prcm_apb0_enable(PRCM_APB0_GATE_PIO | PRCM_APB0_GATE_RSB);
  57. /* Setup external pins */
  58. rsb_cfg_io();
  59. writel(RSB_CTRL_SOFT_RST, &rsb->ctrl);
  60. rsb_set_clk();
  61. return rsb_set_device_mode();
  62. }
  63. static int rsb_await_trans(void)
  64. {
  65. struct sunxi_rsb_reg * const rsb =
  66. (struct sunxi_rsb_reg *)SUNXI_RSB_BASE;
  67. unsigned long tmo = timer_get_us() + 1000000;
  68. u32 stat;
  69. int ret;
  70. while (1) {
  71. stat = readl(&rsb->stat);
  72. if (stat & RSB_STAT_LBSY_INT) {
  73. ret = -EBUSY;
  74. break;
  75. }
  76. if (stat & RSB_STAT_TERR_INT) {
  77. ret = -EIO;
  78. break;
  79. }
  80. if (stat & RSB_STAT_TOVER_INT) {
  81. ret = 0;
  82. break;
  83. }
  84. if (timer_get_us() > tmo) {
  85. ret = -ETIME;
  86. break;
  87. }
  88. }
  89. writel(stat, &rsb->stat); /* Clear status bits */
  90. return ret;
  91. }
  92. static int rsb_set_device_mode(void)
  93. {
  94. struct sunxi_rsb_reg * const rsb =
  95. (struct sunxi_rsb_reg *)SUNXI_RSB_BASE;
  96. unsigned long tmo = timer_get_us() + 1000000;
  97. writel(RSB_DMCR_DEVICE_MODE_START | RSB_DMCR_DEVICE_MODE_DATA,
  98. &rsb->dmcr);
  99. while (readl(&rsb->dmcr) & RSB_DMCR_DEVICE_MODE_START) {
  100. if (timer_get_us() > tmo)
  101. return -ETIME;
  102. }
  103. return rsb_await_trans();
  104. }
  105. static int rsb_do_trans(void)
  106. {
  107. struct sunxi_rsb_reg * const rsb =
  108. (struct sunxi_rsb_reg *)SUNXI_RSB_BASE;
  109. setbits_le32(&rsb->ctrl, RSB_CTRL_START_TRANS);
  110. return rsb_await_trans();
  111. }
  112. int rsb_set_device_address(u16 device_addr, u16 runtime_addr)
  113. {
  114. struct sunxi_rsb_reg * const rsb =
  115. (struct sunxi_rsb_reg *)SUNXI_RSB_BASE;
  116. writel(RSB_DEVADDR_RUNTIME_ADDR(runtime_addr) |
  117. RSB_DEVADDR_DEVICE_ADDR(device_addr), &rsb->devaddr);
  118. writel(RSB_CMD_SET_RTSADDR, &rsb->cmd);
  119. return rsb_do_trans();
  120. }
  121. int rsb_write(const u16 runtime_device_addr, const u8 reg_addr, u8 data)
  122. {
  123. struct sunxi_rsb_reg * const rsb =
  124. (struct sunxi_rsb_reg *)SUNXI_RSB_BASE;
  125. writel(RSB_DEVADDR_RUNTIME_ADDR(runtime_device_addr), &rsb->devaddr);
  126. writel(reg_addr, &rsb->addr);
  127. writel(data, &rsb->data);
  128. writel(RSB_CMD_BYTE_WRITE, &rsb->cmd);
  129. return rsb_do_trans();
  130. }
  131. int rsb_read(const u16 runtime_device_addr, const u8 reg_addr, u8 *data)
  132. {
  133. struct sunxi_rsb_reg * const rsb =
  134. (struct sunxi_rsb_reg *)SUNXI_RSB_BASE;
  135. int ret;
  136. writel(RSB_DEVADDR_RUNTIME_ADDR(runtime_device_addr), &rsb->devaddr);
  137. writel(reg_addr, &rsb->addr);
  138. writel(RSB_CMD_BYTE_READ, &rsb->cmd);
  139. ret = rsb_do_trans();
  140. if (ret)
  141. return ret;
  142. *data = readl(&rsb->data) & 0xff;
  143. return 0;
  144. }