imx-regs.h 16 KB

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  1. /*
  2. * (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
  3. * (c) 2009 Ilya Yanok, Emcraft Systems <yanok@emcraft.com>
  4. *
  5. * See file CREDITS for list of people who contributed to this
  6. * project.
  7. *
  8. * This program is free software; you can redistribute it and/or
  9. * modify it under the terms of the GNU General Public License as
  10. * published by the Free Software Foundation; either version 2 of
  11. * the License, or (at your option) any later version.
  12. *
  13. * This program is distributed in the hope that it will be useful,
  14. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16. * GNU General Public License for more details.
  17. *
  18. * You should have received a copy of the GNU General Public License
  19. * along with this program; if not, write to the Free Software
  20. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21. * MA 02111-1307 USA
  22. */
  23. #ifndef _IMX_REGS_H
  24. #define _IMX_REGS_H
  25. #include <asm/arch/regs-rtc.h>
  26. #ifndef __ASSEMBLY__
  27. extern void imx_gpio_mode (int gpio_mode);
  28. #ifdef CONFIG_MXC_UART
  29. extern void mx27_uart1_init_pins(void);
  30. #endif /* CONFIG_MXC_UART */
  31. #ifdef CONFIG_FEC_MXC
  32. extern void mx27_fec_init_pins(void);
  33. #endif /* CONFIG_FEC_MXC */
  34. #ifdef CONFIG_MXC_MMC
  35. extern void mx27_sd1_init_pins(void);
  36. extern void mx27_sd2_init_pins(void);
  37. #endif /* CONFIG_MXC_MMC */
  38. /* AIPI */
  39. struct aipi_regs {
  40. u32 psr0;
  41. u32 psr1;
  42. };
  43. /* System Control */
  44. struct system_control_regs {
  45. u32 res[5];
  46. u32 fmcr;
  47. u32 gpcr;
  48. u32 wbcr;
  49. u32 dscr1;
  50. u32 dscr2;
  51. u32 dscr3;
  52. u32 dscr4;
  53. u32 dscr5;
  54. u32 dscr6;
  55. u32 dscr7;
  56. u32 dscr8;
  57. u32 dscr9;
  58. u32 dscr10;
  59. u32 dscr11;
  60. u32 dscr12;
  61. u32 dscr13;
  62. u32 pscr;
  63. u32 pmcr;
  64. u32 res1;
  65. u32 dcvr0;
  66. u32 dcvr1;
  67. u32 dcvr2;
  68. u32 dcvr3;
  69. };
  70. /* Chip Select Registers */
  71. struct weim_regs {
  72. u32 cs0u; /* Chip Select 0 Upper Register */
  73. u32 cs0l; /* Chip Select 0 Lower Register */
  74. u32 cs0a; /* Chip Select 0 Addition Register */
  75. u32 pad0;
  76. u32 cs1u; /* Chip Select 1 Upper Register */
  77. u32 cs1l; /* Chip Select 1 Lower Register */
  78. u32 cs1a; /* Chip Select 1 Addition Register */
  79. u32 pad1;
  80. u32 cs2u; /* Chip Select 2 Upper Register */
  81. u32 cs2l; /* Chip Select 2 Lower Register */
  82. u32 cs2a; /* Chip Select 2 Addition Register */
  83. u32 pad2;
  84. u32 cs3u; /* Chip Select 3 Upper Register */
  85. u32 cs3l; /* Chip Select 3 Lower Register */
  86. u32 cs3a; /* Chip Select 3 Addition Register */
  87. u32 pad3;
  88. u32 cs4u; /* Chip Select 4 Upper Register */
  89. u32 cs4l; /* Chip Select 4 Lower Register */
  90. u32 cs4a; /* Chip Select 4 Addition Register */
  91. u32 pad4;
  92. u32 cs5u; /* Chip Select 5 Upper Register */
  93. u32 cs5l; /* Chip Select 5 Lower Register */
  94. u32 cs5a; /* Chip Select 5 Addition Register */
  95. u32 pad5;
  96. u32 eim; /* WEIM Configuration Register */
  97. };
  98. /* SDRAM Controller registers */
  99. struct esdramc_regs {
  100. /* Enhanced SDRAM Control Register 0 */
  101. u32 esdctl0;
  102. /* Enhanced SDRAM Configuration Register 0 */
  103. u32 esdcfg0;
  104. /* Enhanced SDRAM Control Register 1 */
  105. u32 esdctl1;
  106. /* Enhanced SDRAM Configuration Register 1 */
  107. u32 esdcfg1;
  108. /* Enhanced SDRAM Miscellanious Register */
  109. u32 esdmisc;
  110. };
  111. /* Watchdog Registers*/
  112. struct wdog_regs {
  113. u32 wcr;
  114. u32 wsr;
  115. u32 wstr;
  116. };
  117. /* PLL registers */
  118. struct pll_regs {
  119. u32 cscr; /* Clock Source Control Register */
  120. u32 mpctl0; /* MCU PLL Control Register 0 */
  121. u32 mpctl1; /* MCU PLL Control Register 1 */
  122. u32 spctl0; /* System PLL Control Register 0 */
  123. u32 spctl1; /* System PLL Control Register 1 */
  124. u32 osc26mctl; /* Oscillator 26M Register */
  125. u32 pcdr0; /* Peripheral Clock Divider Register 0 */
  126. u32 pcdr1; /* Peripheral Clock Divider Register 1 */
  127. u32 pccr0; /* Peripheral Clock Control Register 0 */
  128. u32 pccr1; /* Peripheral Clock Control Register 1 */
  129. u32 ccsr; /* Clock Control Status Register */
  130. };
  131. /*
  132. * Definitions for the clocksource registers
  133. */
  134. struct gpt_regs {
  135. u32 gpt_tctl;
  136. u32 gpt_tprer;
  137. u32 gpt_tcmp;
  138. u32 gpt_tcr;
  139. u32 gpt_tcn;
  140. u32 gpt_tstat;
  141. };
  142. /*
  143. * GPIO Module and I/O Multiplexer
  144. */
  145. #define PORTA 0
  146. #define PORTB 1
  147. #define PORTC 2
  148. #define PORTD 3
  149. #define PORTE 4
  150. #define PORTF 5
  151. /* IIM Control Registers */
  152. struct iim_regs {
  153. u32 iim_stat;
  154. u32 iim_statm;
  155. u32 iim_err;
  156. u32 iim_emask;
  157. u32 iim_fctl;
  158. u32 iim_ua;
  159. u32 iim_la;
  160. u32 iim_sdat;
  161. u32 iim_prev;
  162. u32 iim_srev;
  163. u32 iim_prg_p;
  164. u32 iim_scs0;
  165. u32 iim_scs1;
  166. u32 iim_scs2;
  167. u32 iim_scs3;
  168. u32 res[0x1f1];
  169. struct fuse_bank {
  170. u32 fuse_regs[0x20];
  171. u32 fuse_rsvd[0xe0];
  172. } bank[1];
  173. };
  174. struct fuse_bank0_regs {
  175. u32 fuse0_3[5];
  176. u32 mac_addr[6];
  177. u32 fuse10_31[0x16];
  178. };
  179. #endif
  180. #define ARCH_MXC
  181. #define IMX_IO_BASE 0x10000000
  182. #define IMX_AIPI1_BASE (0x00000 + IMX_IO_BASE)
  183. #define IMX_WDT_BASE (0x02000 + IMX_IO_BASE)
  184. #define IMX_TIM1_BASE (0x03000 + IMX_IO_BASE)
  185. #define IMX_TIM2_BASE (0x04000 + IMX_IO_BASE)
  186. #define IMX_TIM3_BASE (0x05000 + IMX_IO_BASE)
  187. #define IMX_RTC_BASE (0x07000 + IMX_IO_BASE)
  188. #define UART1_BASE (0x0a000 + IMX_IO_BASE)
  189. #define UART2_BASE (0x0b000 + IMX_IO_BASE)
  190. #define UART3_BASE (0x0c000 + IMX_IO_BASE)
  191. #define UART4_BASE (0x0d000 + IMX_IO_BASE)
  192. #define IMX_I2C1_BASE (0x12000 + IMX_IO_BASE)
  193. #define IMX_GPIO_BASE (0x15000 + IMX_IO_BASE)
  194. #define IMX_TIM4_BASE (0x19000 + IMX_IO_BASE)
  195. #define IMX_TIM5_BASE (0x1a000 + IMX_IO_BASE)
  196. #define IMX_UART5_BASE (0x1b000 + IMX_IO_BASE)
  197. #define IMX_UART6_BASE (0x1c000 + IMX_IO_BASE)
  198. #define IMX_I2C2_BASE (0x1D000 + IMX_IO_BASE)
  199. #define IMX_TIM6_BASE (0x1f000 + IMX_IO_BASE)
  200. #define IMX_AIPI2_BASE (0x20000 + IMX_IO_BASE)
  201. #define IMX_PLL_BASE (0x27000 + IMX_IO_BASE)
  202. #define IMX_SYSTEM_CTL_BASE (0x27800 + IMX_IO_BASE)
  203. #define IMX_IIM_BASE (0x28000 + IMX_IO_BASE)
  204. #define IIM_BASE_ADDR IMX_IIM_BASE
  205. #define IMX_FEC_BASE (0x2b000 + IMX_IO_BASE)
  206. #define IMX_ESD_BASE (0xD8001000)
  207. #define IMX_WEIM_BASE (0xD8002000)
  208. /* FMCR System Control bit definition*/
  209. #define UART4_RXD_CTL (1 << 25)
  210. #define UART4_RTS_CTL (1 << 24)
  211. #define KP_COL6_CTL (1 << 18)
  212. #define KP_ROW7_CTL (1 << 17)
  213. #define KP_ROW6_CTL (1 << 16)
  214. #define PC_WAIT_B_CTL (1 << 14)
  215. #define PC_READY_CTL (1 << 13)
  216. #define PC_VS1_CTL (1 << 12)
  217. #define PC_VS2_CTL (1 << 11)
  218. #define PC_BVD1_CTL (1 << 10)
  219. #define PC_BVD2_CTL (1 << 9)
  220. #define IOS16_CTL (1 << 8)
  221. #define NF_FMS (1 << 5)
  222. #define NF_16BIT_SEL (1 << 4)
  223. #define SLCDC_SEL (1 << 2)
  224. #define SDCS1_SEL (1 << 1)
  225. #define SDCS0_SEL (1 << 0)
  226. /* important definition of some bits of WCR */
  227. #define WCR_WDE 0x04
  228. #define CSCR_MPEN (1 << 0)
  229. #define CSCR_SPEN (1 << 1)
  230. #define CSCR_FPM_EN (1 << 2)
  231. #define CSCR_OSC26M_DIS (1 << 3)
  232. #define CSCR_OSC26M_DIV1P5 (1 << 4)
  233. #define CSCR_AHB_DIV
  234. #define CSCR_ARM_DIV
  235. #define CSCR_ARM_SRC_MPLL (1 << 15)
  236. #define CSCR_MCU_SEL (1 << 16)
  237. #define CSCR_SP_SEL (1 << 17)
  238. #define CSCR_MPLL_RESTART (1 << 18)
  239. #define CSCR_SPLL_RESTART (1 << 19)
  240. #define CSCR_MSHC_SEL (1 << 20)
  241. #define CSCR_H264_SEL (1 << 21)
  242. #define CSCR_SSI1_SEL (1 << 22)
  243. #define CSCR_SSI2_SEL (1 << 23)
  244. #define CSCR_SD_CNT
  245. #define CSCR_USB_DIV
  246. #define CSCR_UPDATE_DIS (1 << 31)
  247. #define MPCTL1_BRMO (1 << 6)
  248. #define MPCTL1_LF (1 << 15)
  249. #define PCCR0_SSI2_EN (1 << 0)
  250. #define PCCR0_SSI1_EN (1 << 1)
  251. #define PCCR0_SLCDC_EN (1 << 2)
  252. #define PCCR0_SDHC3_EN (1 << 3)
  253. #define PCCR0_SDHC2_EN (1 << 4)
  254. #define PCCR0_SDHC1_EN (1 << 5)
  255. #define PCCR0_SDC_EN (1 << 6)
  256. #define PCCR0_SAHARA_EN (1 << 7)
  257. #define PCCR0_RTIC_EN (1 << 8)
  258. #define PCCR0_RTC_EN (1 << 9)
  259. #define PCCR0_PWM_EN (1 << 11)
  260. #define PCCR0_OWIRE_EN (1 << 12)
  261. #define PCCR0_MSHC_EN (1 << 13)
  262. #define PCCR0_LCDC_EN (1 << 14)
  263. #define PCCR0_KPP_EN (1 << 15)
  264. #define PCCR0_IIM_EN (1 << 16)
  265. #define PCCR0_I2C2_EN (1 << 17)
  266. #define PCCR0_I2C1_EN (1 << 18)
  267. #define PCCR0_GPT6_EN (1 << 19)
  268. #define PCCR0_GPT5_EN (1 << 20)
  269. #define PCCR0_GPT4_EN (1 << 21)
  270. #define PCCR0_GPT3_EN (1 << 22)
  271. #define PCCR0_GPT2_EN (1 << 23)
  272. #define PCCR0_GPT1_EN (1 << 24)
  273. #define PCCR0_GPIO_EN (1 << 25)
  274. #define PCCR0_FEC_EN (1 << 26)
  275. #define PCCR0_EMMA_EN (1 << 27)
  276. #define PCCR0_DMA_EN (1 << 28)
  277. #define PCCR0_CSPI3_EN (1 << 29)
  278. #define PCCR0_CSPI2_EN (1 << 30)
  279. #define PCCR0_CSPI1_EN (1 << 31)
  280. #define PCCR1_MSHC_BAUDEN (1 << 2)
  281. #define PCCR1_NFC_BAUDEN (1 << 3)
  282. #define PCCR1_SSI2_BAUDEN (1 << 4)
  283. #define PCCR1_SSI1_BAUDEN (1 << 5)
  284. #define PCCR1_H264_BAUDEN (1 << 6)
  285. #define PCCR1_PERCLK4_EN (1 << 7)
  286. #define PCCR1_PERCLK3_EN (1 << 8)
  287. #define PCCR1_PERCLK2_EN (1 << 9)
  288. #define PCCR1_PERCLK1_EN (1 << 10)
  289. #define PCCR1_HCLK_USB (1 << 11)
  290. #define PCCR1_HCLK_SLCDC (1 << 12)
  291. #define PCCR1_HCLK_SAHARA (1 << 13)
  292. #define PCCR1_HCLK_RTIC (1 << 14)
  293. #define PCCR1_HCLK_LCDC (1 << 15)
  294. #define PCCR1_HCLK_H264 (1 << 16)
  295. #define PCCR1_HCLK_FEC (1 << 17)
  296. #define PCCR1_HCLK_EMMA (1 << 18)
  297. #define PCCR1_HCLK_EMI (1 << 19)
  298. #define PCCR1_HCLK_DMA (1 << 20)
  299. #define PCCR1_HCLK_CSI (1 << 21)
  300. #define PCCR1_HCLK_BROM (1 << 22)
  301. #define PCCR1_HCLK_ATA (1 << 23)
  302. #define PCCR1_WDT_EN (1 << 24)
  303. #define PCCR1_USB_EN (1 << 25)
  304. #define PCCR1_UART6_EN (1 << 26)
  305. #define PCCR1_UART5_EN (1 << 27)
  306. #define PCCR1_UART4_EN (1 << 28)
  307. #define PCCR1_UART3_EN (1 << 29)
  308. #define PCCR1_UART2_EN (1 << 30)
  309. #define PCCR1_UART1_EN (1 << 31)
  310. /* SDRAM Controller registers bitfields */
  311. #define ESDCTL_PRCT(x) (((x) & 0x3f) << 0)
  312. #define ESDCTL_BL (1 << 7)
  313. #define ESDCTL_FP (1 << 8)
  314. #define ESDCTL_PWDT(x) (((x) & 3) << 10)
  315. #define ESDCTL_SREFR(x) (((x) & 7) << 13)
  316. #define ESDCTL_DSIZ_16_UPPER (0 << 16)
  317. #define ESDCTL_DSIZ_16_LOWER (1 << 16)
  318. #define ESDCTL_DSIZ_32 (2 << 16)
  319. #define ESDCTL_COL8 (0 << 20)
  320. #define ESDCTL_COL9 (1 << 20)
  321. #define ESDCTL_COL10 (2 << 20)
  322. #define ESDCTL_ROW11 (0 << 24)
  323. #define ESDCTL_ROW12 (1 << 24)
  324. #define ESDCTL_ROW13 (2 << 24)
  325. #define ESDCTL_ROW14 (3 << 24)
  326. #define ESDCTL_ROW15 (4 << 24)
  327. #define ESDCTL_SP (1 << 27)
  328. #define ESDCTL_SMODE_NORMAL (0 << 28)
  329. #define ESDCTL_SMODE_PRECHARGE (1 << 28)
  330. #define ESDCTL_SMODE_AUTO_REF (2 << 28)
  331. #define ESDCTL_SMODE_LOAD_MODE (3 << 28)
  332. #define ESDCTL_SMODE_MAN_REF (4 << 28)
  333. #define ESDCTL_SDE (1 << 31)
  334. #define ESDCFG_TRC(x) (((x) & 0xf) << 0)
  335. #define ESDCFG_TRCD(x) (((x) & 0x7) << 4)
  336. #define ESDCFG_TCAS(x) (((x) & 0x3) << 8)
  337. #define ESDCFG_TRRD(x) (((x) & 0x3) << 10)
  338. #define ESDCFG_TRAS(x) (((x) & 0x7) << 12)
  339. #define ESDCFG_TWR (1 << 15)
  340. #define ESDCFG_TMRD(x) (((x) & 0x3) << 16)
  341. #define ESDCFG_TRP(x) (((x) & 0x3) << 18)
  342. #define ESDCFG_TWTR (1 << 20)
  343. #define ESDCFG_TXP(x) (((x) & 0x3) << 21)
  344. #define ESDMISC_RST (1 << 1)
  345. #define ESDMISC_MDDREN (1 << 2)
  346. #define ESDMISC_MDDR_DL_RST (1 << 3)
  347. #define ESDMISC_MDDR_MDIS (1 << 4)
  348. #define ESDMISC_LHD (1 << 5)
  349. #define ESDMISC_MA10_SHARE (1 << 6)
  350. #define ESDMISC_SDRAM_RDY (1 << 31)
  351. #define PC5_PF_I2C2_DATA (GPIO_PORTC | GPIO_OUT | GPIO_PF | 5)
  352. #define PC6_PF_I2C2_CLK (GPIO_PORTC | GPIO_OUT | GPIO_PF | 6)
  353. #define PC7_PF_USBOTG_DATA5 (GPIO_PORTC | GPIO_OUT | GPIO_PF | 7)
  354. #define PC8_PF_USBOTG_DATA6 (GPIO_PORTC | GPIO_OUT | GPIO_PF | 8)
  355. #define PC9_PF_USBOTG_DATA0 (GPIO_PORTC | GPIO_OUT | GPIO_PF | 9)
  356. #define PC10_PF_USBOTG_DATA2 (GPIO_PORTC | GPIO_OUT | GPIO_PF | 10)
  357. #define PC11_PF_USBOTG_DATA1 (GPIO_PORTC | GPIO_OUT | GPIO_PF | 11)
  358. #define PC12_PF_USBOTG_DATA4 (GPIO_PORTC | GPIO_OUT | GPIO_PF | 12)
  359. #define PC13_PF_USBOTG_DATA3 (GPIO_PORTC | GPIO_OUT | GPIO_PF | 13)
  360. #define PD0_AIN_FEC_TXD0 (GPIO_PORTD | GPIO_OUT | GPIO_AIN | 0)
  361. #define PD1_AIN_FEC_TXD1 (GPIO_PORTD | GPIO_OUT | GPIO_AIN | 1)
  362. #define PD2_AIN_FEC_TXD2 (GPIO_PORTD | GPIO_OUT | GPIO_AIN | 2)
  363. #define PD3_AIN_FEC_TXD3 (GPIO_PORTD | GPIO_OUT | GPIO_AIN | 3)
  364. #define PD4_AOUT_FEC_RX_ER (GPIO_PORTD | GPIO_IN | GPIO_AOUT | 4)
  365. #define PD5_AOUT_FEC_RXD1 (GPIO_PORTD | GPIO_IN | GPIO_AOUT | 5)
  366. #define PD6_AOUT_FEC_RXD2 (GPIO_PORTD | GPIO_IN | GPIO_AOUT | 6)
  367. #define PD7_AOUT_FEC_RXD3 (GPIO_PORTD | GPIO_IN | GPIO_AOUT | 7)
  368. #define PD8_AF_FEC_MDIO (GPIO_PORTD | GPIO_IN | GPIO_AF | 8)
  369. #define PD9_AIN_FEC_MDC (GPIO_PORTD | GPIO_OUT | GPIO_AIN | 9)
  370. #define PD10_AOUT_FEC_CRS (GPIO_PORTD | GPIO_IN | GPIO_AOUT | 10)
  371. #define PD11_AOUT_FEC_TX_CLK (GPIO_PORTD | GPIO_IN | GPIO_AOUT | 11)
  372. #define PD12_AOUT_FEC_RXD0 (GPIO_PORTD | GPIO_IN | GPIO_AOUT | 12)
  373. #define PD13_AOUT_FEC_RX_DV (GPIO_PORTD | GPIO_IN | GPIO_AOUT | 13)
  374. #define PD14_AOUT_FEC_CLR (GPIO_PORTD | GPIO_IN | GPIO_AOUT | 14)
  375. #define PD15_AOUT_FEC_COL (GPIO_PORTD | GPIO_IN | GPIO_AOUT | 15)
  376. #define PD16_AIN_FEC_TX_ER (GPIO_PORTD | GPIO_OUT | GPIO_AIN | 16)
  377. #define PF23_AIN_FEC_TX_EN (GPIO_PORTF | GPIO_OUT | GPIO_AIN | 23)
  378. #define PE0_PF_USBOTG_NXT (GPIO_PORTE | GPIO_OUT | GPIO_PF | 0)
  379. #define PE1_PF_USBOTG_STP (GPIO_PORTE | GPIO_OUT | GPIO_PF | 1)
  380. #define PE2_PF_USBOTG_DIR (GPIO_PORTE | GPIO_OUT | GPIO_PF | 2)
  381. #define PE3_PF_UART2_CTS (GPIO_PORTE | GPIO_OUT | GPIO_PF | 3)
  382. #define PE4_PF_UART2_RTS (GPIO_PORTE | GPIO_IN | GPIO_PF | 4)
  383. #define PE6_PF_UART2_TXD (GPIO_PORTE | GPIO_OUT | GPIO_PF | 6)
  384. #define PE7_PF_UART2_RXD (GPIO_PORTE | GPIO_IN | GPIO_PF | 7)
  385. #define PE8_PF_UART3_TXD (GPIO_PORTE | GPIO_OUT | GPIO_PF | 8)
  386. #define PE9_PF_UART3_RXD (GPIO_PORTE | GPIO_IN | GPIO_PF | 9)
  387. #define PE10_PF_UART3_CTS (GPIO_PORTE | GPIO_OUT | GPIO_PF | 10)
  388. #define PE11_PF_UART3_RTS (GPIO_PORTE | GPIO_IN | GPIO_PF | 11)
  389. #define PE12_PF_UART1_TXD (GPIO_PORTE | GPIO_OUT | GPIO_PF | 12)
  390. #define PE13_PF_UART1_RXD (GPIO_PORTE | GPIO_IN | GPIO_PF | 13)
  391. #define PE14_PF_UART1_CTS (GPIO_PORTE | GPIO_OUT | GPIO_PF | 14)
  392. #define PE15_PF_UART1_RTS (GPIO_PORTE | GPIO_IN | GPIO_PF | 15)
  393. #define PE18_PF_SD1_D0 (GPIO_PORTE | GPIO_PF | 18)
  394. #define PE19_PF_SD1_D1 (GPIO_PORTE | GPIO_PF | 19)
  395. #define PE20_PF_SD1_D2 (GPIO_PORTE | GPIO_PF | 20)
  396. #define PE21_PF_SD1_D3 (GPIO_PORTE | GPIO_PF | 21)
  397. #define PE22_PF_SD1_CMD (GPIO_PORTE | GPIO_PF | 22)
  398. #define PE23_PF_SD1_CLK (GPIO_PORTE | GPIO_PF | 23)
  399. #define PB4_PF_SD2_D0 (GPIO_PORTB | GPIO_PF | 4)
  400. #define PB5_PF_SD2_D1 (GPIO_PORTB | GPIO_PF | 5)
  401. #define PB6_PF_SD2_D2 (GPIO_PORTB | GPIO_PF | 6)
  402. #define PB7_PF_SD2_D3 (GPIO_PORTB | GPIO_PF | 7)
  403. #define PB8_PF_SD2_CMD (GPIO_PORTB | GPIO_PF | 8)
  404. #define PB9_PF_SD2_CLK (GPIO_PORTB | GPIO_PF | 9)
  405. #define PD17_PF_I2C_DATA (GPIO_PORTD | GPIO_OUT | GPIO_PF | 17)
  406. #define PD18_PF_I2C_CLK (GPIO_PORTD | GPIO_OUT | GPIO_PF | 18)
  407. #define PE24_PF_USBOTG_CLK (GPIO_PORTE | GPIO_OUT | GPIO_PF | 24)
  408. #define PE25_PF_USBOTG_DATA7 (GPIO_PORTE | GPIO_OUT | GPIO_PF | 25)
  409. /* Clocksource Bitfields */
  410. #define TCTL_SWR (1 << 15) /* Software reset */
  411. #define TCTL_FRR (1 << 8) /* Freerun / restart */
  412. #define TCTL_CAP (3 << 6) /* Capture Edge */
  413. #define TCTL_OM (1 << 5) /* output mode */
  414. #define TCTL_IRQEN (1 << 4) /* interrupt enable */
  415. #define TCTL_CLKSOURCE 1 /* Clock source bit position */
  416. #define TCTL_TEN 1 /* Timer enable */
  417. #define TPRER_PRES 0xff /* Prescale */
  418. #define TSTAT_CAPT (1 << 1) /* Capture event */
  419. #define TSTAT_COMP 1 /* Compare event */
  420. #define GPIO1_BASE_ADDR 0x10015000
  421. #define GPIO2_BASE_ADDR 0x10015100
  422. #define GPIO3_BASE_ADDR 0x10015200
  423. #define GPIO4_BASE_ADDR 0x10015300
  424. #define GPIO5_BASE_ADDR 0x10015400
  425. #define GPIO6_BASE_ADDR 0x10015500
  426. #define GPIO_PIN_MASK 0x1f
  427. #define GPIO_PORT_SHIFT 5
  428. #define GPIO_PORT_MASK (0x7 << GPIO_PORT_SHIFT)
  429. #define GPIO_PORTA (PORTA << GPIO_PORT_SHIFT)
  430. #define GPIO_PORTB (PORTB << GPIO_PORT_SHIFT)
  431. #define GPIO_PORTC (PORTC << GPIO_PORT_SHIFT)
  432. #define GPIO_PORTD (PORTD << GPIO_PORT_SHIFT)
  433. #define GPIO_PORTE (PORTE << GPIO_PORT_SHIFT)
  434. #define GPIO_PORTF (PORTF << GPIO_PORT_SHIFT)
  435. #define GPIO_OUT (1 << 8)
  436. #define GPIO_IN (0 << 8)
  437. #define GPIO_PUEN (1 << 9)
  438. #define GPIO_PF (1 << 10)
  439. #define GPIO_AF (1 << 11)
  440. #define GPIO_OCR_SHIFT 12
  441. #define GPIO_OCR_MASK (3 << GPIO_OCR_SHIFT)
  442. #define GPIO_AIN (0 << GPIO_OCR_SHIFT)
  443. #define GPIO_BIN (1 << GPIO_OCR_SHIFT)
  444. #define GPIO_CIN (2 << GPIO_OCR_SHIFT)
  445. #define GPIO_GPIO (3 << GPIO_OCR_SHIFT)
  446. #define GPIO_AOUT_SHIFT 14
  447. #define GPIO_AOUT_MASK (3 << GPIO_AOUT_SHIFT)
  448. #define GPIO_AOUT (0 << GPIO_AOUT_SHIFT)
  449. #define GPIO_AOUT_ISR (1 << GPIO_AOUT_SHIFT)
  450. #define GPIO_AOUT_0 (2 << GPIO_AOUT_SHIFT)
  451. #define GPIO_AOUT_1 (3 << GPIO_AOUT_SHIFT)
  452. #define GPIO_BOUT_SHIFT 16
  453. #define GPIO_BOUT_MASK (3 << GPIO_BOUT_SHIFT)
  454. #define GPIO_BOUT (0 << GPIO_BOUT_SHIFT)
  455. #define GPIO_BOUT_ISR (1 << GPIO_BOUT_SHIFT)
  456. #define GPIO_BOUT_0 (2 << GPIO_BOUT_SHIFT)
  457. #define GPIO_BOUT_1 (3 << GPIO_BOUT_SHIFT)
  458. #define IIM_STAT_BUSY (1 << 7)
  459. #define IIM_STAT_PRGD (1 << 1)
  460. #define IIM_STAT_SNSD (1 << 0)
  461. #define IIM_ERR_PRGE (1 << 7)
  462. #define IIM_ERR_WPE (1 << 6)
  463. #define IIM_ERR_OPE (1 << 5)
  464. #define IIM_ERR_RPE (1 << 4)
  465. #define IIM_ERR_WLRE (1 << 3)
  466. #define IIM_ERR_SNSE (1 << 2)
  467. #define IIM_ERR_PARITYE (1 << 1)
  468. #endif /* _IMX_REGS_H */