1234567891011121314151617181920212223242526272829303132333435363738394041424344454647484950515253545556575859606162636465666768697071727374757677787980818283848586878889909192939495969798991001011021031041051061071081091101111121131141151161171181191201211221231241251261271281291301311321331341351361371381391401411421431441451461471481491501511521531541551561571581591601611621631641651661671681691701711721731741751761771781791801811821831841851861871881891901911921931941951961971981992002012022032042052062072082092102112122132142152162172182192202212222232242252262272282292302312322332342352362372382392402412422432442452462472482492502512522532542552562572582592602612622632642652662672682692702712722732742752762772782792802812822832842852862872882892902912922932942952962972982993003013023033043053063073083093103113123133143153163173183193203213223233243253263273283293303313323333343353363373383393403413423433443453463473483493503513523533543553563573583593603613623633643653663673683693703713723733743753763773783793803813823833843853863873883893903913923933943953963973983994004014024034044054064074084094104114124134144154164174184194204214224234244254264274284294304314324334344354364374384394404414424434444454464474484494504514524534544554564574584594604614624634644654664674684694704714724734744754764774784794804814824834844854864874884894904914924934944954964974984995005015025035045055065075085095105115125135145155165175185195205215225235245255265275285295305315325335345355365375385395405415425435445455465475485495505515525535545555565575585595605615625635645655665675685695705715725735745755765775785795805815825835845855865875885895905915925935945955965975985996006016026036046056066076086096106116126136146156166176186196206216226236246256266276286296306316326336346356366376386396406416426436446456466476486496506516526536546556566576586596606616626636646656666676686696706716726736746756766776786796806816826836846856866876886896906916926936946956966976986997007017027037047057067077087097107117127137147157167177187197207217227237247257267277287297307317327337347357367377387397407417427437447457467477487497507517527537547557567577587597607617627637647657667677687697707717727737747757767777787797807817827837847857867877887897907917927937947957967977987998008018028038048058068078088098108118128138148158168178188198208218228238248258268278288298308318328338348358368378388398408418428438448458468478488498508518528538548558568578588598608618628638648658668678688698708718728738748758768778788798808818828838848858868878888898908918928938948958968978988999009019029039049059069079089099109119129139149159169179189199209219229239249259269279289299309319329339349359369379389399409419429439449459469479489499509519529539549559569579589599609619629639649659669679689699709719729739749759769779789799809819829839849859869879889899909919929939949959969979989991000100110021003100410051006100710081009101010111012101310141015101610171018101910201021102210231024102510261027102810291030103110321033103410351036103710381039104010411042104310441045104610471048104910501051105210531054 |
- // SPDX-License-Identifier: (GPL-2.0 OR MIT)
- /* Copyright (c) 2021 StarFive Technology Co., Ltd. */
- /dts-v1/;
- #include "starfive_jh7100_clk.dtsi"
- #include <dt-bindings/clock/starfive-jh7100.h>
- #include <dt-bindings/starfive_fb.h>
- / {
- #address-cells = <2>;
- #size-cells = <2>;
- compatible = "starfive,jh7100";
- cpus {
- #address-cells = <1>;
- #size-cells = <0>;
- cpu@0 {
- compatible = "sifive,u74-mc", "riscv";
- d-cache-block-size = <64>;
- d-cache-sets = <64>;
- d-cache-size = <32768>;
- d-tlb-sets = <1>;
- d-tlb-size = <32>;
- device_type = "cpu";
- i-cache-block-size = <64>;
- i-cache-sets = <64>;
- i-cache-size = <32768>;
- i-tlb-sets = <1>;
- i-tlb-size = <32>;
- mmu-type = "riscv,sv39";
- next-level-cache = <&ccache>;
- reg = <0>;
- riscv,isa = "rv64imafdc";
- starfive,itim = <&itim0>;
- status = "okay";
- tlb-split;
- cpu0_intc: interrupt-controller {
- #interrupt-cells = <1>;
- compatible = "riscv,cpu-intc";
- interrupt-controller;
- };
- };
- cpu@1 {
- compatible = "sifive,u74-mc", "riscv";
- d-cache-block-size = <64>;
- d-cache-sets = <64>;
- d-cache-size = <32768>;
- d-tlb-sets = <1>;
- d-tlb-size = <32>;
- device_type = "cpu";
- i-cache-block-size = <64>;
- i-cache-sets = <64>;
- i-cache-size = <32768>;
- i-tlb-sets = <1>;
- i-tlb-size = <32>;
- mmu-type = "riscv,sv39";
- next-level-cache = <&ccache>;
- reg = <1>;
- riscv,isa = "rv64imafdc";
- starfive,itim = <&itim1>;
- status = "okay";
- tlb-split;
- cpu1_intc: interrupt-controller {
- #interrupt-cells = <1>;
- compatible = "riscv,cpu-intc";
- interrupt-controller;
- };
- };
- };
- osc_sys: osc_sys {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- /* This value must be overridden by the board */
- clock-frequency = <0>;
- };
- osc_aud: osc_aud {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- /* This value must be overridden by the board */
- clock-frequency = <0>;
- };
- soc {
- compatible = "simple-bus";
- interrupt-parent = <&plic>;
- #address-cells = <2>;
- #size-cells = <2>;
- ranges;
- ccache: cache-controller@2010000 {
- cache-block-size = <64>;
- cache-line-size = <64>;
- cache-level = <2>;
- cache-sets = <2048>;
- cache-size = <2097152>;
- cache-unified;
- #size-cells = <2>;
- compatible = "sifive,fu540-c000-ccache", "sifive,fu740-c000-ccache", "starfive,ccache0", "cache";
- interrupts = <128 131 129 130>;
- /*next-level-cache = <&L40 &L36>;*/
- reg = <0x0 0x2010000 0x0 0x1000>,
- <0x0 0x8000000 0x0 0x2000000>;
- reg-names = "control", "sideband";
- ranges = <0x0 0x0 0x0 0x80000000 0x8 0x0>;
- };
- dtim: dtim@1000000 {
- compatible = "starfive,dtim0";
- reg = <0x0 0x1000000 0x0 0x2000>;
- reg-names = "mem";
- };
- itim0: itim@1808000 {
- compatible = "starfive,itim0";
- reg = <0x0 0x1808000 0x0 0x8000>;
- reg-names = "mem";
- };
- itim1: itim@1820000 {
- compatible = "starfive,itim0";
- reg = <0x0 0x1820000 0x0 0x8000>;
- reg-names = "mem";
- };
- clint: clint@2000000 {
- #interrupt-cells = <1>;
- compatible = "riscv,clint0";
- interrupts-extended = <&cpu0_intc 3>,
- <&cpu0_intc 7>,
- <&cpu1_intc 3>,
- <&cpu1_intc 7>;
- reg = <0x0 0x2000000 0x0 0x10000>;
- reg-names = "control";
- };
- wdog: wdog@12480000 {
- compatible = "starfive,si5-wdt";
- reg = <0x0 0x12480000 0x0 0x10000>;
- interrupt-parent = <&plic>;
- interrupts = <80>;
- interrupt-names = "wdog";
- clocks = <&clkgen JH7100_CLK_WDT_CORE>,
- <&clkgen JH7100_CLK_WDTIMER_APB>;
- clock-names = "core_clk", "apb_clk";
- clock-frequency = <50000000>;
- timeout-sec = <15>;
- status = "okay";
- };
- plic: interrupt-controller@c000000 {
- #interrupt-cells = <1>;
- compatible = "riscv,plic0";
- interrupt-controller;
- interrupts-extended = <&cpu0_intc 11>,
- <&cpu0_intc 9>,
- <&cpu1_intc 11>,
- <&cpu1_intc 9>;
- reg = <0x0 0xc000000 0x0 0x4000000>;
- reg-names = "control";
- riscv,max-priority = <7>;
- riscv,ndev = <127>;
- };
- clkgen: clock-controller@11800000 {
- compatible = "starfive,jh7100-clkgen";
- reg = <0x0 0x11800000 0x0 0x10000>;
- clocks = <&osc_sys>, <&osc_aud>;
- clock-names = "osc_sys", "osc_aud";
- #clock-cells = <1>;
- };
- uart0: serial@11870000 {
- compatible = "snps,dw-apb-uart";
- interrupts = <92>;
- reg = <0x0 0x11870000 0x0 0x10000>;
- reg-io-width = <4>;
- reg-shift = <2>;
- clocks = <&clkgen JH7100_CLK_UART0_CORE>,
- <&clkgen JH7100_CLK_UART0_APB>;
- clock-names = "baudclk", "apb_pclk";
- current-clock = <74250000>;
- current-speed = <115200>;
- status = "disabled";
- };
- uart1: serial@11880000 {
- compatible = "snps,dw-apb-uart";
- interrupts = <93>;
- reg = <0x0 0x11880000 0x0 0x10000>;
- reg-io-width = <4>;
- reg-shift = <2>;
- clocks = <&clkgen JH7100_CLK_UART1_CORE>,
- <&clkgen JH7100_CLK_UART1_APB>;
- clock-names = "baudclk", "apb_pclk";
- current-clock = <74250000>;
- current-speed = <115200>;
- status = "disabled";
- };
- uart2: serial@12430000 {
- compatible = "snps,dw-apb-uart";
- interrupts = <72>;
- reg = <0x0 0x12430000 0x0 0x10000>;
- reg-io-width = <4>;
- reg-shift = <2>;
- clocks = <&clkgen JH7100_CLK_UART2_CORE>,
- <&clkgen JH7100_CLK_UART2_APB>;
- clock-names = "baudclk", "apb_pclk";
- current-clock = <100000000>;
- current-speed = <115200>;
- status = "disabled";
- };
- uart3: serial@12440000 {
- compatible = "snps,dw-apb-uart", "starfive,uart0";
- interrupts = <73>;
- reg = <0x0 0x12440000 0x0 0x10000>;
- reg-io-width = <4>;
- reg-shift = <2>;
- clocks = <&clkgen JH7100_CLK_UART3_CORE>,
- <&clkgen JH7100_CLK_UART3_APB>;
- clock-names = "baudclk", "apb_pclk";
- current-clock = <100000000>;
- current-speed = <115200>;
- status = "disabled";
- };
- dma2p: dma-controller@100b0000 {
- compatible = "snps,axi-dma-1.01a";
- reg = <0x0 0x100b0000 0x0 0x10000>;
- clocks = <&clkgen JH7100_CLK_SGDMA2P_AXI>,
- <&clkgen JH7100_CLK_SGDMA2P_AHB>;
- clock-names = "core-clk", "cfgr-clk";
- interrupts = <2>;
- #dma-cells = <1>;
- dma-channels = <4>;
- snps,dma-masters = <1>;
- snps,data-width = <4>;
- snps,block-size = <4096 4096 4096 4096>;
- snps,priority = <0 1 2 3>;
- snps,axi-max-burst-len = <128>;
- status = "okay";
- dma-coherent;
- };
- dma1p: dma-controller@10500000 {
- compatible = "snps,axi-dma-1.01a";
- reg = <0x0 0x10500000 0x0 0x10000>;
- clocks = <&clkgen JH7100_CLK_SGDMA1P_AXI>,
- <&clkgen JH7100_CLK_SGDMA1P_BUS>;
- clock-names = "core-clk", "cfgr-clk";
- interrupts = <1>;
- #dma-cells = <1>;
- dma-channels = <16>;
- snps,dma-masters = <1>;
- snps,data-width = <3>;
- snps,block-size = <4096 4096 4096 4096 4096 4096 4096 4096 4096 4096 4096 4096 4096 4096 4096 4096>;
- snps,priority = <0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15>;
- snps,axi-max-burst-len = <64>;
- status = "okay";
- };
- usb3: usb@104c0000 {
- compatible = "cdns,usb3";
- reg = <0x0 0x104c0000 0x0 0x10000>, // memory area for HOST registers
- <0x0 0x104d0000 0x0 0x10000>, // memory area for DEVICE registers
- <0x0 0x104e0000 0x0 0x10000>; // memory area for OTG/DRD registers
- reg-names = "otg", "xhci", "dev";
- interrupts = <44>, <52>, <43>;
- interrupt-names = "host", "peripheral", "otg";
- phy-names = "cdns3,usb3-phy", "cdns3,usb2-phy";
- maximum-speed = "super-speed";
- status = "disabled";
- };
- gpio: pinctrl@11910000 {
- compatible = "starfive,jh7100-pinctrl";
- reg = <0x0 0x11910000 0x0 0x10000>,
- <0x0 0x11858000 0x0 0x1000>;
- reg-names = "gpio", "padctl";
- clocks = <&clkgen JH7100_CLK_GPIO_APB>;
- gpio-controller;
- #gpio-cells = <2>;
- interrupts = <32>;
- interrupt-controller;
- #interrupt-cells = <2>;
- };
- i2c0: i2c@118b0000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "snps,designware-i2c";
- reg = <0x0 0x118b0000 0x0 0x10000>;
- interrupts = <96>;
- clocks = <&clkgen JH7100_CLK_I2C0_CORE>,
- <&clkgen JH7100_CLK_I2C0_APB>;
- clock-names = "ref", "pclk";
- status = "disabled";
- };
- i2c1: i2c@118c0000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "snps,designware-i2c";
- reg = <0x0 0x118c0000 0x0 0x10000>;
- interrupts = <97>;
- clocks = <&clkgen JH7100_CLK_I2C1_CORE>,
- <&clkgen JH7100_CLK_I2C1_APB>;
- clock-names = "ref", "pclk";
- status = "disabled";
- };
- i2c2: i2c@12450000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "snps,designware-i2c";
- reg = <0x0 0x12450000 0x0 0x10000>;
- interrupts = <74>;
- clocks = <&clkgen JH7100_CLK_I2C2_CORE>,
- <&clkgen JH7100_CLK_I2C2_APB>;
- clock-names = "ref", "pclk";
- status = "disabled";
- };
- i2c3: i2c@12460000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "snps,designware-i2c";
- reg = <0x0 0x12460000 0x0 0x10000>;
- interrupts = <75>;
- clocks = <&clkgen JH7100_CLK_I2C3_CORE>,
- <&clkgen JH7100_CLK_I2C3_APB>;
- clock-names = "ref", "pclk";
- status = "disabled";
- };
- trng: trng@118d0000 {
- compatible = "starfive,vic-rng";
- reg = <0x0 0x118d0000 0x0 0x10000>;
- interrupts = <98>;
- clocks = <&clkgen JH7100_CLK_TRNG_APB>;
- };
- crypto: crypto@100d0000 {
- compatible = "starfive,vic-sec";
- reg = <0x0 0x100d0000 0x0 0x20000>,
- <0x0 0x11800234 0x0 0xc>;
- reg-names = "secmem", "secclk";
- interrupts = <31>;
- clocks = <&clkgen JH7100_CLK_SEC_AHB>;
- };
- /* gmac device configuration */
- stmmac_axi_setup: stmmac-axi-config {
- snps,wr_osr_lmt = <0xf>;
- snps,rd_osr_lmt = <0xf>;
- snps,blen = <256 128 64 32 0 0 0>;
- };
- gmac: ethernet@10020000 {
- compatible = "snps,dwmac";
- reg = <0x0 0x10020000 0x0 0x10000>;
- interrupts = <6 7>;
- interrupt-names = "macirq", "eth_wake_irq";
- max-frame-size = <9000>;
- phy-mode = "rgmii-txid";
- snps,multicast-filter-bins = <256>;
- snps,perfect-filter-entries = <128>;
- rx-fifo-depth = <32768>;
- tx-fifo-depth = <16384>;
- clocks = <&clkgen JH7100_CLK_GMAC_AHB>,
- <&clkgen JH7100_CLK_GMAC_AHB>,
- <&clkgen JH7100_CLK_GMAC_PTP_REF>;
- clock-names = "stmmaceth", "pclk", "ptp_ref";
- snps,fixed-burst;
- snps,no-pbl-x8 = <1>;
- /*snps,force_sf_dma_mode;*/
- snps,force_thresh_dma_mode;
- snps,axi-config = <&stmmac_axi_setup>;
- };
- nvdla@11940000 {
- compatible = "nvidia,nvdla_os_initial";
- interrupts = <22>;
- memory-region = <&nvdla_reserved>;
- reg = <0x0 0x11940000 0x0 0x40000>;
- status = "okay";
- };
- jpu: coadj12@11900000 {
- compatible = "cm,codaj12-jpu-1";
- reg = <0x0 0x11900000 0x0 0x300>;
- memory-region = <&jpu_reserved>;
- interrupts = <24>;
- clocks = <&clkgen JH7100_CLK_JPEG_APB>;
- clock-names = "jpege";
- reg-names = "control";
- status = "okay";
- };
- vpu_dec: vpu_dec@118f0000 {
- compatible = "c&m,cm511-vpu";
- reg = <0 0x118f0000 0 0x10000>;
- //memory-region = <&vpu_reserved>;
- interrupts = <23>;
- clocks = <&clkgen JH7100_CLK_VP6_CORE>;
- clock-names = "vcodec";
- status = "okay";
- };
- vpu_enc: vpu_enc@118e0000 {
- compatible = "cm,cm521-vpu";
- reg = <0x0 0x118e0000 0x0 0x4000>;
- interrupts = <26>;
- clocks = <&clkgen JH7100_CLK_VP6_CORE>;
- clock-names = "vcodec";
- reg-names = "control";
- };
- ptc: pwm@12490000 {
- compatible = "starfive,pwm0";
- reg = <0x0 0x12490000 0x0 0x10000>;
- reg-names = "control";
- sifive,approx-period = <100000000>;
- clocks = <&clkgen JH7100_CLK_PWM_APB>;
- #pwm-cells = <3>;
- sifive,npwm = <8>;
- status = "disabled";
- };
- qspi: spi@11860000 {
- compatible = "cadence,qspi","cdns,qspi-nor";
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <0x0 0x11860000 0x0 0x10000>,
- <0x0 0x20000000 0x0 0x20000000>;
- interrupts = <3>;
- clocks = <&clkgen JH7100_CLK_QSPI_AHB>;
- cdns,fifo-depth = <256>;
- cdns,fifo-width = <4>;
- cdns,trigger-address = <0x0>;
- status = "okay";
- spi-max-frequency = <250000000>;
- };
- spi0: spi@11890000 {
- compatible = "snps,dw-apb-ssi";
- #address-cells = <1>;
- #size-cells = <0>;
- interrupts = <94>;
- reg = <0x0 0x11890000 0x0 0x10000>;
- clocks = <&clkgen JH7100_CLK_SPI0_CORE>,
- <&clkgen JH7100_CLK_SPI0_APB>;
- clock-names = "ssi_clk", "pclk";
- status = "disabled";
- };
- spi1: spi@118a0000 {
- compatible = "snps,dw-apb-ssi";
- #address-cells = <1>;
- #size-cells = <0>;
- interrupts = <95>;
- reg = <0x0 0x118a0000 0x0 0x10000>;
- clocks = <&clkgen JH7100_CLK_SPI1_CORE>,
- <&clkgen JH7100_CLK_SPI1_APB>;
- clock-names = "ssi_clk", "pclk";
- status = "disabled";
- };
- spi2: spi@12410000 {
- compatible = "snps,dw-apb-ssi";
- #address-cells = <1>;
- #size-cells = <0>;
- interrupts = <70>;
- reg = <0x0 0x12410000 0x0 0x10000>;
- clocks = <&clkgen JH7100_CLK_SPI2_CORE>,
- <&clkgen JH7100_CLK_SPI2_APB>;
- clock-names = "ssi_clk", "pclk";
- status = "disabled";
- };
- spi3: spi@12420000 {
- compatible = "snps,dw-apb-ssi";
- #address-cells = <1>;
- #size-cells = <0>;
- interrupts = <71>;
- reg = <0x0 0x12420000 0x0 0x10000>;
- clocks = <&clkgen JH7100_CLK_SPI3_CORE>,
- <&clkgen JH7100_CLK_SPI3_APB>;
- clock-names = "ssi_clk", "pclk";
- status = "disabled";
- };
- xrp@f0000000 {
- compatible = "cdns,xrp";
- reg = <0x0 0xf0000000 0x0 0x01ffffff>,
- <0x10 0x72000000 0x0 0x00001000>,
- <0x10 0x72001000 0x0 0x00fff000>,
- <0x0 0x124b0000 0x0 0x00010000>;
- clocks = <&clkgen JH7100_CLK_VP6_CORE>;
- firmware-name = "vp6_elf";
- dsp-irq = <19 20>;
- dsp-irq-src = <0x20 0x21>;
- intc-irq-mode = <1>;
- intc-irq = <0 1>;
- interrupts = <27 28>;
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x40000000 0x0 0x40000000 0x01000000>,
- <0xb0000000 0x10 0x70000000 0x3000000>;
- dsp@0 {
- };
- };
- sdio0: mmc@10000000 {
- compatible = "snps,dw-mshc";
- reg = <0x0 0x10000000 0x0 0x10000>;
- interrupts = <4>;
- clocks = <&clkgen JH7100_CLK_SDIO0_AHB>,
- <&clkgen JH7100_CLK_SDIO0_CCLKINT>;
- clock-names = "biu", "ciu";
- clock-frequency = <100000000>;
- data-addr = <0>;
- fifo-depth = <32>;
- fifo-watermark-aligned;
- bus-width = <4>;
- max-frequency = <10000000>;
- status = "disabled";
- };
- sdio1: mmc@10010000 {
- compatible = "snps,dw-mshc";
- reg = <0x0 0x10010000 0x0 0x10000>;
- interrupts = <5>;
- clocks = <&clkgen JH7100_CLK_SDIO1_AHB>,
- <&clkgen JH7100_CLK_SDIO1_CCLKINT>;
- clock-names = "biu", "ciu";
- clock-frequency = <100000000>;
- data-addr = <0>;
- fifo-depth = <32>;
- fifo-watermark-aligned;
- bus-width = <4>;
- max-frequency = <50000000>;
- status = "disabled";
- };
- sfivefb: sfivefb@12000000 {
- compatible = "starfive,vpp-lcdc";
- interrupts = <101>, <103>;
- interrupt-names = "lcdc_irq", "vpp1_irq";
- reg = <0x0 0x12000000 0x0 0x10000>,
- <0x0 0x12100000 0x0 0x10000>,
- <0x0 0x12040000 0x0 0x10000>,
- <0x0 0x12080000 0x0 0x10000>,
- <0x0 0x120c0000 0x0 0x10000>,
- <0x0 0x12240000 0x0 0x10000>,
- <0x0 0x12250000 0x0 0x10000>,
- <0x0 0x12260000 0x0 0x10000>;
- reg-names = "lcdc", "dsitx", "vpp0", "vpp1", "vpp2", "clk", "rst", "sys";
- memory-region = <&sffb_reserved>;
- #if 0 // FIXME uart clocks can't be right for lcdc
- clocks = <&clkgen JH7100_CLK_UART>,
- <&clkgen JH7100_CLK_APB2>;
- #endif
- clock-names = "baudclk", "apb_pclk";
- ddr-format = <WIN_FMT_RGB565>;/*LCDC win_format*/
- status = "disabled";
- };
- display-subsystem {
- compatible = "starfive,display-subsystem";
- memory-region = <&sffb_reserved>;
- status = "okay";
- dma-coherent;
- };
- display-encoder {
- compatible = "starfive,display-encoder";
- encoder-type = <2>; //2-TMDS, 3-LVDS, 6-DSI, 8-DPI
- status = "okay";
- ports {
- port@0 {
- hdmi_out:endpoint {
- remote-endpoint = <&tda998x_0_input>;
- //remote-endpoint = <&dsi_out_port>;
- };
- };
- port@1 {
- hdmi_input0:endpoint {
- remote-endpoint = <&crtc_0_out>;
- };
- };
- };
- };
- crtc: crtc@12000000 {
- compatible = "starfive,jh7100-crtc";
- status = "okay";
- interrupt-parent = <&plic>;
- interrupts = <101>, <103>;
- interrupt-names = "lcdc_irq", "vpp1_irq";
- reg = <0x0 0x12000000 0x0 0x10000>,
- //<0x0 0x12100000 0x0 0x10000>,
- <0x0 0x12040000 0x0 0x10000>,
- <0x0 0x12080000 0x0 0x10000>,
- <0x0 0x120c0000 0x0 0x10000>,
- <0x0 0x12240000 0x0 0x10000>,
- <0x0 0x12250000 0x0 0x10000>,
- <0x0 0x12260000 0x0 0x10000>;
- //reg-names = "lcdc", "dsitx", "vpp0", "vpp1", "vpp2", "clk", "rst", "sys";
- reg-names = "lcdc", "vpp0", "vpp1", "vpp2", "clk", "rst", "sys";
- clocks = <&uartclk>, <&apb2clk>;
- clock-names = "baudclk", "apb_pclk";
- ddr-format = <WIN_FMT_RGB565>;
- #address-cells = <1>;
- #size-cells = <0>;
- pp1 {
- pp-id = <1>;
- fifo-out;
- //sys-bus-out;
- src-format = <COLOR_RGB565>;
- src-width = <1920>;
- src-height = <1080>;
- dst-format = <COLOR_RGB888_ARGB>;
- dst-width = <1920>;
- dst-height = <1080>;
- };
- port: port@0 {
- reg = <0>;
- crtc_0_out: endpoint {
- remote-endpoint = <&hdmi_input0>;
- };
- };
- };
- mipi_dphy: mipi-dphy@12260000{
- compatible = "starfive,jh7100-mipi-dphy-tx";
- //reg = <0x0 0x12260000 0x0 0x10000>;
- clocks = <&uartclk>, <&apb2clk>;
- clock-names = "baudclk", "apb_pclk";
- #phy-cells = <0>;
- };
- mipi_dsi: mipi@12100000 {
- compatible = "cdns,dsi";
- clocks = <&apb1clk>, <&apb2clk>;
- clock-names = "dsi_p_clk", "dsi_sys_clk";
- phys = <&mipi_dphy>;
- phy-names = "dphy";
- status = "okay";
- reg = <0x0 0x12100000 0x0 0x10000>;
- reg-names = "dsi";
- port {
- dsi_out_port: endpoint {
- remote-endpoint = <&panel_dsi_port>;
- };
- };
- mipi_panel: panel@0 {
- //compatible = "";
- status = "okay";
- };
- };
- vin_sysctl: vin_sysctl@19800000 {
- compatible = "starfive,stf-vin";
- reg = <0x0 0x19800000 0x0 0x10000>,
- <0x0 0x19810000 0x0 0x10000>,
- <0x0 0x19820000 0x0 0x10000>,
- <0x0 0x19830000 0x0 0x10000>,
- <0x0 0x19840000 0x0 0x10000>,
- <0x0 0x19870000 0x0 0x30000>,
- <0x0 0x198a0000 0x0 0x30000>,
- <0x0 0x11800000 0x0 0x10000>,
- <0x0 0x11840000 0x0 0x10000>;
- reg-names = "mipi0", "vclk", "vrst", "mipi1", "sctrl",
- "isp0", "isp1", "tclk", "trst";
- interrupts = <119 109 112>;
- memory-region = <&vin_reserved>;
- pinctrl-names = "default";
- pinctrl-0 = <&dvpsensor_pins>;
- status = "okay";
- clocks = <&clkgen JH7100_CLK_VIN_SRC>,
- <&clkgen JH7100_CLK_ISP0_AXI>,
- <&clkgen JH7100_CLK_ISP0NOC_AXI>,
- <&clkgen JH7100_CLK_ISPSLV_AXI>,
- <&clkgen JH7100_CLK_ISP1_AXI>,
- <&clkgen JH7100_CLK_ISP1NOC_AXI>,
- <&clkgen JH7100_CLK_VIN_AXI>,
- <&clkgen JH7100_CLK_VINNOC_AXI>;
- // <&clkgen JH7100_CLK_CSI2RX_APB>,
- // <&clkgen JH7100_CLK_MIPI_RX0_PXL_0>,
- // <&clkgen JH7100_CLK_MIPI_RX0_PXL_1>,
- // <&clkgen JH7100_CLK_MIPI_RX0_PXL_2>,
- // <&clkgen JH7100_CLK_MIPI_RX0_PXL_3>,
- // <&clkgen JH7100_CLK_MIPI_RX0_SYS>,
- // <&clkgen JH7100_CLK_MIPI_RX1_PXL_0>,
- // <&clkgen JH7100_CLK_MIPI_RX1_PXL_1>,
- // <&clkgen JH7100_CLK_MIPI_RX1_PXL_2>,
- // <&clkgen JH7100_CLK_MIPI_RX1_PXL_3>,
- // <&clkgen JH7100_CLK_MIPI_RX1_SYS>,
- // <&clkgen JH7100_CLK_DPHY_CFGCLK>,
- // <&clkgen JH7100_CLK_DPHY_REFCLK>,
- // <&clkgen JH7100_CLK_DPHY_TXCLKESC>,
- // <&clkgen JH7100_CLK_ISP0_CTRL>,
- // <&clkgen JH7100_CLK_ISP0_2X_CTRL>,
- // <&clkgen JH7100_CLK_ISP0_MIPI_CTRL>,
- // <&clkgen JH7100_CLK_ISP1_CTRL>,
- // <&clkgen JH7100_CLK_ISP1_2X_CTRL>,
- // <&clkgen JH7100_CLK_ISP1_MIPI_CTRL>;
- clock-names = "vin_src",
- "isp0_axi",
- "isp0noc_axi",
- "ispslv_axi",
- "isp1_axi",
- "isp1noc_axi",
- "vin_axi",
- "vinnoc_axi";
- // "csi2rx_apb_clk",
- // "mipirx0_pixel0",
- // "mipirx0_pixel1",
- // "mipirx0_pixel2",
- // "mipirx0_pixel3",
- // "mipirx0_sys",
- // "mipirx1_pixel0",
- // "mipirx1_pixel1",
- // "mipirx1_pixel2",
- // "mipirx1_pixel3",
- // "mipirx1_sys",
- // "csidphy_cfgclk",
- // "csidphy_regclk",
- // "csidphy_txclkesc",
- // "isp0_ctrl",
- // "isp0_2x_ctrl",
- // "isp0_mipi_ctrl",
- // "isp1_ctrl",
- // "isp1_2x_ctrl",
- // "isp1_mipi_ctrl";
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
- port@0 {
- reg = <0>;
- dphy0_out_csi2rx: endpoint {
- remote-endpoint = <&csi2rx0_in_dphy>;
- clock-lanes = <0>;
- data-lanes = <1 2>;
- status = "failed";
- };
- };
- //port@1 {
- // reg = <1>;
- // dphy1_out_csi2rx: endpoint {
- // remote-endpoint = <&csi2rx1_in_dphy>;
- // clock-lanes = <0>;
- // data-lanes = <1 2>;
- // status = "failed";
- // };
- //};
- /* TODO: Used for EVB board, comment here for starlight board, remove it later*/
- port@2 {
- reg = <2>; // dvp sensor
- // Parallel bus endpoint
- parallel_from_ov5640: endpoint {
- remote-endpoint = <&ov5640_to_parallel>;
- bus-type = <5>; // Parallel
- bus-width = <8>;
- data-shift = <2>; // lines 9:2 are used
- hsync-active = <1>;
- vsync-active = <0>;
- pclk-sample = <1>;
- status = "failed";
- };
- };
- port@3 {
- reg = <2>; //dvp sensor
- // Parallel bus endpoint
- parallel_from_sc2235: endpoint {
- remote-endpoint = <&sc2235_to_parallel>;
- bus-type = <5>; // Parallel
- bus-width = <8>;
- data-shift = <2>; // lines 9:2 are used
- hsync-active = <1>;
- vsync-active = <1>;
- pclk-sample = <1>;
- status = "failed";
- };
- };
- port@4 {
- reg = <3>; //csi2rx0 sensor
- /* CSI2 bus endpoint */
- csi2rx0_from_imx219: endpoint {
- remote-endpoint = <&imx219_to_csi2rx0>;
- bus-type = <4>; /* MIPI CSI-2 D-PHY */
- clock-lanes = <0>;
- data-lanes = <1 2>;
- status = "okay";
- };
- };
- port@5 {
- reg = <4>; // csi2rx1 sensor
- /* CSI2 bus endpoint */
- csi2rx1_from_imx219: endpoint {
- remote-endpoint = <&imx219_to_csi2rx1>;
- bus-type = <4>; /* MIPI CSI-2 D-PHY */
- clock-lanes = <5>;
- data-lanes = <3 4>;
- lane-polarities = <0 1 0>;
- status = "okay";
- };
- };
- };
- };
- csi2rx: csi-bridge@19800000 {
- compatible = "cdns,csi2rx";
- reg = <0x0 0x19800000 0x0 0x10000>;
- clocks = <&byteclock>, <&byteclock>,
- <&coreclock>, <&coreclock>,
- <&coreclock>, <&coreclock>;
- clock-names = "sys_clk", "p_clk",
- "pixel_if0_clk", "pixel_if1_clk",
- "pixel_if2_clk", "pixel_if3_clk";
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
- port@0 {
- reg = <0>;
- csi2rx0_in_dphy: endpoint {
- remote-endpoint = <&dphy0_out_csi2rx>;
- clock-lanes = <0>;
- data-lanes = <1 2>;
- };
- };
- };
- };
- sfctemp: tmon@124a0000 {
- compatible = "starfive,jh7100-temp";
- reg = <0x0 0x124a0000 0x0 0x10000>;
- #thermal-sensor-cells = <0>;
- interrupts = <122>;
- };
- thermal-zones {
- cpu-thermal {
- polling-delay-passive = <250>;
- polling-delay = <15000>;
- thermal-sensors = <&sfctemp>;
- cooling-maps {
- };
- trips {
- cpu_alert0: cpu_alert0 {
- /* milliCelsius */
- temperature = <75000>;
- hysteresis = <2000>;
- type = "passive";
- };
- cpu_crit: cpu_crit {
- /* milliCelsius */
- temperature = <90000>;
- hysteresis = <2000>;
- type = "critical";
- };
- };
- };
- };
- otp: otp@11810000 {
- compatible = "starfive,fu740-otp";
- reg = <0x0 0x11810000 0x0 0x10000>;
- fuse-count = <0x200>;
- clocks = <&clkgen JH7100_CLK_OTP_APB>;
- };
- i2sadc0: i2sadc0@10400000 {
- compatible = "snps,designware-i2sadc0";
- reg = <0x0 0x10400000 0x0 0x1000>;
- interrupt-parent = <&plic>;
- /* interrupts = <59>; */
- /* interrupt-names = "rx"; */
- clocks = <&apb1clk>;
- clock-names = "i2sclk";
- #sound-dai-cells = <0>;
- dmas = <&dma2p 28>;
- dma-names = "rx";
- };
- i2svad: i2svad@10420000 {
- compatible = "sf,sf-i2svad";
- reg = <0x0 0x10420000 0x0 0x1000> ;
- interrupt-parent = <&plic>;
- interrupts = <60>, <61>;
- interrupt-names = "spintr", "slintr";
- clocks = <&apb1clk>;
- clock-names = "i2sclk";
- #sound-dai-cells = <0>;
- };
- i2sdac0: i2sdac0@10450000 {
- compatible = "snps,designware-i2sdac0";
- reg = <0x0 0x10450000 0x0 0x1000>;
- interrupt-parent = <&plic>;
- /*interrupts = <64>; */
- /*interrupt-names = "tx";*/
- clocks = <&apb1clk>;
- clock-names = "i2sclk";
- #sound-dai-cells = <0>;
- dmas = <&dma2p 30>;
- dma-names = "tx";
- };
- i2sdac1: i2sdac1@10460000 {
- compatible = "snps,designware-i2sdac1";
- reg = <0x0 0x10460000 0x0 0x1000>;
- interrupt-parent = <&plic>;
- /*interrupts = <66>;*/
- /*interrupt-names = "tx";*/
- clocks = <&apb1clk>;
- clock-names = "i2sclk";
- #sound-dai-cells = <0>;
- dmas = <&dma2p 31>;
- dma-names = "tx";
- };
- i2sdac16k: i2sdac16k@10470000 {
- compatible = "snps,designware-i2sdac16k";
- reg = <0x0 0x10470000 0x0 0x1000>;
- interrupt-parent = <&plic>;
- /* interrupts = <68>; */
- /* interrupt-names = "tx"; */
- clocks = <&apb1clk>;
- clock-names = "i2sclk";
- #sound-dai-cells = <0>;
- dmas = <&dma2p 29>;
- dma-names = "tx";
- };
- spdif0: spdif0@10430000 {
- compatible = "starfive,sf-spdif";
- reg = <0x0 0x10430000 0x0 0x1000>;
- interrupt-parent = <&plic>;
- interrupts = <62>;
- interrupt-names = "tx";
- clocks = <&audioclk>;
- clock-names = "audioclk";
- #sound-dai-cells = <0>;
- };
- pdm: pdm@10410000 {
- compatible = "starfive,sf-pdm";
- reg = <0x0 0x10410000 0x0 0x1000>, <0x0 0x10480000 0x0 0x1000>;
- reg-names = "pdm", "audio-clk";
- clocks = <&audioclk>;
- clock-names = "audioclk";
- #sound-dai-cells = <0>;
- };
- ac108_mclk: ac108_mclk {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <24576000>;
- };
- wm8960_mclk: wm8960_mclk {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <24576000>;
- };
- spdif_transmitter: spdif_transmitter {
- compatible = "linux,spdif-dit";
- #sound-dai-cells = <0>;
- };
- spdif_receiver: spdif_receiver {
- compatible = "linux,spdif-dir";
- #sound-dai-cells = <0>;
- };
- pwmdac: pwmdac@10440000 {
- compatible = "sf,pwmdac";
- reg = <0x0 0x10440000 0x0 0x1000>;
- clocks = <&apb1clk>;
- dmas = <&dma2p 23>;
- dma-names = "tx";
- #sound-dai-cells = <0>;
- };
- pwmdac_codec: pwmdac-transmitter {
- compatible = "linux,pwmdac-dit";
- #sound-dai-cells = <0>;
- };
- dmic_codec: dmic_codec {
- compatible = "dmic-codec";
- #sound-dai-cells = <0>;
- };
- sound:snd-card{
- compatible = "simple-audio-card";
- simple-audio-card,name = "Starfive-Multi-Sound-Card";
- #address-cells = <1>;
- #size-cells = <0>;
- /* pwmdac */
- simple-audio-card,dai-link@0 {
- reg = <0>;
- status = "okay";
- format = "left_j";
- bitclock-master = <&sndcpu0>;
- frame-master = <&sndcpu0>;
- sndcpu0: cpu {
- sound-dai = <&pwmdac>;
- };
- codec {
- sound-dai = <&pwmdac_codec>;
- };
- };
- };
- };
- };
|