jh7100.dtsi 26 KB

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  1. // SPDX-License-Identifier: (GPL-2.0 OR MIT)
  2. /* Copyright (c) 2021 StarFive Technology Co., Ltd. */
  3. /dts-v1/;
  4. #include "starfive_jh7100_clk.dtsi"
  5. #include <dt-bindings/clock/starfive-jh7100.h>
  6. #include <dt-bindings/starfive_fb.h>
  7. / {
  8. #address-cells = <2>;
  9. #size-cells = <2>;
  10. compatible = "starfive,jh7100";
  11. cpus {
  12. #address-cells = <1>;
  13. #size-cells = <0>;
  14. cpu@0 {
  15. compatible = "sifive,u74-mc", "riscv";
  16. d-cache-block-size = <64>;
  17. d-cache-sets = <64>;
  18. d-cache-size = <32768>;
  19. d-tlb-sets = <1>;
  20. d-tlb-size = <32>;
  21. device_type = "cpu";
  22. i-cache-block-size = <64>;
  23. i-cache-sets = <64>;
  24. i-cache-size = <32768>;
  25. i-tlb-sets = <1>;
  26. i-tlb-size = <32>;
  27. mmu-type = "riscv,sv39";
  28. next-level-cache = <&ccache>;
  29. reg = <0>;
  30. riscv,isa = "rv64imafdc";
  31. starfive,itim = <&itim0>;
  32. status = "okay";
  33. tlb-split;
  34. cpu0_intc: interrupt-controller {
  35. #interrupt-cells = <1>;
  36. compatible = "riscv,cpu-intc";
  37. interrupt-controller;
  38. };
  39. };
  40. cpu@1 {
  41. compatible = "sifive,u74-mc", "riscv";
  42. d-cache-block-size = <64>;
  43. d-cache-sets = <64>;
  44. d-cache-size = <32768>;
  45. d-tlb-sets = <1>;
  46. d-tlb-size = <32>;
  47. device_type = "cpu";
  48. i-cache-block-size = <64>;
  49. i-cache-sets = <64>;
  50. i-cache-size = <32768>;
  51. i-tlb-sets = <1>;
  52. i-tlb-size = <32>;
  53. mmu-type = "riscv,sv39";
  54. next-level-cache = <&ccache>;
  55. reg = <1>;
  56. riscv,isa = "rv64imafdc";
  57. starfive,itim = <&itim1>;
  58. status = "okay";
  59. tlb-split;
  60. cpu1_intc: interrupt-controller {
  61. #interrupt-cells = <1>;
  62. compatible = "riscv,cpu-intc";
  63. interrupt-controller;
  64. };
  65. };
  66. };
  67. osc_sys: osc_sys {
  68. compatible = "fixed-clock";
  69. #clock-cells = <0>;
  70. /* This value must be overridden by the board */
  71. clock-frequency = <0>;
  72. };
  73. osc_aud: osc_aud {
  74. compatible = "fixed-clock";
  75. #clock-cells = <0>;
  76. /* This value must be overridden by the board */
  77. clock-frequency = <0>;
  78. };
  79. soc {
  80. compatible = "simple-bus";
  81. interrupt-parent = <&plic>;
  82. #address-cells = <2>;
  83. #size-cells = <2>;
  84. ranges;
  85. ccache: cache-controller@2010000 {
  86. cache-block-size = <64>;
  87. cache-line-size = <64>;
  88. cache-level = <2>;
  89. cache-sets = <2048>;
  90. cache-size = <2097152>;
  91. cache-unified;
  92. #size-cells = <2>;
  93. compatible = "sifive,fu540-c000-ccache", "sifive,fu740-c000-ccache", "starfive,ccache0", "cache";
  94. interrupts = <128 131 129 130>;
  95. /*next-level-cache = <&L40 &L36>;*/
  96. reg = <0x0 0x2010000 0x0 0x1000>,
  97. <0x0 0x8000000 0x0 0x2000000>;
  98. reg-names = "control", "sideband";
  99. ranges = <0x0 0x0 0x0 0x80000000 0x8 0x0>;
  100. };
  101. dtim: dtim@1000000 {
  102. compatible = "starfive,dtim0";
  103. reg = <0x0 0x1000000 0x0 0x2000>;
  104. reg-names = "mem";
  105. };
  106. itim0: itim@1808000 {
  107. compatible = "starfive,itim0";
  108. reg = <0x0 0x1808000 0x0 0x8000>;
  109. reg-names = "mem";
  110. };
  111. itim1: itim@1820000 {
  112. compatible = "starfive,itim0";
  113. reg = <0x0 0x1820000 0x0 0x8000>;
  114. reg-names = "mem";
  115. };
  116. clint: clint@2000000 {
  117. #interrupt-cells = <1>;
  118. compatible = "riscv,clint0";
  119. interrupts-extended = <&cpu0_intc 3>,
  120. <&cpu0_intc 7>,
  121. <&cpu1_intc 3>,
  122. <&cpu1_intc 7>;
  123. reg = <0x0 0x2000000 0x0 0x10000>;
  124. reg-names = "control";
  125. };
  126. wdog: wdog@12480000 {
  127. compatible = "starfive,si5-wdt";
  128. reg = <0x0 0x12480000 0x0 0x10000>;
  129. interrupt-parent = <&plic>;
  130. interrupts = <80>;
  131. interrupt-names = "wdog";
  132. clocks = <&clkgen JH7100_CLK_WDT_CORE>,
  133. <&clkgen JH7100_CLK_WDTIMER_APB>;
  134. clock-names = "core_clk", "apb_clk";
  135. clock-frequency = <50000000>;
  136. timeout-sec = <15>;
  137. status = "okay";
  138. };
  139. plic: interrupt-controller@c000000 {
  140. #interrupt-cells = <1>;
  141. compatible = "riscv,plic0";
  142. interrupt-controller;
  143. interrupts-extended = <&cpu0_intc 11>,
  144. <&cpu0_intc 9>,
  145. <&cpu1_intc 11>,
  146. <&cpu1_intc 9>;
  147. reg = <0x0 0xc000000 0x0 0x4000000>;
  148. reg-names = "control";
  149. riscv,max-priority = <7>;
  150. riscv,ndev = <127>;
  151. };
  152. clkgen: clock-controller@11800000 {
  153. compatible = "starfive,jh7100-clkgen";
  154. reg = <0x0 0x11800000 0x0 0x10000>;
  155. clocks = <&osc_sys>, <&osc_aud>;
  156. clock-names = "osc_sys", "osc_aud";
  157. #clock-cells = <1>;
  158. };
  159. uart0: serial@11870000 {
  160. compatible = "snps,dw-apb-uart";
  161. interrupts = <92>;
  162. reg = <0x0 0x11870000 0x0 0x10000>;
  163. reg-io-width = <4>;
  164. reg-shift = <2>;
  165. clocks = <&clkgen JH7100_CLK_UART0_CORE>,
  166. <&clkgen JH7100_CLK_UART0_APB>;
  167. clock-names = "baudclk", "apb_pclk";
  168. current-clock = <74250000>;
  169. current-speed = <115200>;
  170. status = "disabled";
  171. };
  172. uart1: serial@11880000 {
  173. compatible = "snps,dw-apb-uart";
  174. interrupts = <93>;
  175. reg = <0x0 0x11880000 0x0 0x10000>;
  176. reg-io-width = <4>;
  177. reg-shift = <2>;
  178. clocks = <&clkgen JH7100_CLK_UART1_CORE>,
  179. <&clkgen JH7100_CLK_UART1_APB>;
  180. clock-names = "baudclk", "apb_pclk";
  181. current-clock = <74250000>;
  182. current-speed = <115200>;
  183. status = "disabled";
  184. };
  185. uart2: serial@12430000 {
  186. compatible = "snps,dw-apb-uart";
  187. interrupts = <72>;
  188. reg = <0x0 0x12430000 0x0 0x10000>;
  189. reg-io-width = <4>;
  190. reg-shift = <2>;
  191. clocks = <&clkgen JH7100_CLK_UART2_CORE>,
  192. <&clkgen JH7100_CLK_UART2_APB>;
  193. clock-names = "baudclk", "apb_pclk";
  194. current-clock = <100000000>;
  195. current-speed = <115200>;
  196. status = "disabled";
  197. };
  198. uart3: serial@12440000 {
  199. compatible = "snps,dw-apb-uart", "starfive,uart0";
  200. interrupts = <73>;
  201. reg = <0x0 0x12440000 0x0 0x10000>;
  202. reg-io-width = <4>;
  203. reg-shift = <2>;
  204. clocks = <&clkgen JH7100_CLK_UART3_CORE>,
  205. <&clkgen JH7100_CLK_UART3_APB>;
  206. clock-names = "baudclk", "apb_pclk";
  207. current-clock = <100000000>;
  208. current-speed = <115200>;
  209. status = "disabled";
  210. };
  211. dma2p: dma-controller@100b0000 {
  212. compatible = "snps,axi-dma-1.01a";
  213. reg = <0x0 0x100b0000 0x0 0x10000>;
  214. clocks = <&clkgen JH7100_CLK_SGDMA2P_AXI>,
  215. <&clkgen JH7100_CLK_SGDMA2P_AHB>;
  216. clock-names = "core-clk", "cfgr-clk";
  217. interrupts = <2>;
  218. #dma-cells = <1>;
  219. dma-channels = <4>;
  220. snps,dma-masters = <1>;
  221. snps,data-width = <4>;
  222. snps,block-size = <4096 4096 4096 4096>;
  223. snps,priority = <0 1 2 3>;
  224. snps,axi-max-burst-len = <128>;
  225. status = "okay";
  226. dma-coherent;
  227. };
  228. dma1p: dma-controller@10500000 {
  229. compatible = "snps,axi-dma-1.01a";
  230. reg = <0x0 0x10500000 0x0 0x10000>;
  231. clocks = <&clkgen JH7100_CLK_SGDMA1P_AXI>,
  232. <&clkgen JH7100_CLK_SGDMA1P_BUS>;
  233. clock-names = "core-clk", "cfgr-clk";
  234. interrupts = <1>;
  235. #dma-cells = <1>;
  236. dma-channels = <16>;
  237. snps,dma-masters = <1>;
  238. snps,data-width = <3>;
  239. snps,block-size = <4096 4096 4096 4096 4096 4096 4096 4096 4096 4096 4096 4096 4096 4096 4096 4096>;
  240. snps,priority = <0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15>;
  241. snps,axi-max-burst-len = <64>;
  242. status = "okay";
  243. };
  244. usb3: usb@104c0000 {
  245. compatible = "cdns,usb3";
  246. reg = <0x0 0x104c0000 0x0 0x10000>, // memory area for HOST registers
  247. <0x0 0x104d0000 0x0 0x10000>, // memory area for DEVICE registers
  248. <0x0 0x104e0000 0x0 0x10000>; // memory area for OTG/DRD registers
  249. reg-names = "otg", "xhci", "dev";
  250. interrupts = <44>, <52>, <43>;
  251. interrupt-names = "host", "peripheral", "otg";
  252. phy-names = "cdns3,usb3-phy", "cdns3,usb2-phy";
  253. maximum-speed = "super-speed";
  254. status = "disabled";
  255. };
  256. gpio: pinctrl@11910000 {
  257. compatible = "starfive,jh7100-pinctrl";
  258. reg = <0x0 0x11910000 0x0 0x10000>,
  259. <0x0 0x11858000 0x0 0x1000>;
  260. reg-names = "gpio", "padctl";
  261. clocks = <&clkgen JH7100_CLK_GPIO_APB>;
  262. gpio-controller;
  263. #gpio-cells = <2>;
  264. interrupts = <32>;
  265. interrupt-controller;
  266. #interrupt-cells = <2>;
  267. };
  268. i2c0: i2c@118b0000 {
  269. #address-cells = <1>;
  270. #size-cells = <0>;
  271. compatible = "snps,designware-i2c";
  272. reg = <0x0 0x118b0000 0x0 0x10000>;
  273. interrupts = <96>;
  274. clocks = <&clkgen JH7100_CLK_I2C0_CORE>,
  275. <&clkgen JH7100_CLK_I2C0_APB>;
  276. clock-names = "ref", "pclk";
  277. status = "disabled";
  278. };
  279. i2c1: i2c@118c0000 {
  280. #address-cells = <1>;
  281. #size-cells = <0>;
  282. compatible = "snps,designware-i2c";
  283. reg = <0x0 0x118c0000 0x0 0x10000>;
  284. interrupts = <97>;
  285. clocks = <&clkgen JH7100_CLK_I2C1_CORE>,
  286. <&clkgen JH7100_CLK_I2C1_APB>;
  287. clock-names = "ref", "pclk";
  288. status = "disabled";
  289. };
  290. i2c2: i2c@12450000 {
  291. #address-cells = <1>;
  292. #size-cells = <0>;
  293. compatible = "snps,designware-i2c";
  294. reg = <0x0 0x12450000 0x0 0x10000>;
  295. interrupts = <74>;
  296. clocks = <&clkgen JH7100_CLK_I2C2_CORE>,
  297. <&clkgen JH7100_CLK_I2C2_APB>;
  298. clock-names = "ref", "pclk";
  299. status = "disabled";
  300. };
  301. i2c3: i2c@12460000 {
  302. #address-cells = <1>;
  303. #size-cells = <0>;
  304. compatible = "snps,designware-i2c";
  305. reg = <0x0 0x12460000 0x0 0x10000>;
  306. interrupts = <75>;
  307. clocks = <&clkgen JH7100_CLK_I2C3_CORE>,
  308. <&clkgen JH7100_CLK_I2C3_APB>;
  309. clock-names = "ref", "pclk";
  310. status = "disabled";
  311. };
  312. trng: trng@118d0000 {
  313. compatible = "starfive,vic-rng";
  314. reg = <0x0 0x118d0000 0x0 0x10000>;
  315. interrupts = <98>;
  316. clocks = <&clkgen JH7100_CLK_TRNG_APB>;
  317. };
  318. crypto: crypto@100d0000 {
  319. compatible = "starfive,vic-sec";
  320. reg = <0x0 0x100d0000 0x0 0x20000>,
  321. <0x0 0x11800234 0x0 0xc>;
  322. reg-names = "secmem", "secclk";
  323. interrupts = <31>;
  324. clocks = <&clkgen JH7100_CLK_SEC_AHB>;
  325. };
  326. /* gmac device configuration */
  327. stmmac_axi_setup: stmmac-axi-config {
  328. snps,wr_osr_lmt = <0xf>;
  329. snps,rd_osr_lmt = <0xf>;
  330. snps,blen = <256 128 64 32 0 0 0>;
  331. };
  332. gmac: ethernet@10020000 {
  333. compatible = "snps,dwmac";
  334. reg = <0x0 0x10020000 0x0 0x10000>;
  335. interrupts = <6 7>;
  336. interrupt-names = "macirq", "eth_wake_irq";
  337. max-frame-size = <9000>;
  338. phy-mode = "rgmii-txid";
  339. snps,multicast-filter-bins = <256>;
  340. snps,perfect-filter-entries = <128>;
  341. rx-fifo-depth = <32768>;
  342. tx-fifo-depth = <16384>;
  343. clocks = <&clkgen JH7100_CLK_GMAC_AHB>,
  344. <&clkgen JH7100_CLK_GMAC_AHB>,
  345. <&clkgen JH7100_CLK_GMAC_PTP_REF>;
  346. clock-names = "stmmaceth", "pclk", "ptp_ref";
  347. snps,fixed-burst;
  348. snps,no-pbl-x8 = <1>;
  349. /*snps,force_sf_dma_mode;*/
  350. snps,force_thresh_dma_mode;
  351. snps,axi-config = <&stmmac_axi_setup>;
  352. };
  353. nvdla@11940000 {
  354. compatible = "nvidia,nvdla_os_initial";
  355. interrupts = <22>;
  356. memory-region = <&nvdla_reserved>;
  357. reg = <0x0 0x11940000 0x0 0x40000>;
  358. status = "okay";
  359. };
  360. jpu: coadj12@11900000 {
  361. compatible = "cm,codaj12-jpu-1";
  362. reg = <0x0 0x11900000 0x0 0x300>;
  363. memory-region = <&jpu_reserved>;
  364. interrupts = <24>;
  365. clocks = <&clkgen JH7100_CLK_JPEG_APB>;
  366. clock-names = "jpege";
  367. reg-names = "control";
  368. status = "okay";
  369. };
  370. vpu_dec: vpu_dec@118f0000 {
  371. compatible = "c&m,cm511-vpu";
  372. reg = <0 0x118f0000 0 0x10000>;
  373. //memory-region = <&vpu_reserved>;
  374. interrupts = <23>;
  375. clocks = <&clkgen JH7100_CLK_VP6_CORE>;
  376. clock-names = "vcodec";
  377. status = "okay";
  378. };
  379. vpu_enc: vpu_enc@118e0000 {
  380. compatible = "cm,cm521-vpu";
  381. reg = <0x0 0x118e0000 0x0 0x4000>;
  382. interrupts = <26>;
  383. clocks = <&clkgen JH7100_CLK_VP6_CORE>;
  384. clock-names = "vcodec";
  385. reg-names = "control";
  386. };
  387. ptc: pwm@12490000 {
  388. compatible = "starfive,pwm0";
  389. reg = <0x0 0x12490000 0x0 0x10000>;
  390. reg-names = "control";
  391. sifive,approx-period = <100000000>;
  392. clocks = <&clkgen JH7100_CLK_PWM_APB>;
  393. #pwm-cells = <3>;
  394. sifive,npwm = <8>;
  395. status = "disabled";
  396. };
  397. qspi: spi@11860000 {
  398. compatible = "cadence,qspi","cdns,qspi-nor";
  399. #address-cells = <1>;
  400. #size-cells = <0>;
  401. reg = <0x0 0x11860000 0x0 0x10000>,
  402. <0x0 0x20000000 0x0 0x20000000>;
  403. interrupts = <3>;
  404. clocks = <&clkgen JH7100_CLK_QSPI_AHB>;
  405. cdns,fifo-depth = <256>;
  406. cdns,fifo-width = <4>;
  407. cdns,trigger-address = <0x0>;
  408. status = "okay";
  409. spi-max-frequency = <250000000>;
  410. };
  411. spi0: spi@11890000 {
  412. compatible = "snps,dw-apb-ssi";
  413. #address-cells = <1>;
  414. #size-cells = <0>;
  415. interrupts = <94>;
  416. reg = <0x0 0x11890000 0x0 0x10000>;
  417. clocks = <&clkgen JH7100_CLK_SPI0_CORE>,
  418. <&clkgen JH7100_CLK_SPI0_APB>;
  419. clock-names = "ssi_clk", "pclk";
  420. status = "disabled";
  421. };
  422. spi1: spi@118a0000 {
  423. compatible = "snps,dw-apb-ssi";
  424. #address-cells = <1>;
  425. #size-cells = <0>;
  426. interrupts = <95>;
  427. reg = <0x0 0x118a0000 0x0 0x10000>;
  428. clocks = <&clkgen JH7100_CLK_SPI1_CORE>,
  429. <&clkgen JH7100_CLK_SPI1_APB>;
  430. clock-names = "ssi_clk", "pclk";
  431. status = "disabled";
  432. };
  433. spi2: spi@12410000 {
  434. compatible = "snps,dw-apb-ssi";
  435. #address-cells = <1>;
  436. #size-cells = <0>;
  437. interrupts = <70>;
  438. reg = <0x0 0x12410000 0x0 0x10000>;
  439. clocks = <&clkgen JH7100_CLK_SPI2_CORE>,
  440. <&clkgen JH7100_CLK_SPI2_APB>;
  441. clock-names = "ssi_clk", "pclk";
  442. status = "disabled";
  443. };
  444. spi3: spi@12420000 {
  445. compatible = "snps,dw-apb-ssi";
  446. #address-cells = <1>;
  447. #size-cells = <0>;
  448. interrupts = <71>;
  449. reg = <0x0 0x12420000 0x0 0x10000>;
  450. clocks = <&clkgen JH7100_CLK_SPI3_CORE>,
  451. <&clkgen JH7100_CLK_SPI3_APB>;
  452. clock-names = "ssi_clk", "pclk";
  453. status = "disabled";
  454. };
  455. xrp@f0000000 {
  456. compatible = "cdns,xrp";
  457. reg = <0x0 0xf0000000 0x0 0x01ffffff>,
  458. <0x10 0x72000000 0x0 0x00001000>,
  459. <0x10 0x72001000 0x0 0x00fff000>,
  460. <0x0 0x124b0000 0x0 0x00010000>;
  461. clocks = <&clkgen JH7100_CLK_VP6_CORE>;
  462. firmware-name = "vp6_elf";
  463. dsp-irq = <19 20>;
  464. dsp-irq-src = <0x20 0x21>;
  465. intc-irq-mode = <1>;
  466. intc-irq = <0 1>;
  467. interrupts = <27 28>;
  468. #address-cells = <1>;
  469. #size-cells = <1>;
  470. ranges = <0x40000000 0x0 0x40000000 0x01000000>,
  471. <0xb0000000 0x10 0x70000000 0x3000000>;
  472. dsp@0 {
  473. };
  474. };
  475. sdio0: mmc@10000000 {
  476. compatible = "snps,dw-mshc";
  477. reg = <0x0 0x10000000 0x0 0x10000>;
  478. interrupts = <4>;
  479. clocks = <&clkgen JH7100_CLK_SDIO0_AHB>,
  480. <&clkgen JH7100_CLK_SDIO0_CCLKINT>;
  481. clock-names = "biu", "ciu";
  482. clock-frequency = <100000000>;
  483. data-addr = <0>;
  484. fifo-depth = <32>;
  485. fifo-watermark-aligned;
  486. bus-width = <4>;
  487. max-frequency = <10000000>;
  488. status = "disabled";
  489. };
  490. sdio1: mmc@10010000 {
  491. compatible = "snps,dw-mshc";
  492. reg = <0x0 0x10010000 0x0 0x10000>;
  493. interrupts = <5>;
  494. clocks = <&clkgen JH7100_CLK_SDIO1_AHB>,
  495. <&clkgen JH7100_CLK_SDIO1_CCLKINT>;
  496. clock-names = "biu", "ciu";
  497. clock-frequency = <100000000>;
  498. data-addr = <0>;
  499. fifo-depth = <32>;
  500. fifo-watermark-aligned;
  501. bus-width = <4>;
  502. max-frequency = <50000000>;
  503. status = "disabled";
  504. };
  505. sfivefb: sfivefb@12000000 {
  506. compatible = "starfive,vpp-lcdc";
  507. interrupts = <101>, <103>;
  508. interrupt-names = "lcdc_irq", "vpp1_irq";
  509. reg = <0x0 0x12000000 0x0 0x10000>,
  510. <0x0 0x12100000 0x0 0x10000>,
  511. <0x0 0x12040000 0x0 0x10000>,
  512. <0x0 0x12080000 0x0 0x10000>,
  513. <0x0 0x120c0000 0x0 0x10000>,
  514. <0x0 0x12240000 0x0 0x10000>,
  515. <0x0 0x12250000 0x0 0x10000>,
  516. <0x0 0x12260000 0x0 0x10000>;
  517. reg-names = "lcdc", "dsitx", "vpp0", "vpp1", "vpp2", "clk", "rst", "sys";
  518. memory-region = <&sffb_reserved>;
  519. #if 0 // FIXME uart clocks can't be right for lcdc
  520. clocks = <&clkgen JH7100_CLK_UART>,
  521. <&clkgen JH7100_CLK_APB2>;
  522. #endif
  523. clock-names = "baudclk", "apb_pclk";
  524. ddr-format = <WIN_FMT_RGB565>;/*LCDC win_format*/
  525. status = "disabled";
  526. };
  527. display-subsystem {
  528. compatible = "starfive,display-subsystem";
  529. memory-region = <&sffb_reserved>;
  530. status = "okay";
  531. dma-coherent;
  532. };
  533. display-encoder {
  534. compatible = "starfive,display-encoder";
  535. encoder-type = <2>; //2-TMDS, 3-LVDS, 6-DSI, 8-DPI
  536. status = "okay";
  537. ports {
  538. port@0 {
  539. hdmi_out:endpoint {
  540. remote-endpoint = <&tda998x_0_input>;
  541. //remote-endpoint = <&dsi_out_port>;
  542. };
  543. };
  544. port@1 {
  545. hdmi_input0:endpoint {
  546. remote-endpoint = <&crtc_0_out>;
  547. };
  548. };
  549. };
  550. };
  551. crtc: crtc@12000000 {
  552. compatible = "starfive,jh7100-crtc";
  553. status = "okay";
  554. interrupt-parent = <&plic>;
  555. interrupts = <101>, <103>;
  556. interrupt-names = "lcdc_irq", "vpp1_irq";
  557. reg = <0x0 0x12000000 0x0 0x10000>,
  558. //<0x0 0x12100000 0x0 0x10000>,
  559. <0x0 0x12040000 0x0 0x10000>,
  560. <0x0 0x12080000 0x0 0x10000>,
  561. <0x0 0x120c0000 0x0 0x10000>,
  562. <0x0 0x12240000 0x0 0x10000>,
  563. <0x0 0x12250000 0x0 0x10000>,
  564. <0x0 0x12260000 0x0 0x10000>;
  565. //reg-names = "lcdc", "dsitx", "vpp0", "vpp1", "vpp2", "clk", "rst", "sys";
  566. reg-names = "lcdc", "vpp0", "vpp1", "vpp2", "clk", "rst", "sys";
  567. clocks = <&uartclk>, <&apb2clk>;
  568. clock-names = "baudclk", "apb_pclk";
  569. ddr-format = <WIN_FMT_RGB565>;
  570. #address-cells = <1>;
  571. #size-cells = <0>;
  572. pp1 {
  573. pp-id = <1>;
  574. fifo-out;
  575. //sys-bus-out;
  576. src-format = <COLOR_RGB565>;
  577. src-width = <1920>;
  578. src-height = <1080>;
  579. dst-format = <COLOR_RGB888_ARGB>;
  580. dst-width = <1920>;
  581. dst-height = <1080>;
  582. };
  583. port: port@0 {
  584. reg = <0>;
  585. crtc_0_out: endpoint {
  586. remote-endpoint = <&hdmi_input0>;
  587. };
  588. };
  589. };
  590. mipi_dphy: mipi-dphy@12260000{
  591. compatible = "starfive,jh7100-mipi-dphy-tx";
  592. //reg = <0x0 0x12260000 0x0 0x10000>;
  593. clocks = <&uartclk>, <&apb2clk>;
  594. clock-names = "baudclk", "apb_pclk";
  595. #phy-cells = <0>;
  596. };
  597. mipi_dsi: mipi@12100000 {
  598. compatible = "cdns,dsi";
  599. clocks = <&apb1clk>, <&apb2clk>;
  600. clock-names = "dsi_p_clk", "dsi_sys_clk";
  601. phys = <&mipi_dphy>;
  602. phy-names = "dphy";
  603. status = "okay";
  604. reg = <0x0 0x12100000 0x0 0x10000>;
  605. reg-names = "dsi";
  606. port {
  607. dsi_out_port: endpoint {
  608. remote-endpoint = <&panel_dsi_port>;
  609. };
  610. };
  611. mipi_panel: panel@0 {
  612. //compatible = "";
  613. status = "okay";
  614. };
  615. };
  616. vin_sysctl: vin_sysctl@19800000 {
  617. compatible = "starfive,stf-vin";
  618. reg = <0x0 0x19800000 0x0 0x10000>,
  619. <0x0 0x19810000 0x0 0x10000>,
  620. <0x0 0x19820000 0x0 0x10000>,
  621. <0x0 0x19830000 0x0 0x10000>,
  622. <0x0 0x19840000 0x0 0x10000>,
  623. <0x0 0x19870000 0x0 0x30000>,
  624. <0x0 0x198a0000 0x0 0x30000>,
  625. <0x0 0x11800000 0x0 0x10000>,
  626. <0x0 0x11840000 0x0 0x10000>;
  627. reg-names = "mipi0", "vclk", "vrst", "mipi1", "sctrl",
  628. "isp0", "isp1", "tclk", "trst";
  629. interrupts = <119 109 112>;
  630. memory-region = <&vin_reserved>;
  631. pinctrl-names = "default";
  632. pinctrl-0 = <&dvpsensor_pins>;
  633. status = "okay";
  634. clocks = <&clkgen JH7100_CLK_VIN_SRC>,
  635. <&clkgen JH7100_CLK_ISP0_AXI>,
  636. <&clkgen JH7100_CLK_ISP0NOC_AXI>,
  637. <&clkgen JH7100_CLK_ISPSLV_AXI>,
  638. <&clkgen JH7100_CLK_ISP1_AXI>,
  639. <&clkgen JH7100_CLK_ISP1NOC_AXI>,
  640. <&clkgen JH7100_CLK_VIN_AXI>,
  641. <&clkgen JH7100_CLK_VINNOC_AXI>;
  642. // <&clkgen JH7100_CLK_CSI2RX_APB>,
  643. // <&clkgen JH7100_CLK_MIPI_RX0_PXL_0>,
  644. // <&clkgen JH7100_CLK_MIPI_RX0_PXL_1>,
  645. // <&clkgen JH7100_CLK_MIPI_RX0_PXL_2>,
  646. // <&clkgen JH7100_CLK_MIPI_RX0_PXL_3>,
  647. // <&clkgen JH7100_CLK_MIPI_RX0_SYS>,
  648. // <&clkgen JH7100_CLK_MIPI_RX1_PXL_0>,
  649. // <&clkgen JH7100_CLK_MIPI_RX1_PXL_1>,
  650. // <&clkgen JH7100_CLK_MIPI_RX1_PXL_2>,
  651. // <&clkgen JH7100_CLK_MIPI_RX1_PXL_3>,
  652. // <&clkgen JH7100_CLK_MIPI_RX1_SYS>,
  653. // <&clkgen JH7100_CLK_DPHY_CFGCLK>,
  654. // <&clkgen JH7100_CLK_DPHY_REFCLK>,
  655. // <&clkgen JH7100_CLK_DPHY_TXCLKESC>,
  656. // <&clkgen JH7100_CLK_ISP0_CTRL>,
  657. // <&clkgen JH7100_CLK_ISP0_2X_CTRL>,
  658. // <&clkgen JH7100_CLK_ISP0_MIPI_CTRL>,
  659. // <&clkgen JH7100_CLK_ISP1_CTRL>,
  660. // <&clkgen JH7100_CLK_ISP1_2X_CTRL>,
  661. // <&clkgen JH7100_CLK_ISP1_MIPI_CTRL>;
  662. clock-names = "vin_src",
  663. "isp0_axi",
  664. "isp0noc_axi",
  665. "ispslv_axi",
  666. "isp1_axi",
  667. "isp1noc_axi",
  668. "vin_axi",
  669. "vinnoc_axi";
  670. // "csi2rx_apb_clk",
  671. // "mipirx0_pixel0",
  672. // "mipirx0_pixel1",
  673. // "mipirx0_pixel2",
  674. // "mipirx0_pixel3",
  675. // "mipirx0_sys",
  676. // "mipirx1_pixel0",
  677. // "mipirx1_pixel1",
  678. // "mipirx1_pixel2",
  679. // "mipirx1_pixel3",
  680. // "mipirx1_sys",
  681. // "csidphy_cfgclk",
  682. // "csidphy_regclk",
  683. // "csidphy_txclkesc",
  684. // "isp0_ctrl",
  685. // "isp0_2x_ctrl",
  686. // "isp0_mipi_ctrl",
  687. // "isp1_ctrl",
  688. // "isp1_2x_ctrl",
  689. // "isp1_mipi_ctrl";
  690. ports {
  691. #address-cells = <1>;
  692. #size-cells = <0>;
  693. port@0 {
  694. reg = <0>;
  695. dphy0_out_csi2rx: endpoint {
  696. remote-endpoint = <&csi2rx0_in_dphy>;
  697. clock-lanes = <0>;
  698. data-lanes = <1 2>;
  699. status = "failed";
  700. };
  701. };
  702. //port@1 {
  703. // reg = <1>;
  704. // dphy1_out_csi2rx: endpoint {
  705. // remote-endpoint = <&csi2rx1_in_dphy>;
  706. // clock-lanes = <0>;
  707. // data-lanes = <1 2>;
  708. // status = "failed";
  709. // };
  710. //};
  711. /* TODO: Used for EVB board, comment here for starlight board, remove it later*/
  712. port@2 {
  713. reg = <2>; // dvp sensor
  714. // Parallel bus endpoint
  715. parallel_from_ov5640: endpoint {
  716. remote-endpoint = <&ov5640_to_parallel>;
  717. bus-type = <5>; // Parallel
  718. bus-width = <8>;
  719. data-shift = <2>; // lines 9:2 are used
  720. hsync-active = <1>;
  721. vsync-active = <0>;
  722. pclk-sample = <1>;
  723. status = "failed";
  724. };
  725. };
  726. port@3 {
  727. reg = <2>; //dvp sensor
  728. // Parallel bus endpoint
  729. parallel_from_sc2235: endpoint {
  730. remote-endpoint = <&sc2235_to_parallel>;
  731. bus-type = <5>; // Parallel
  732. bus-width = <8>;
  733. data-shift = <2>; // lines 9:2 are used
  734. hsync-active = <1>;
  735. vsync-active = <1>;
  736. pclk-sample = <1>;
  737. status = "failed";
  738. };
  739. };
  740. port@4 {
  741. reg = <3>; //csi2rx0 sensor
  742. /* CSI2 bus endpoint */
  743. csi2rx0_from_imx219: endpoint {
  744. remote-endpoint = <&imx219_to_csi2rx0>;
  745. bus-type = <4>; /* MIPI CSI-2 D-PHY */
  746. clock-lanes = <0>;
  747. data-lanes = <1 2>;
  748. status = "okay";
  749. };
  750. };
  751. port@5 {
  752. reg = <4>; // csi2rx1 sensor
  753. /* CSI2 bus endpoint */
  754. csi2rx1_from_imx219: endpoint {
  755. remote-endpoint = <&imx219_to_csi2rx1>;
  756. bus-type = <4>; /* MIPI CSI-2 D-PHY */
  757. clock-lanes = <5>;
  758. data-lanes = <3 4>;
  759. lane-polarities = <0 1 0>;
  760. status = "okay";
  761. };
  762. };
  763. };
  764. };
  765. csi2rx: csi-bridge@19800000 {
  766. compatible = "cdns,csi2rx";
  767. reg = <0x0 0x19800000 0x0 0x10000>;
  768. clocks = <&byteclock>, <&byteclock>,
  769. <&coreclock>, <&coreclock>,
  770. <&coreclock>, <&coreclock>;
  771. clock-names = "sys_clk", "p_clk",
  772. "pixel_if0_clk", "pixel_if1_clk",
  773. "pixel_if2_clk", "pixel_if3_clk";
  774. ports {
  775. #address-cells = <1>;
  776. #size-cells = <0>;
  777. port@0 {
  778. reg = <0>;
  779. csi2rx0_in_dphy: endpoint {
  780. remote-endpoint = <&dphy0_out_csi2rx>;
  781. clock-lanes = <0>;
  782. data-lanes = <1 2>;
  783. };
  784. };
  785. };
  786. };
  787. sfctemp: tmon@124a0000 {
  788. compatible = "starfive,jh7100-temp";
  789. reg = <0x0 0x124a0000 0x0 0x10000>;
  790. #thermal-sensor-cells = <0>;
  791. interrupts = <122>;
  792. };
  793. thermal-zones {
  794. cpu-thermal {
  795. polling-delay-passive = <250>;
  796. polling-delay = <15000>;
  797. thermal-sensors = <&sfctemp>;
  798. cooling-maps {
  799. };
  800. trips {
  801. cpu_alert0: cpu_alert0 {
  802. /* milliCelsius */
  803. temperature = <75000>;
  804. hysteresis = <2000>;
  805. type = "passive";
  806. };
  807. cpu_crit: cpu_crit {
  808. /* milliCelsius */
  809. temperature = <90000>;
  810. hysteresis = <2000>;
  811. type = "critical";
  812. };
  813. };
  814. };
  815. };
  816. otp: otp@11810000 {
  817. compatible = "starfive,fu740-otp";
  818. reg = <0x0 0x11810000 0x0 0x10000>;
  819. fuse-count = <0x200>;
  820. clocks = <&clkgen JH7100_CLK_OTP_APB>;
  821. };
  822. i2sadc0: i2sadc0@10400000 {
  823. compatible = "snps,designware-i2sadc0";
  824. reg = <0x0 0x10400000 0x0 0x1000>;
  825. interrupt-parent = <&plic>;
  826. /* interrupts = <59>; */
  827. /* interrupt-names = "rx"; */
  828. clocks = <&apb1clk>;
  829. clock-names = "i2sclk";
  830. #sound-dai-cells = <0>;
  831. dmas = <&dma2p 28>;
  832. dma-names = "rx";
  833. };
  834. i2svad: i2svad@10420000 {
  835. compatible = "sf,sf-i2svad";
  836. reg = <0x0 0x10420000 0x0 0x1000> ;
  837. interrupt-parent = <&plic>;
  838. interrupts = <60>, <61>;
  839. interrupt-names = "spintr", "slintr";
  840. clocks = <&apb1clk>;
  841. clock-names = "i2sclk";
  842. #sound-dai-cells = <0>;
  843. };
  844. i2sdac0: i2sdac0@10450000 {
  845. compatible = "snps,designware-i2sdac0";
  846. reg = <0x0 0x10450000 0x0 0x1000>;
  847. interrupt-parent = <&plic>;
  848. /*interrupts = <64>; */
  849. /*interrupt-names = "tx";*/
  850. clocks = <&apb1clk>;
  851. clock-names = "i2sclk";
  852. #sound-dai-cells = <0>;
  853. dmas = <&dma2p 30>;
  854. dma-names = "tx";
  855. };
  856. i2sdac1: i2sdac1@10460000 {
  857. compatible = "snps,designware-i2sdac1";
  858. reg = <0x0 0x10460000 0x0 0x1000>;
  859. interrupt-parent = <&plic>;
  860. /*interrupts = <66>;*/
  861. /*interrupt-names = "tx";*/
  862. clocks = <&apb1clk>;
  863. clock-names = "i2sclk";
  864. #sound-dai-cells = <0>;
  865. dmas = <&dma2p 31>;
  866. dma-names = "tx";
  867. };
  868. i2sdac16k: i2sdac16k@10470000 {
  869. compatible = "snps,designware-i2sdac16k";
  870. reg = <0x0 0x10470000 0x0 0x1000>;
  871. interrupt-parent = <&plic>;
  872. /* interrupts = <68>; */
  873. /* interrupt-names = "tx"; */
  874. clocks = <&apb1clk>;
  875. clock-names = "i2sclk";
  876. #sound-dai-cells = <0>;
  877. dmas = <&dma2p 29>;
  878. dma-names = "tx";
  879. };
  880. spdif0: spdif0@10430000 {
  881. compatible = "starfive,sf-spdif";
  882. reg = <0x0 0x10430000 0x0 0x1000>;
  883. interrupt-parent = <&plic>;
  884. interrupts = <62>;
  885. interrupt-names = "tx";
  886. clocks = <&audioclk>;
  887. clock-names = "audioclk";
  888. #sound-dai-cells = <0>;
  889. };
  890. pdm: pdm@10410000 {
  891. compatible = "starfive,sf-pdm";
  892. reg = <0x0 0x10410000 0x0 0x1000>, <0x0 0x10480000 0x0 0x1000>;
  893. reg-names = "pdm", "audio-clk";
  894. clocks = <&audioclk>;
  895. clock-names = "audioclk";
  896. #sound-dai-cells = <0>;
  897. };
  898. ac108_mclk: ac108_mclk {
  899. compatible = "fixed-clock";
  900. #clock-cells = <0>;
  901. clock-frequency = <24576000>;
  902. };
  903. wm8960_mclk: wm8960_mclk {
  904. compatible = "fixed-clock";
  905. #clock-cells = <0>;
  906. clock-frequency = <24576000>;
  907. };
  908. spdif_transmitter: spdif_transmitter {
  909. compatible = "linux,spdif-dit";
  910. #sound-dai-cells = <0>;
  911. };
  912. spdif_receiver: spdif_receiver {
  913. compatible = "linux,spdif-dir";
  914. #sound-dai-cells = <0>;
  915. };
  916. pwmdac: pwmdac@10440000 {
  917. compatible = "sf,pwmdac";
  918. reg = <0x0 0x10440000 0x0 0x1000>;
  919. clocks = <&apb1clk>;
  920. dmas = <&dma2p 23>;
  921. dma-names = "tx";
  922. #sound-dai-cells = <0>;
  923. };
  924. pwmdac_codec: pwmdac-transmitter {
  925. compatible = "linux,pwmdac-dit";
  926. #sound-dai-cells = <0>;
  927. };
  928. dmic_codec: dmic_codec {
  929. compatible = "dmic-codec";
  930. #sound-dai-cells = <0>;
  931. };
  932. sound:snd-card{
  933. compatible = "simple-audio-card";
  934. simple-audio-card,name = "Starfive-Multi-Sound-Card";
  935. #address-cells = <1>;
  936. #size-cells = <0>;
  937. /* pwmdac */
  938. simple-audio-card,dai-link@0 {
  939. reg = <0>;
  940. status = "okay";
  941. format = "left_j";
  942. bitclock-master = <&sndcpu0>;
  943. frame-master = <&sndcpu0>;
  944. sndcpu0: cpu {
  945. sound-dai = <&pwmdac>;
  946. };
  947. codec {
  948. sound-dai = <&pwmdac_codec>;
  949. };
  950. };
  951. };
  952. };
  953. };