turris_omnia.c 15 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2017 Marek Behun <marek.behun@nic.cz>
  4. * Copyright (C) 2016 Tomas Hlavacek <tomas.hlavacek@nic.cz>
  5. *
  6. * Derived from the code for
  7. * Marvell/db-88f6820-gp by Stefan Roese <sr@denx.de>
  8. */
  9. #include <common.h>
  10. #include <env.h>
  11. #include <i2c.h>
  12. #include <init.h>
  13. #include <log.h>
  14. #include <miiphy.h>
  15. #include <mtd.h>
  16. #include <net.h>
  17. #include <netdev.h>
  18. #include <asm/global_data.h>
  19. #include <asm/io.h>
  20. #include <asm/arch/cpu.h>
  21. #include <asm/arch/soc.h>
  22. #include <dm/uclass.h>
  23. #include <fdt_support.h>
  24. #include <time.h>
  25. #include <linux/bitops.h>
  26. #include <u-boot/crc.h>
  27. # include <atsha204a-i2c.h>
  28. #include "../drivers/ddr/marvell/a38x/ddr3_init.h"
  29. #include <../serdes/a38x/high_speed_env_spec.h>
  30. DECLARE_GLOBAL_DATA_PTR;
  31. #define OMNIA_SPI_NOR_PATH "/soc/spi@10600/spi-nor@0"
  32. #define OMNIA_I2C_BUS_NAME "i2c@11000->i2cmux@70->i2c@0"
  33. #define OMNIA_I2C_MCU_CHIP_ADDR 0x2a
  34. #define OMNIA_I2C_MCU_CHIP_LEN 1
  35. #define OMNIA_I2C_EEPROM_CHIP_ADDR 0x54
  36. #define OMNIA_I2C_EEPROM_CHIP_LEN 2
  37. #define OMNIA_I2C_EEPROM_MAGIC 0x0341a034
  38. enum mcu_commands {
  39. CMD_GET_STATUS_WORD = 0x01,
  40. CMD_GET_RESET = 0x09,
  41. CMD_WATCHDOG_STATE = 0x0b,
  42. };
  43. enum status_word_bits {
  44. CARD_DET_STSBIT = 0x0010,
  45. MSATA_IND_STSBIT = 0x0020,
  46. };
  47. #define OMNIA_ATSHA204_OTP_VERSION 0
  48. #define OMNIA_ATSHA204_OTP_SERIAL 1
  49. #define OMNIA_ATSHA204_OTP_MAC0 3
  50. #define OMNIA_ATSHA204_OTP_MAC1 4
  51. /*
  52. * Those values and defines are taken from the Marvell U-Boot version
  53. * "u-boot-2013.01-2014_T3.0"
  54. */
  55. #define OMNIA_GPP_OUT_ENA_LOW \
  56. (~(BIT(1) | BIT(4) | BIT(6) | BIT(7) | BIT(8) | BIT(9) | \
  57. BIT(10) | BIT(11) | BIT(19) | BIT(22) | BIT(23) | BIT(25) | \
  58. BIT(26) | BIT(27) | BIT(29) | BIT(30) | BIT(31)))
  59. #define OMNIA_GPP_OUT_ENA_MID \
  60. (~(BIT(0) | BIT(1) | BIT(2) | BIT(3) | BIT(4) | BIT(15) | \
  61. BIT(16) | BIT(17) | BIT(18)))
  62. #define OMNIA_GPP_OUT_VAL_LOW 0x0
  63. #define OMNIA_GPP_OUT_VAL_MID 0x0
  64. #define OMNIA_GPP_POL_LOW 0x0
  65. #define OMNIA_GPP_POL_MID 0x0
  66. static struct serdes_map board_serdes_map_pex[] = {
  67. {PEX0, SERDES_SPEED_5_GBPS, PEX_ROOT_COMPLEX_X1, 0, 0},
  68. {USB3_HOST0, SERDES_SPEED_5_GBPS, SERDES_DEFAULT_MODE, 0, 0},
  69. {PEX1, SERDES_SPEED_5_GBPS, PEX_ROOT_COMPLEX_X1, 0, 0},
  70. {USB3_HOST1, SERDES_SPEED_5_GBPS, SERDES_DEFAULT_MODE, 0, 0},
  71. {PEX2, SERDES_SPEED_5_GBPS, PEX_ROOT_COMPLEX_X1, 0, 0},
  72. {SGMII2, SERDES_SPEED_1_25_GBPS, SERDES_DEFAULT_MODE, 0, 0}
  73. };
  74. static struct serdes_map board_serdes_map_sata[] = {
  75. {SATA0, SERDES_SPEED_6_GBPS, SERDES_DEFAULT_MODE, 0, 0},
  76. {USB3_HOST0, SERDES_SPEED_5_GBPS, SERDES_DEFAULT_MODE, 0, 0},
  77. {PEX1, SERDES_SPEED_5_GBPS, PEX_ROOT_COMPLEX_X1, 0, 0},
  78. {USB3_HOST1, SERDES_SPEED_5_GBPS, SERDES_DEFAULT_MODE, 0, 0},
  79. {PEX2, SERDES_SPEED_5_GBPS, PEX_ROOT_COMPLEX_X1, 0, 0},
  80. {SGMII2, SERDES_SPEED_1_25_GBPS, SERDES_DEFAULT_MODE, 0, 0}
  81. };
  82. static struct udevice *omnia_get_i2c_chip(const char *name, uint addr,
  83. uint offset_len)
  84. {
  85. struct udevice *bus, *dev;
  86. int ret;
  87. ret = uclass_get_device_by_name(UCLASS_I2C, OMNIA_I2C_BUS_NAME, &bus);
  88. if (ret) {
  89. printf("Cannot get I2C bus %s: uclass_get_device_by_name failed: %i\n",
  90. OMNIA_I2C_BUS_NAME, ret);
  91. return NULL;
  92. }
  93. ret = i2c_get_chip(bus, addr, offset_len, &dev);
  94. if (ret) {
  95. printf("Cannot get %s I2C chip: i2c_get_chip failed: %i\n",
  96. name, ret);
  97. return NULL;
  98. }
  99. return dev;
  100. }
  101. static int omnia_mcu_read(u8 cmd, void *buf, int len)
  102. {
  103. struct udevice *chip;
  104. chip = omnia_get_i2c_chip("MCU", OMNIA_I2C_MCU_CHIP_ADDR,
  105. OMNIA_I2C_MCU_CHIP_LEN);
  106. if (!chip)
  107. return -ENODEV;
  108. return dm_i2c_read(chip, cmd, buf, len);
  109. }
  110. static int omnia_mcu_write(u8 cmd, const void *buf, int len)
  111. {
  112. struct udevice *chip;
  113. chip = omnia_get_i2c_chip("MCU", OMNIA_I2C_MCU_CHIP_ADDR,
  114. OMNIA_I2C_MCU_CHIP_LEN);
  115. if (!chip)
  116. return -ENODEV;
  117. return dm_i2c_write(chip, cmd, buf, len);
  118. }
  119. static bool disable_mcu_watchdog(void)
  120. {
  121. int ret;
  122. puts("Disabling MCU watchdog... ");
  123. ret = omnia_mcu_write(CMD_WATCHDOG_STATE, "\x00", 1);
  124. if (ret) {
  125. printf("omnia_mcu_write failed: %i\n", ret);
  126. return false;
  127. }
  128. puts("disabled\n");
  129. return true;
  130. }
  131. static bool omnia_detect_sata(void)
  132. {
  133. int ret;
  134. u16 stsword;
  135. puts("MiniPCIe/mSATA card detection... ");
  136. ret = omnia_mcu_read(CMD_GET_STATUS_WORD, &stsword, sizeof(stsword));
  137. if (ret) {
  138. printf("omnia_mcu_read failed: %i, defaulting to MiniPCIe card\n",
  139. ret);
  140. return false;
  141. }
  142. if (!(stsword & CARD_DET_STSBIT)) {
  143. puts("none\n");
  144. return false;
  145. }
  146. if (stsword & MSATA_IND_STSBIT)
  147. puts("mSATA\n");
  148. else
  149. puts("MiniPCIe\n");
  150. return stsword & MSATA_IND_STSBIT ? true : false;
  151. }
  152. int hws_board_topology_load(struct serdes_map **serdes_map_array, u8 *count)
  153. {
  154. if (omnia_detect_sata()) {
  155. *serdes_map_array = board_serdes_map_sata;
  156. *count = ARRAY_SIZE(board_serdes_map_sata);
  157. } else {
  158. *serdes_map_array = board_serdes_map_pex;
  159. *count = ARRAY_SIZE(board_serdes_map_pex);
  160. }
  161. return 0;
  162. }
  163. struct omnia_eeprom {
  164. u32 magic;
  165. u32 ramsize;
  166. char region[4];
  167. u32 crc;
  168. };
  169. static bool omnia_read_eeprom(struct omnia_eeprom *oep)
  170. {
  171. struct udevice *chip;
  172. u32 crc;
  173. int ret;
  174. chip = omnia_get_i2c_chip("EEPROM", OMNIA_I2C_EEPROM_CHIP_ADDR,
  175. OMNIA_I2C_EEPROM_CHIP_LEN);
  176. if (!chip)
  177. return false;
  178. ret = dm_i2c_read(chip, 0, (void *)oep, sizeof(*oep));
  179. if (ret) {
  180. printf("dm_i2c_read failed: %i, cannot read EEPROM\n", ret);
  181. return false;
  182. }
  183. if (oep->magic != OMNIA_I2C_EEPROM_MAGIC) {
  184. printf("bad EEPROM magic number (%08x, should be %08x)\n",
  185. oep->magic, OMNIA_I2C_EEPROM_MAGIC);
  186. return false;
  187. }
  188. crc = crc32(0, (void *)oep, sizeof(*oep) - 4);
  189. if (crc != oep->crc) {
  190. printf("bad EEPROM CRC (stored %08x, computed %08x)\n",
  191. oep->crc, crc);
  192. return false;
  193. }
  194. return true;
  195. }
  196. static int omnia_get_ram_size_gb(void)
  197. {
  198. static int ram_size;
  199. struct omnia_eeprom oep;
  200. if (!ram_size) {
  201. /* Get the board config from EEPROM */
  202. if (omnia_read_eeprom(&oep)) {
  203. debug("Memory config in EEPROM: 0x%02x\n", oep.ramsize);
  204. if (oep.ramsize == 0x2)
  205. ram_size = 2;
  206. else
  207. ram_size = 1;
  208. } else {
  209. /* Hardcoded fallback */
  210. puts("Memory config from EEPROM read failed!\n");
  211. puts("Falling back to default 1 GiB!\n");
  212. ram_size = 1;
  213. }
  214. }
  215. return ram_size;
  216. }
  217. /*
  218. * Define the DDR layout / topology here in the board file. This will
  219. * be used by the DDR3 init code in the SPL U-Boot version to configure
  220. * the DDR3 controller.
  221. */
  222. static struct mv_ddr_topology_map board_topology_map_1g = {
  223. DEBUG_LEVEL_ERROR,
  224. 0x1, /* active interfaces */
  225. /* cs_mask, mirror, dqs_swap, ck_swap X PUPs */
  226. { { { {0x1, 0, 0, 0},
  227. {0x1, 0, 0, 0},
  228. {0x1, 0, 0, 0},
  229. {0x1, 0, 0, 0},
  230. {0x1, 0, 0, 0} },
  231. SPEED_BIN_DDR_1600K, /* speed_bin */
  232. MV_DDR_DEV_WIDTH_16BIT, /* memory_width */
  233. MV_DDR_DIE_CAP_4GBIT, /* mem_size */
  234. MV_DDR_FREQ_800, /* frequency */
  235. 0, 0, /* cas_wl cas_l */
  236. MV_DDR_TEMP_NORMAL, /* temperature */
  237. MV_DDR_TIM_2T} }, /* timing */
  238. BUS_MASK_32BIT, /* Busses mask */
  239. MV_DDR_CFG_DEFAULT, /* ddr configuration data source */
  240. NOT_COMBINED, /* ddr twin-die combined */
  241. { {0} }, /* raw spd data */
  242. {0} /* timing parameters */
  243. };
  244. static struct mv_ddr_topology_map board_topology_map_2g = {
  245. DEBUG_LEVEL_ERROR,
  246. 0x1, /* active interfaces */
  247. /* cs_mask, mirror, dqs_swap, ck_swap X PUPs */
  248. { { { {0x1, 0, 0, 0},
  249. {0x1, 0, 0, 0},
  250. {0x1, 0, 0, 0},
  251. {0x1, 0, 0, 0},
  252. {0x1, 0, 0, 0} },
  253. SPEED_BIN_DDR_1600K, /* speed_bin */
  254. MV_DDR_DEV_WIDTH_16BIT, /* memory_width */
  255. MV_DDR_DIE_CAP_8GBIT, /* mem_size */
  256. MV_DDR_FREQ_800, /* frequency */
  257. 0, 0, /* cas_wl cas_l */
  258. MV_DDR_TEMP_NORMAL, /* temperature */
  259. MV_DDR_TIM_2T} }, /* timing */
  260. BUS_MASK_32BIT, /* Busses mask */
  261. MV_DDR_CFG_DEFAULT, /* ddr configuration data source */
  262. NOT_COMBINED, /* ddr twin-die combined */
  263. { {0} }, /* raw spd data */
  264. {0} /* timing parameters */
  265. };
  266. struct mv_ddr_topology_map *mv_ddr_topology_map_get(void)
  267. {
  268. if (omnia_get_ram_size_gb() == 2)
  269. return &board_topology_map_2g;
  270. else
  271. return &board_topology_map_1g;
  272. }
  273. static int set_regdomain(void)
  274. {
  275. struct omnia_eeprom oep;
  276. char rd[3] = {' ', ' ', 0};
  277. if (omnia_read_eeprom(&oep))
  278. memcpy(rd, &oep.region, 2);
  279. else
  280. puts("EEPROM regdomain read failed.\n");
  281. printf("Regdomain set to %s\n", rd);
  282. return env_set("regdomain", rd);
  283. }
  284. static void handle_reset_button(void)
  285. {
  286. const char * const vars[1] = { "bootcmd_rescue", };
  287. int ret;
  288. u8 reset_status;
  289. /*
  290. * Ensure that bootcmd_rescue has always stock value, so that running
  291. * run bootcmd_rescue
  292. * always works correctly.
  293. */
  294. env_set_default_vars(1, (char * const *)vars, 0);
  295. ret = omnia_mcu_read(CMD_GET_RESET, &reset_status, 1);
  296. if (ret) {
  297. printf("omnia_mcu_read failed: %i, reset status unknown!\n",
  298. ret);
  299. return;
  300. }
  301. env_set_ulong("omnia_reset", reset_status);
  302. if (reset_status) {
  303. const char * const vars[2] = {
  304. "bootcmd",
  305. "distro_bootcmd",
  306. };
  307. /*
  308. * Set the above envs to their default values, in case the user
  309. * managed to break them.
  310. */
  311. env_set_default_vars(2, (char * const *)vars, 0);
  312. /* Ensure bootcmd_rescue is used by distroboot */
  313. env_set("boot_targets", "rescue");
  314. printf("RESET button was pressed, overwriting bootcmd!\n");
  315. } else {
  316. /*
  317. * In case the user somehow managed to save environment with
  318. * boot_targets=rescue, reset boot_targets to default value.
  319. * This could happen in subsequent commands if bootcmd_rescue
  320. * failed.
  321. */
  322. if (!strcmp(env_get("boot_targets"), "rescue")) {
  323. const char * const vars[1] = {
  324. "boot_targets",
  325. };
  326. env_set_default_vars(1, (char * const *)vars, 0);
  327. }
  328. }
  329. }
  330. int board_early_init_f(void)
  331. {
  332. /* Configure MPP */
  333. writel(0x11111111, MVEBU_MPP_BASE + 0x00);
  334. writel(0x11111111, MVEBU_MPP_BASE + 0x04);
  335. writel(0x11244011, MVEBU_MPP_BASE + 0x08);
  336. writel(0x22222111, MVEBU_MPP_BASE + 0x0c);
  337. writel(0x22200002, MVEBU_MPP_BASE + 0x10);
  338. writel(0x30042022, MVEBU_MPP_BASE + 0x14);
  339. writel(0x55550555, MVEBU_MPP_BASE + 0x18);
  340. writel(0x00005550, MVEBU_MPP_BASE + 0x1c);
  341. /* Set GPP Out value */
  342. writel(OMNIA_GPP_OUT_VAL_LOW, MVEBU_GPIO0_BASE + 0x00);
  343. writel(OMNIA_GPP_OUT_VAL_MID, MVEBU_GPIO1_BASE + 0x00);
  344. /* Set GPP Polarity */
  345. writel(OMNIA_GPP_POL_LOW, MVEBU_GPIO0_BASE + 0x0c);
  346. writel(OMNIA_GPP_POL_MID, MVEBU_GPIO1_BASE + 0x0c);
  347. /* Set GPP Out Enable */
  348. writel(OMNIA_GPP_OUT_ENA_LOW, MVEBU_GPIO0_BASE + 0x04);
  349. writel(OMNIA_GPP_OUT_ENA_MID, MVEBU_GPIO1_BASE + 0x04);
  350. return 0;
  351. }
  352. void spl_board_init(void)
  353. {
  354. /*
  355. * If booting from UART, disable MCU watchdog in SPL, since uploading
  356. * U-Boot proper can take too much time and trigger it.
  357. */
  358. if (get_boot_device() == BOOT_DEVICE_UART)
  359. disable_mcu_watchdog();
  360. }
  361. int board_init(void)
  362. {
  363. /* address of boot parameters */
  364. gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
  365. return 0;
  366. }
  367. int board_late_init(void)
  368. {
  369. /*
  370. * If not booting from UART, MCU watchdog was not disabled in SPL,
  371. * disable it now.
  372. */
  373. if (get_boot_device() != BOOT_DEVICE_UART)
  374. disable_mcu_watchdog();
  375. set_regdomain();
  376. handle_reset_button();
  377. pci_init();
  378. return 0;
  379. }
  380. static struct udevice *get_atsha204a_dev(void)
  381. {
  382. static struct udevice *dev;
  383. if (dev)
  384. return dev;
  385. if (uclass_get_device_by_name(UCLASS_MISC, "atsha204a@64", &dev)) {
  386. puts("Cannot find ATSHA204A on I2C bus!\n");
  387. dev = NULL;
  388. }
  389. return dev;
  390. }
  391. int checkboard(void)
  392. {
  393. u32 version_num, serial_num;
  394. int err = 1;
  395. struct udevice *dev = get_atsha204a_dev();
  396. if (dev) {
  397. err = atsha204a_wakeup(dev);
  398. if (err)
  399. goto out;
  400. err = atsha204a_read(dev, ATSHA204A_ZONE_OTP, false,
  401. OMNIA_ATSHA204_OTP_VERSION,
  402. (u8 *)&version_num);
  403. if (err)
  404. goto out;
  405. err = atsha204a_read(dev, ATSHA204A_ZONE_OTP, false,
  406. OMNIA_ATSHA204_OTP_SERIAL,
  407. (u8 *)&serial_num);
  408. if (err)
  409. goto out;
  410. atsha204a_sleep(dev);
  411. }
  412. out:
  413. printf("Turris Omnia:\n");
  414. printf(" RAM size: %i MiB\n", omnia_get_ram_size_gb() * 1024);
  415. if (err)
  416. printf(" Serial Number: unknown\n");
  417. else
  418. printf(" Serial Number: %08X%08X\n", be32_to_cpu(version_num),
  419. be32_to_cpu(serial_num));
  420. return 0;
  421. }
  422. static void increment_mac(u8 *mac)
  423. {
  424. int i;
  425. for (i = 5; i >= 3; i--) {
  426. mac[i] += 1;
  427. if (mac[i])
  428. break;
  429. }
  430. }
  431. int misc_init_r(void)
  432. {
  433. int err;
  434. struct udevice *dev = get_atsha204a_dev();
  435. u8 mac0[4], mac1[4], mac[6];
  436. if (!dev)
  437. goto out;
  438. err = atsha204a_wakeup(dev);
  439. if (err)
  440. goto out;
  441. err = atsha204a_read(dev, ATSHA204A_ZONE_OTP, false,
  442. OMNIA_ATSHA204_OTP_MAC0, mac0);
  443. if (err)
  444. goto out;
  445. err = atsha204a_read(dev, ATSHA204A_ZONE_OTP, false,
  446. OMNIA_ATSHA204_OTP_MAC1, mac1);
  447. if (err)
  448. goto out;
  449. atsha204a_sleep(dev);
  450. mac[0] = mac0[1];
  451. mac[1] = mac0[2];
  452. mac[2] = mac0[3];
  453. mac[3] = mac1[1];
  454. mac[4] = mac1[2];
  455. mac[5] = mac1[3];
  456. if (is_valid_ethaddr(mac))
  457. eth_env_set_enetaddr("eth1addr", mac);
  458. increment_mac(mac);
  459. if (is_valid_ethaddr(mac))
  460. eth_env_set_enetaddr("eth2addr", mac);
  461. increment_mac(mac);
  462. if (is_valid_ethaddr(mac))
  463. eth_env_set_enetaddr("ethaddr", mac);
  464. out:
  465. return 0;
  466. }
  467. #if defined(CONFIG_OF_BOARD_SETUP)
  468. /*
  469. * I plan to generalize this function and move it to common/fdt_support.c.
  470. * This will require some more work on multiple boards, though, so for now leave
  471. * it here.
  472. */
  473. static bool fixup_mtd_partitions(void *blob, int offset, struct mtd_info *mtd)
  474. {
  475. struct mtd_info *slave;
  476. int parts;
  477. parts = fdt_subnode_offset(blob, offset, "partitions");
  478. if (parts < 0)
  479. return false;
  480. if (fdt_del_node(blob, parts) < 0)
  481. return false;
  482. parts = fdt_add_subnode(blob, offset, "partitions");
  483. if (parts < 0)
  484. return false;
  485. if (fdt_setprop_u32(blob, parts, "#address-cells", 1) < 0)
  486. return false;
  487. if (fdt_setprop_u32(blob, parts, "#size-cells", 1) < 0)
  488. return false;
  489. if (fdt_setprop_string(blob, parts, "compatible",
  490. "fixed-partitions") < 0)
  491. return false;
  492. mtd_probe_devices();
  493. list_for_each_entry(slave, &mtd->partitions, node) {
  494. char name[32];
  495. int part;
  496. snprintf(name, sizeof(name), "partition@%llx", slave->offset);
  497. part = fdt_add_subnode(blob, parts, name);
  498. if (part < 0)
  499. return false;
  500. if (fdt_setprop_u32(blob, part, "reg", slave->offset) < 0)
  501. return false;
  502. if (fdt_appendprop_u32(blob, part, "reg", slave->size) < 0)
  503. return false;
  504. if (fdt_setprop_string(blob, part, "label", slave->name) < 0)
  505. return false;
  506. if (!(slave->flags & MTD_WRITEABLE))
  507. if (fdt_setprop_empty(blob, part, "read-only") < 0)
  508. return false;
  509. if (slave->flags & MTD_POWERUP_LOCK)
  510. if (fdt_setprop_empty(blob, part, "lock") < 0)
  511. return false;
  512. }
  513. return true;
  514. }
  515. int ft_board_setup(void *blob, struct bd_info *bd)
  516. {
  517. struct mtd_info *mtd;
  518. int node;
  519. mtd = get_mtd_device_nm(OMNIA_SPI_NOR_PATH);
  520. if (IS_ERR_OR_NULL(mtd))
  521. goto fail;
  522. node = fdt_path_offset(blob, OMNIA_SPI_NOR_PATH);
  523. if (node < 0)
  524. goto fail;
  525. if (!fixup_mtd_partitions(blob, node, mtd))
  526. goto fail;
  527. put_mtd_device(mtd);
  528. return 0;
  529. fail:
  530. printf("Failed fixing SPI NOR partitions!\n");
  531. if (!IS_ERR_OR_NULL(mtd))
  532. put_mtd_device(mtd);
  533. return 0;
  534. }
  535. #endif