kirkwood_spi.c 9.7 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2009
  4. * Marvell Semiconductor <www.marvell.com>
  5. * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
  6. *
  7. * Derived from drivers/spi/mpc8xxx_spi.c
  8. */
  9. #include <common.h>
  10. #include <dm.h>
  11. #include <log.h>
  12. #include <malloc.h>
  13. #include <spi.h>
  14. #include <asm/io.h>
  15. #include <asm/arch/soc.h>
  16. #ifdef CONFIG_ARCH_KIRKWOOD
  17. #include <asm/arch/mpp.h>
  18. #endif
  19. #include <asm/arch-mvebu/spi.h>
  20. static void _spi_cs_activate(struct kwspi_registers *reg)
  21. {
  22. setbits_le32(&reg->ctrl, KWSPI_CSN_ACT);
  23. }
  24. static void _spi_cs_deactivate(struct kwspi_registers *reg)
  25. {
  26. clrbits_le32(&reg->ctrl, KWSPI_CSN_ACT);
  27. }
  28. static int _spi_xfer(struct kwspi_registers *reg, unsigned int bitlen,
  29. const void *dout, void *din, unsigned long flags)
  30. {
  31. unsigned int tmpdout, tmpdin;
  32. int tm, isread = 0;
  33. debug("spi_xfer: dout %p din %p bitlen %u\n", dout, din, bitlen);
  34. if (flags & SPI_XFER_BEGIN)
  35. _spi_cs_activate(reg);
  36. /*
  37. * handle data in 8-bit chunks
  38. * TBD: 2byte xfer mode to be enabled
  39. */
  40. clrsetbits_le32(&reg->cfg, KWSPI_XFERLEN_MASK, KWSPI_XFERLEN_1BYTE);
  41. while (bitlen > 4) {
  42. debug("loopstart bitlen %d\n", bitlen);
  43. tmpdout = 0;
  44. /* Shift data so it's msb-justified */
  45. if (dout)
  46. tmpdout = *(u32 *)dout & 0xff;
  47. clrbits_le32(&reg->irq_cause, KWSPI_SMEMRDIRQ);
  48. writel(tmpdout, &reg->dout); /* Write the data out */
  49. debug("*** spi_xfer: ... %08x written, bitlen %d\n",
  50. tmpdout, bitlen);
  51. /*
  52. * Wait for SPI transmit to get out
  53. * or time out (1 second = 1000 ms)
  54. * The NE event must be read and cleared first
  55. */
  56. for (tm = 0, isread = 0; tm < KWSPI_TIMEOUT; ++tm) {
  57. if (readl(&reg->irq_cause) & KWSPI_SMEMRDIRQ) {
  58. isread = 1;
  59. tmpdin = readl(&reg->din);
  60. debug("spi_xfer: din %p..%08x read\n",
  61. din, tmpdin);
  62. if (din) {
  63. *((u8 *)din) = (u8)tmpdin;
  64. din += 1;
  65. }
  66. if (dout)
  67. dout += 1;
  68. bitlen -= 8;
  69. }
  70. if (isread)
  71. break;
  72. }
  73. if (tm >= KWSPI_TIMEOUT)
  74. printf("*** spi_xfer: Time out during SPI transfer\n");
  75. debug("loopend bitlen %d\n", bitlen);
  76. }
  77. if (flags & SPI_XFER_END)
  78. _spi_cs_deactivate(reg);
  79. return 0;
  80. }
  81. #ifndef CONFIG_DM_SPI
  82. static struct kwspi_registers *spireg =
  83. (struct kwspi_registers *)MVEBU_SPI_BASE;
  84. #ifdef CONFIG_ARCH_KIRKWOOD
  85. static u32 cs_spi_mpp_back[2];
  86. #endif
  87. struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
  88. unsigned int max_hz, unsigned int mode)
  89. {
  90. struct spi_slave *slave;
  91. u32 data;
  92. #ifdef CONFIG_ARCH_KIRKWOOD
  93. static const u32 kwspi_mpp_config[2][2] = {
  94. { MPP0_SPI_SCn, 0 }, /* if cs == 0 */
  95. { MPP7_SPI_SCn, 0 } /* if cs != 0 */
  96. };
  97. #endif
  98. if (!spi_cs_is_valid(bus, cs))
  99. return NULL;
  100. slave = spi_alloc_slave_base(bus, cs);
  101. if (!slave)
  102. return NULL;
  103. writel(KWSPI_SMEMRDY, &spireg->ctrl);
  104. /* calculate spi clock prescaller using max_hz */
  105. data = ((CONFIG_SYS_TCLK / 2) / max_hz) + 0x10;
  106. data = data < KWSPI_CLKPRESCL_MIN ? KWSPI_CLKPRESCL_MIN : data;
  107. data = data > KWSPI_CLKPRESCL_MASK ? KWSPI_CLKPRESCL_MASK : data;
  108. /* program spi clock prescaller using max_hz */
  109. writel(KWSPI_ADRLEN_3BYTE | data, &spireg->cfg);
  110. debug("data = 0x%08x\n", data);
  111. writel(KWSPI_SMEMRDIRQ, &spireg->irq_cause);
  112. writel(KWSPI_IRQMASK, &spireg->irq_mask);
  113. #ifdef CONFIG_ARCH_KIRKWOOD
  114. /* program mpp registers to select SPI_CSn */
  115. kirkwood_mpp_conf(kwspi_mpp_config[cs ? 1 : 0], cs_spi_mpp_back);
  116. #endif
  117. return slave;
  118. }
  119. void spi_free_slave(struct spi_slave *slave)
  120. {
  121. #ifdef CONFIG_ARCH_KIRKWOOD
  122. kirkwood_mpp_conf(cs_spi_mpp_back, NULL);
  123. #endif
  124. free(slave);
  125. }
  126. __attribute__((weak)) int board_spi_claim_bus(struct spi_slave *slave)
  127. {
  128. return 0;
  129. }
  130. int spi_claim_bus(struct spi_slave *slave)
  131. {
  132. return board_spi_claim_bus(slave);
  133. }
  134. __attribute__((weak)) void board_spi_release_bus(struct spi_slave *slave)
  135. {
  136. }
  137. void spi_release_bus(struct spi_slave *slave)
  138. {
  139. board_spi_release_bus(slave);
  140. }
  141. #ifndef CONFIG_SPI_CS_IS_VALID
  142. /*
  143. * you can define this function board specific
  144. * define above CONFIG in board specific config file and
  145. * provide the function in board specific src file
  146. */
  147. int spi_cs_is_valid(unsigned int bus, unsigned int cs)
  148. {
  149. return bus == 0 && (cs == 0 || cs == 1);
  150. }
  151. #endif
  152. void spi_cs_activate(struct spi_slave *slave)
  153. {
  154. _spi_cs_activate(spireg);
  155. }
  156. void spi_cs_deactivate(struct spi_slave *slave)
  157. {
  158. _spi_cs_deactivate(spireg);
  159. }
  160. int spi_xfer(struct spi_slave *slave, unsigned int bitlen,
  161. const void *dout, void *din, unsigned long flags)
  162. {
  163. return _spi_xfer(spireg, bitlen, dout, din, flags);
  164. }
  165. #else
  166. /* Here now the DM part */
  167. struct mvebu_spi_dev {
  168. bool is_errata_50mhz_ac;
  169. };
  170. struct mvebu_spi_platdata {
  171. struct kwspi_registers *spireg;
  172. bool is_errata_50mhz_ac;
  173. };
  174. struct mvebu_spi_priv {
  175. struct kwspi_registers *spireg;
  176. };
  177. static int mvebu_spi_set_speed(struct udevice *bus, uint hz)
  178. {
  179. struct mvebu_spi_platdata *plat = dev_get_platdata(bus);
  180. struct kwspi_registers *reg = plat->spireg;
  181. u32 data;
  182. /* calculate spi clock prescaller using max_hz */
  183. data = ((CONFIG_SYS_TCLK / 2) / hz) + 0x10;
  184. data = data < KWSPI_CLKPRESCL_MIN ? KWSPI_CLKPRESCL_MIN : data;
  185. data = data > KWSPI_CLKPRESCL_MASK ? KWSPI_CLKPRESCL_MASK : data;
  186. /* program spi clock prescaler using max_hz */
  187. writel(KWSPI_ADRLEN_3BYTE | data, &reg->cfg);
  188. debug("data = 0x%08x\n", data);
  189. return 0;
  190. }
  191. static void mvebu_spi_50mhz_ac_timing_erratum(struct udevice *bus, uint mode)
  192. {
  193. struct mvebu_spi_platdata *plat = dev_get_platdata(bus);
  194. struct kwspi_registers *reg = plat->spireg;
  195. u32 data;
  196. /*
  197. * Erratum description: (Erratum NO. FE-9144572) The device
  198. * SPI interface supports frequencies of up to 50 MHz.
  199. * However, due to this erratum, when the device core clock is
  200. * 250 MHz and the SPI interfaces is configured for 50MHz SPI
  201. * clock and CPOL=CPHA=1 there might occur data corruption on
  202. * reads from the SPI device.
  203. * Erratum Workaround:
  204. * Work in one of the following configurations:
  205. * 1. Set CPOL=CPHA=0 in "SPI Interface Configuration
  206. * Register".
  207. * 2. Set TMISO_SAMPLE value to 0x2 in "SPI Timing Parameters 1
  208. * Register" before setting the interface.
  209. */
  210. data = readl(&reg->timing1);
  211. data &= ~KW_SPI_TMISO_SAMPLE_MASK;
  212. if (CONFIG_SYS_TCLK == 250000000 &&
  213. mode & SPI_CPOL &&
  214. mode & SPI_CPHA)
  215. data |= KW_SPI_TMISO_SAMPLE_2;
  216. else
  217. data |= KW_SPI_TMISO_SAMPLE_1;
  218. writel(data, &reg->timing1);
  219. }
  220. static int mvebu_spi_set_mode(struct udevice *bus, uint mode)
  221. {
  222. struct mvebu_spi_platdata *plat = dev_get_platdata(bus);
  223. struct kwspi_registers *reg = plat->spireg;
  224. u32 data = readl(&reg->cfg);
  225. data &= ~(KWSPI_CPHA | KWSPI_CPOL | KWSPI_RXLSBF | KWSPI_TXLSBF);
  226. if (mode & SPI_CPHA)
  227. data |= KWSPI_CPHA;
  228. if (mode & SPI_CPOL)
  229. data |= KWSPI_CPOL;
  230. if (mode & SPI_LSB_FIRST)
  231. data |= (KWSPI_RXLSBF | KWSPI_TXLSBF);
  232. writel(data, &reg->cfg);
  233. if (plat->is_errata_50mhz_ac)
  234. mvebu_spi_50mhz_ac_timing_erratum(bus, mode);
  235. return 0;
  236. }
  237. static int mvebu_spi_xfer(struct udevice *dev, unsigned int bitlen,
  238. const void *dout, void *din, unsigned long flags)
  239. {
  240. struct udevice *bus = dev->parent;
  241. struct mvebu_spi_platdata *plat = dev_get_platdata(bus);
  242. return _spi_xfer(plat->spireg, bitlen, dout, din, flags);
  243. }
  244. __attribute__((weak)) int mvebu_board_spi_claim_bus(struct udevice *dev)
  245. {
  246. return 0;
  247. }
  248. static int mvebu_spi_claim_bus(struct udevice *dev)
  249. {
  250. struct udevice *bus = dev->parent;
  251. struct mvebu_spi_platdata *plat = dev_get_platdata(bus);
  252. /* Configure the chip-select in the CTRL register */
  253. clrsetbits_le32(&plat->spireg->ctrl,
  254. KWSPI_CS_MASK << KWSPI_CS_SHIFT,
  255. spi_chip_select(dev) << KWSPI_CS_SHIFT);
  256. return mvebu_board_spi_claim_bus(dev);
  257. }
  258. __attribute__((weak)) int mvebu_board_spi_release_bus(struct udevice *dev)
  259. {
  260. return 0;
  261. }
  262. static int mvebu_spi_release_bus(struct udevice *dev)
  263. {
  264. return mvebu_board_spi_release_bus(dev);
  265. }
  266. static int mvebu_spi_probe(struct udevice *bus)
  267. {
  268. struct mvebu_spi_platdata *plat = dev_get_platdata(bus);
  269. struct kwspi_registers *reg = plat->spireg;
  270. writel(KWSPI_SMEMRDY, &reg->ctrl);
  271. writel(KWSPI_SMEMRDIRQ, &reg->irq_cause);
  272. writel(KWSPI_IRQMASK, &reg->irq_mask);
  273. return 0;
  274. }
  275. static int mvebu_spi_ofdata_to_platdata(struct udevice *bus)
  276. {
  277. struct mvebu_spi_platdata *plat = dev_get_platdata(bus);
  278. const struct mvebu_spi_dev *drvdata =
  279. (struct mvebu_spi_dev *)dev_get_driver_data(bus);
  280. plat->spireg = (struct kwspi_registers *)devfdt_get_addr(bus);
  281. plat->is_errata_50mhz_ac = drvdata->is_errata_50mhz_ac;
  282. return 0;
  283. }
  284. static const struct dm_spi_ops mvebu_spi_ops = {
  285. .claim_bus = mvebu_spi_claim_bus,
  286. .release_bus = mvebu_spi_release_bus,
  287. .xfer = mvebu_spi_xfer,
  288. .set_speed = mvebu_spi_set_speed,
  289. .set_mode = mvebu_spi_set_mode,
  290. /*
  291. * cs_info is not needed, since we require all chip selects to be
  292. * in the device tree explicitly
  293. */
  294. };
  295. static const struct mvebu_spi_dev armada_spi_dev_data = {
  296. .is_errata_50mhz_ac = false,
  297. };
  298. static const struct mvebu_spi_dev armada_xp_spi_dev_data = {
  299. .is_errata_50mhz_ac = false,
  300. };
  301. static const struct mvebu_spi_dev armada_375_spi_dev_data = {
  302. .is_errata_50mhz_ac = false,
  303. };
  304. static const struct mvebu_spi_dev armada_380_spi_dev_data = {
  305. .is_errata_50mhz_ac = true,
  306. };
  307. static const struct udevice_id mvebu_spi_ids[] = {
  308. {
  309. .compatible = "marvell,orion-spi",
  310. .data = (ulong)&armada_spi_dev_data,
  311. },
  312. {
  313. .compatible = "marvell,armada-375-spi",
  314. .data = (ulong)&armada_375_spi_dev_data
  315. },
  316. {
  317. .compatible = "marvell,armada-380-spi",
  318. .data = (ulong)&armada_380_spi_dev_data
  319. },
  320. {
  321. .compatible = "marvell,armada-xp-spi",
  322. .data = (ulong)&armada_xp_spi_dev_data
  323. },
  324. { }
  325. };
  326. U_BOOT_DRIVER(mvebu_spi) = {
  327. .name = "mvebu_spi",
  328. .id = UCLASS_SPI,
  329. .of_match = mvebu_spi_ids,
  330. .ops = &mvebu_spi_ops,
  331. .ofdata_to_platdata = mvebu_spi_ofdata_to_platdata,
  332. .platdata_auto_alloc_size = sizeof(struct mvebu_spi_platdata),
  333. .priv_auto_alloc_size = sizeof(struct mvebu_spi_priv),
  334. .probe = mvebu_spi_probe,
  335. };
  336. #endif