spi-nor-tiny.c 19 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Based on m25p80.c, by Mike Lavender (mike@steroidmicros.com), with
  4. * influence from lart.c (Abraham Van Der Merwe) and mtd_dataflash.c
  5. *
  6. * Copyright (C) 2005, Intec Automation Inc.
  7. * Copyright (C) 2014, Freescale Semiconductor, Inc.
  8. *
  9. * Synced from Linux v4.19
  10. */
  11. #include <common.h>
  12. #include <log.h>
  13. #include <dm/device_compat.h>
  14. #include <linux/err.h>
  15. #include <linux/errno.h>
  16. #include <linux/log2.h>
  17. #include <linux/math64.h>
  18. #include <linux/sizes.h>
  19. #include <linux/mtd/mtd.h>
  20. #include <linux/mtd/spi-nor.h>
  21. #include <spi-mem.h>
  22. #include <spi.h>
  23. #include "sf_internal.h"
  24. /* Define max times to check status register before we give up. */
  25. /*
  26. * For everything but full-chip erase; probably could be much smaller, but kept
  27. * around for safety for now
  28. */
  29. #define HZ CONFIG_SYS_HZ
  30. #define DEFAULT_READY_WAIT_JIFFIES (40UL * HZ)
  31. static int spi_nor_read_write_reg(struct spi_nor *nor, struct spi_mem_op
  32. *op, void *buf)
  33. {
  34. if (op->data.dir == SPI_MEM_DATA_IN)
  35. op->data.buf.in = buf;
  36. else
  37. op->data.buf.out = buf;
  38. return spi_mem_exec_op(nor->spi, op);
  39. }
  40. static int spi_nor_read_reg(struct spi_nor *nor, u8 code, u8 *val, int len)
  41. {
  42. struct spi_mem_op op = SPI_MEM_OP(SPI_MEM_OP_CMD(code, 1),
  43. SPI_MEM_OP_NO_ADDR,
  44. SPI_MEM_OP_NO_DUMMY,
  45. SPI_MEM_OP_DATA_IN(len, NULL, 1));
  46. int ret;
  47. ret = spi_nor_read_write_reg(nor, &op, val);
  48. if (ret < 0)
  49. dev_dbg(&flash->spimem->spi->dev, "error %d reading %x\n", ret,
  50. code);
  51. return ret;
  52. }
  53. static int spi_nor_write_reg(struct spi_nor *nor, u8 opcode, u8 *buf, int len)
  54. {
  55. struct spi_mem_op op = SPI_MEM_OP(SPI_MEM_OP_CMD(opcode, 1),
  56. SPI_MEM_OP_NO_ADDR,
  57. SPI_MEM_OP_NO_DUMMY,
  58. SPI_MEM_OP_DATA_OUT(len, NULL, 1));
  59. return spi_nor_read_write_reg(nor, &op, buf);
  60. }
  61. static ssize_t spi_nor_read_data(struct spi_nor *nor, loff_t from, size_t len,
  62. u_char *buf)
  63. {
  64. struct spi_mem_op op =
  65. SPI_MEM_OP(SPI_MEM_OP_CMD(nor->read_opcode, 1),
  66. SPI_MEM_OP_ADDR(nor->addr_width, from, 1),
  67. SPI_MEM_OP_DUMMY(nor->read_dummy, 1),
  68. SPI_MEM_OP_DATA_IN(len, buf, 1));
  69. size_t remaining = len;
  70. int ret;
  71. /* get transfer protocols. */
  72. op.cmd.buswidth = spi_nor_get_protocol_inst_nbits(nor->read_proto);
  73. op.addr.buswidth = spi_nor_get_protocol_addr_nbits(nor->read_proto);
  74. op.dummy.buswidth = op.addr.buswidth;
  75. op.data.buswidth = spi_nor_get_protocol_data_nbits(nor->read_proto);
  76. /* convert the dummy cycles to the number of bytes */
  77. op.dummy.nbytes = (nor->read_dummy * op.dummy.buswidth) / 8;
  78. while (remaining) {
  79. op.data.nbytes = remaining < UINT_MAX ? remaining : UINT_MAX;
  80. ret = spi_mem_adjust_op_size(nor->spi, &op);
  81. if (ret)
  82. return ret;
  83. ret = spi_mem_exec_op(nor->spi, &op);
  84. if (ret)
  85. return ret;
  86. op.addr.val += op.data.nbytes;
  87. remaining -= op.data.nbytes;
  88. op.data.buf.in += op.data.nbytes;
  89. }
  90. return len;
  91. }
  92. #if defined(CONFIG_SPI_FLASH_SPANSION) || defined(CONFIG_SPI_FLASH_WINBOND)
  93. /*
  94. * Read configuration register, returning its value in the
  95. * location. Return the configuration register value.
  96. * Returns negative if error occurred.
  97. */
  98. static int read_cr(struct spi_nor *nor)
  99. {
  100. int ret;
  101. u8 val;
  102. ret = spi_nor_read_reg(nor, SPINOR_OP_RDCR, &val, 1);
  103. if (ret < 0) {
  104. dev_dbg(nor->dev, "error %d reading CR\n", ret);
  105. return ret;
  106. }
  107. return val;
  108. }
  109. #endif
  110. /*
  111. * Write status register 1 byte
  112. * Returns negative if error occurred.
  113. */
  114. static inline int write_sr(struct spi_nor *nor, u8 val)
  115. {
  116. nor->cmd_buf[0] = val;
  117. return spi_nor_write_reg(nor, SPINOR_OP_WRSR, nor->cmd_buf, 1);
  118. }
  119. /*
  120. * Set write enable latch with Write Enable command.
  121. * Returns negative if error occurred.
  122. */
  123. static inline int write_enable(struct spi_nor *nor)
  124. {
  125. return spi_nor_write_reg(nor, SPINOR_OP_WREN, NULL, 0);
  126. }
  127. /*
  128. * Send write disable instruction to the chip.
  129. */
  130. static inline int write_disable(struct spi_nor *nor)
  131. {
  132. return spi_nor_write_reg(nor, SPINOR_OP_WRDI, NULL, 0);
  133. }
  134. static inline struct spi_nor *mtd_to_spi_nor(struct mtd_info *mtd)
  135. {
  136. return mtd->priv;
  137. }
  138. static u8 spi_nor_convert_opcode(u8 opcode, const u8 table[][2], size_t size)
  139. {
  140. size_t i;
  141. for (i = 0; i < size; i++)
  142. if (table[i][0] == opcode)
  143. return table[i][1];
  144. /* No conversion found, keep input op code. */
  145. return opcode;
  146. }
  147. static inline u8 spi_nor_convert_3to4_read(u8 opcode)
  148. {
  149. static const u8 spi_nor_3to4_read[][2] = {
  150. { SPINOR_OP_READ, SPINOR_OP_READ_4B },
  151. { SPINOR_OP_READ_FAST, SPINOR_OP_READ_FAST_4B },
  152. { SPINOR_OP_READ_1_1_2, SPINOR_OP_READ_1_1_2_4B },
  153. { SPINOR_OP_READ_1_2_2, SPINOR_OP_READ_1_2_2_4B },
  154. { SPINOR_OP_READ_1_1_4, SPINOR_OP_READ_1_1_4_4B },
  155. { SPINOR_OP_READ_1_4_4, SPINOR_OP_READ_1_4_4_4B },
  156. };
  157. return spi_nor_convert_opcode(opcode, spi_nor_3to4_read,
  158. ARRAY_SIZE(spi_nor_3to4_read));
  159. }
  160. static void spi_nor_set_4byte_opcodes(struct spi_nor *nor,
  161. const struct flash_info *info)
  162. {
  163. nor->read_opcode = spi_nor_convert_3to4_read(nor->read_opcode);
  164. }
  165. /* Enable/disable 4-byte addressing mode. */
  166. static inline int set_4byte(struct spi_nor *nor, const struct flash_info *info,
  167. int enable)
  168. {
  169. int status;
  170. bool need_wren = false;
  171. u8 cmd;
  172. switch (JEDEC_MFR(info)) {
  173. case SNOR_MFR_ST:
  174. case SNOR_MFR_MICRON:
  175. /* Some Micron need WREN command; all will accept it */
  176. need_wren = true;
  177. case SNOR_MFR_MACRONIX:
  178. case SNOR_MFR_WINBOND:
  179. if (need_wren)
  180. write_enable(nor);
  181. cmd = enable ? SPINOR_OP_EN4B : SPINOR_OP_EX4B;
  182. status = spi_nor_write_reg(nor, cmd, NULL, 0);
  183. if (need_wren)
  184. write_disable(nor);
  185. if (!status && !enable &&
  186. JEDEC_MFR(info) == SNOR_MFR_WINBOND) {
  187. /*
  188. * On Winbond W25Q256FV, leaving 4byte mode causes
  189. * the Extended Address Register to be set to 1, so all
  190. * 3-byte-address reads come from the second 16M.
  191. * We must clear the register to enable normal behavior.
  192. */
  193. write_enable(nor);
  194. nor->cmd_buf[0] = 0;
  195. spi_nor_write_reg(nor, SPINOR_OP_WREAR,
  196. nor->cmd_buf, 1);
  197. write_disable(nor);
  198. }
  199. return status;
  200. default:
  201. /* Spansion style */
  202. nor->cmd_buf[0] = enable << 7;
  203. return spi_nor_write_reg(nor, SPINOR_OP_BRWR, nor->cmd_buf, 1);
  204. }
  205. }
  206. #if defined(CONFIG_SPI_FLASH_SPANSION) || \
  207. defined(CONFIG_SPI_FLASH_WINBOND) || \
  208. defined(CONFIG_SPI_FLASH_MACRONIX)
  209. /*
  210. * Read the status register, returning its value in the location
  211. * Return the status register value.
  212. * Returns negative if error occurred.
  213. */
  214. static int read_sr(struct spi_nor *nor)
  215. {
  216. int ret;
  217. u8 val;
  218. ret = spi_nor_read_reg(nor, SPINOR_OP_RDSR, &val, 1);
  219. if (ret < 0) {
  220. pr_debug("error %d reading SR\n", (int)ret);
  221. return ret;
  222. }
  223. return val;
  224. }
  225. /*
  226. * Read the flag status register, returning its value in the location
  227. * Return the status register value.
  228. * Returns negative if error occurred.
  229. */
  230. static int read_fsr(struct spi_nor *nor)
  231. {
  232. int ret;
  233. u8 val;
  234. ret = spi_nor_read_reg(nor, SPINOR_OP_RDFSR, &val, 1);
  235. if (ret < 0) {
  236. pr_debug("error %d reading FSR\n", ret);
  237. return ret;
  238. }
  239. return val;
  240. }
  241. static int spi_nor_sr_ready(struct spi_nor *nor)
  242. {
  243. int sr = read_sr(nor);
  244. if (sr < 0)
  245. return sr;
  246. return !(sr & SR_WIP);
  247. }
  248. static int spi_nor_fsr_ready(struct spi_nor *nor)
  249. {
  250. int fsr = read_fsr(nor);
  251. if (fsr < 0)
  252. return fsr;
  253. return fsr & FSR_READY;
  254. }
  255. static int spi_nor_ready(struct spi_nor *nor)
  256. {
  257. int sr, fsr;
  258. sr = spi_nor_sr_ready(nor);
  259. if (sr < 0)
  260. return sr;
  261. fsr = nor->flags & SNOR_F_USE_FSR ? spi_nor_fsr_ready(nor) : 1;
  262. if (fsr < 0)
  263. return fsr;
  264. return sr && fsr;
  265. }
  266. /*
  267. * Service routine to read status register until ready, or timeout occurs.
  268. * Returns non-zero if error.
  269. */
  270. static int spi_nor_wait_till_ready_with_timeout(struct spi_nor *nor,
  271. unsigned long timeout)
  272. {
  273. unsigned long timebase;
  274. int ret;
  275. timebase = get_timer(0);
  276. while (get_timer(timebase) < timeout) {
  277. ret = spi_nor_ready(nor);
  278. if (ret < 0)
  279. return ret;
  280. if (ret)
  281. return 0;
  282. }
  283. dev_err(nor->dev, "flash operation timed out\n");
  284. return -ETIMEDOUT;
  285. }
  286. static int spi_nor_wait_till_ready(struct spi_nor *nor)
  287. {
  288. return spi_nor_wait_till_ready_with_timeout(nor,
  289. DEFAULT_READY_WAIT_JIFFIES);
  290. }
  291. #endif /* CONFIG_SPI_FLASH_SPANSION */
  292. /*
  293. * Erase an address range on the nor chip. The address range may extend
  294. * one or more erase sectors. Return an error is there is a problem erasing.
  295. */
  296. static int spi_nor_erase(struct mtd_info *mtd, struct erase_info *instr)
  297. {
  298. return -ENOTSUPP;
  299. }
  300. static const struct flash_info *spi_nor_read_id(struct spi_nor *nor)
  301. {
  302. int tmp;
  303. u8 id[SPI_NOR_MAX_ID_LEN];
  304. const struct flash_info *info;
  305. tmp = spi_nor_read_reg(nor, SPINOR_OP_RDID, id, SPI_NOR_MAX_ID_LEN);
  306. if (tmp < 0) {
  307. dev_dbg(nor->dev, "error %d reading JEDEC ID\n", tmp);
  308. return ERR_PTR(tmp);
  309. }
  310. info = spi_nor_ids;
  311. for (; info->sector_size != 0; info++) {
  312. if (info->id_len) {
  313. if (!memcmp(info->id, id, info->id_len))
  314. return info;
  315. }
  316. }
  317. dev_dbg(nor->dev, "unrecognized JEDEC id bytes: %02x, %02x, %02x\n",
  318. id[0], id[1], id[2]);
  319. return ERR_PTR(-ENODEV);
  320. }
  321. static int spi_nor_read(struct mtd_info *mtd, loff_t from, size_t len,
  322. size_t *retlen, u_char *buf)
  323. {
  324. struct spi_nor *nor = mtd_to_spi_nor(mtd);
  325. int ret;
  326. dev_dbg(nor->dev, "from 0x%08x, len %zd\n", (u32)from, len);
  327. while (len) {
  328. loff_t addr = from;
  329. ret = spi_nor_read_data(nor, addr, len, buf);
  330. if (ret == 0) {
  331. /* We shouldn't see 0-length reads */
  332. ret = -EIO;
  333. goto read_err;
  334. }
  335. if (ret < 0)
  336. goto read_err;
  337. *retlen += ret;
  338. buf += ret;
  339. from += ret;
  340. len -= ret;
  341. }
  342. ret = 0;
  343. read_err:
  344. return ret;
  345. }
  346. /*
  347. * Write an address range to the nor chip. Data must be written in
  348. * FLASH_PAGESIZE chunks. The address range may be any size provided
  349. * it is within the physical boundaries.
  350. */
  351. static int spi_nor_write(struct mtd_info *mtd, loff_t to, size_t len,
  352. size_t *retlen, const u_char *buf)
  353. {
  354. return -ENOTSUPP;
  355. }
  356. #ifdef CONFIG_SPI_FLASH_MACRONIX
  357. /**
  358. * macronix_quad_enable() - set QE bit in Status Register.
  359. * @nor: pointer to a 'struct spi_nor'
  360. *
  361. * Set the Quad Enable (QE) bit in the Status Register.
  362. *
  363. * bit 6 of the Status Register is the QE bit for Macronix like QSPI memories.
  364. *
  365. * Return: 0 on success, -errno otherwise.
  366. */
  367. static int macronix_quad_enable(struct spi_nor *nor)
  368. {
  369. int ret, val;
  370. val = read_sr(nor);
  371. if (val < 0)
  372. return val;
  373. if (val & SR_QUAD_EN_MX)
  374. return 0;
  375. write_enable(nor);
  376. write_sr(nor, val | SR_QUAD_EN_MX);
  377. ret = spi_nor_wait_till_ready(nor);
  378. if (ret)
  379. return ret;
  380. ret = read_sr(nor);
  381. if (!(ret > 0 && (ret & SR_QUAD_EN_MX))) {
  382. dev_err(nor->dev, "Macronix Quad bit not set\n");
  383. return -EINVAL;
  384. }
  385. return 0;
  386. }
  387. #endif
  388. #if defined(CONFIG_SPI_FLASH_SPANSION) || defined(CONFIG_SPI_FLASH_WINBOND)
  389. /*
  390. * Write status Register and configuration register with 2 bytes
  391. * The first byte will be written to the status register, while the
  392. * second byte will be written to the configuration register.
  393. * Return negative if error occurred.
  394. */
  395. static int write_sr_cr(struct spi_nor *nor, u8 *sr_cr)
  396. {
  397. int ret;
  398. write_enable(nor);
  399. ret = spi_nor_write_reg(nor, SPINOR_OP_WRSR, sr_cr, 2);
  400. if (ret < 0) {
  401. dev_dbg(nor->dev,
  402. "error while writing configuration register\n");
  403. return -EINVAL;
  404. }
  405. ret = spi_nor_wait_till_ready(nor);
  406. if (ret) {
  407. dev_dbg(nor->dev,
  408. "timeout while writing configuration register\n");
  409. return ret;
  410. }
  411. return 0;
  412. }
  413. /**
  414. * spansion_read_cr_quad_enable() - set QE bit in Configuration Register.
  415. * @nor: pointer to a 'struct spi_nor'
  416. *
  417. * Set the Quad Enable (QE) bit in the Configuration Register.
  418. * This function should be used with QSPI memories supporting the Read
  419. * Configuration Register (35h) instruction.
  420. *
  421. * bit 1 of the Configuration Register is the QE bit for Spansion like QSPI
  422. * memories.
  423. *
  424. * Return: 0 on success, -errno otherwise.
  425. */
  426. static int spansion_read_cr_quad_enable(struct spi_nor *nor)
  427. {
  428. u8 sr_cr[2];
  429. int ret;
  430. /* Check current Quad Enable bit value. */
  431. ret = read_cr(nor);
  432. if (ret < 0) {
  433. dev_dbg(dev, "error while reading configuration register\n");
  434. return -EINVAL;
  435. }
  436. if (ret & CR_QUAD_EN_SPAN)
  437. return 0;
  438. sr_cr[1] = ret | CR_QUAD_EN_SPAN;
  439. /* Keep the current value of the Status Register. */
  440. ret = read_sr(nor);
  441. if (ret < 0) {
  442. dev_dbg(dev, "error while reading status register\n");
  443. return -EINVAL;
  444. }
  445. sr_cr[0] = ret;
  446. ret = write_sr_cr(nor, sr_cr);
  447. if (ret)
  448. return ret;
  449. /* Read back and check it. */
  450. ret = read_cr(nor);
  451. if (!(ret > 0 && (ret & CR_QUAD_EN_SPAN))) {
  452. dev_dbg(nor->dev, "Spansion Quad bit not set\n");
  453. return -EINVAL;
  454. }
  455. return 0;
  456. }
  457. #endif /* CONFIG_SPI_FLASH_SPANSION */
  458. struct spi_nor_read_command {
  459. u8 num_mode_clocks;
  460. u8 num_wait_states;
  461. u8 opcode;
  462. enum spi_nor_protocol proto;
  463. };
  464. enum spi_nor_read_command_index {
  465. SNOR_CMD_READ,
  466. SNOR_CMD_READ_FAST,
  467. /* Quad SPI */
  468. SNOR_CMD_READ_1_1_4,
  469. SNOR_CMD_READ_MAX
  470. };
  471. struct spi_nor_flash_parameter {
  472. struct spi_nor_hwcaps hwcaps;
  473. struct spi_nor_read_command reads[SNOR_CMD_READ_MAX];
  474. };
  475. static void
  476. spi_nor_set_read_settings(struct spi_nor_read_command *read,
  477. u8 num_mode_clocks,
  478. u8 num_wait_states,
  479. u8 opcode,
  480. enum spi_nor_protocol proto)
  481. {
  482. read->num_mode_clocks = num_mode_clocks;
  483. read->num_wait_states = num_wait_states;
  484. read->opcode = opcode;
  485. read->proto = proto;
  486. }
  487. static int spi_nor_init_params(struct spi_nor *nor,
  488. const struct flash_info *info,
  489. struct spi_nor_flash_parameter *params)
  490. {
  491. /* (Fast) Read settings. */
  492. params->hwcaps.mask = SNOR_HWCAPS_READ;
  493. spi_nor_set_read_settings(&params->reads[SNOR_CMD_READ],
  494. 0, 0, SPINOR_OP_READ,
  495. SNOR_PROTO_1_1_1);
  496. if (!(info->flags & SPI_NOR_NO_FR)) {
  497. params->hwcaps.mask |= SNOR_HWCAPS_READ_FAST;
  498. spi_nor_set_read_settings(&params->reads[SNOR_CMD_READ_FAST],
  499. 0, 8, SPINOR_OP_READ_FAST,
  500. SNOR_PROTO_1_1_1);
  501. }
  502. if (info->flags & SPI_NOR_QUAD_READ) {
  503. params->hwcaps.mask |= SNOR_HWCAPS_READ_1_1_4;
  504. spi_nor_set_read_settings(&params->reads[SNOR_CMD_READ_1_1_4],
  505. 0, 8, SPINOR_OP_READ_1_1_4,
  506. SNOR_PROTO_1_1_4);
  507. }
  508. return 0;
  509. }
  510. static int spi_nor_select_read(struct spi_nor *nor,
  511. const struct spi_nor_flash_parameter *params,
  512. u32 shared_hwcaps)
  513. {
  514. int best_match = shared_hwcaps & SNOR_HWCAPS_READ_MASK;
  515. int cmd;
  516. const struct spi_nor_read_command *read;
  517. if (best_match < 0)
  518. return -EINVAL;
  519. if (best_match & SNOR_HWCAPS_READ_1_1_4)
  520. cmd = SNOR_CMD_READ_1_1_4;
  521. else if (best_match & SNOR_HWCAPS_READ_FAST)
  522. cmd = SNOR_CMD_READ_FAST;
  523. else
  524. cmd = SNOR_CMD_READ;
  525. read = &params->reads[cmd];
  526. nor->read_opcode = read->opcode;
  527. nor->read_proto = read->proto;
  528. /*
  529. * In the spi-nor framework, we don't need to make the difference
  530. * between mode clock cycles and wait state clock cycles.
  531. * Indeed, the value of the mode clock cycles is used by a QSPI
  532. * flash memory to know whether it should enter or leave its 0-4-4
  533. * (Continuous Read / XIP) mode.
  534. * eXecution In Place is out of the scope of the mtd sub-system.
  535. * Hence we choose to merge both mode and wait state clock cycles
  536. * into the so called dummy clock cycles.
  537. */
  538. nor->read_dummy = read->num_mode_clocks + read->num_wait_states;
  539. return 0;
  540. }
  541. static int spi_nor_setup(struct spi_nor *nor, const struct flash_info *info,
  542. const struct spi_nor_flash_parameter *params,
  543. const struct spi_nor_hwcaps *hwcaps)
  544. {
  545. u32 shared_mask;
  546. int err;
  547. /*
  548. * Keep only the hardware capabilities supported by both the SPI
  549. * controller and the SPI flash memory.
  550. */
  551. shared_mask = hwcaps->mask & params->hwcaps.mask;
  552. /* Select the (Fast) Read command. */
  553. err = spi_nor_select_read(nor, params, shared_mask);
  554. if (err) {
  555. dev_dbg(nor->dev,
  556. "can't select read settings supported by both the SPI controller and memory.\n");
  557. return err;
  558. }
  559. /* Enable Quad I/O if needed. */
  560. if (spi_nor_get_protocol_width(nor->read_proto) == 4) {
  561. switch (JEDEC_MFR(info)) {
  562. #ifdef CONFIG_SPI_FLASH_MACRONIX
  563. case SNOR_MFR_MACRONIX:
  564. err = macronix_quad_enable(nor);
  565. break;
  566. #endif
  567. case SNOR_MFR_ST:
  568. case SNOR_MFR_MICRON:
  569. break;
  570. default:
  571. #if defined(CONFIG_SPI_FLASH_SPANSION) || defined(CONFIG_SPI_FLASH_WINBOND)
  572. /* Kept only for backward compatibility purpose. */
  573. err = spansion_read_cr_quad_enable(nor);
  574. #endif
  575. break;
  576. }
  577. }
  578. if (err) {
  579. dev_dbg(nor->dev, "quad mode not supported\n");
  580. return err;
  581. }
  582. return 0;
  583. }
  584. static int spi_nor_init(struct spi_nor *nor)
  585. {
  586. if (nor->addr_width == 4 &&
  587. (JEDEC_MFR(nor->info) != SNOR_MFR_SPANSION) &&
  588. !(nor->info->flags & SPI_NOR_4B_OPCODES)) {
  589. /*
  590. * If the RESET# pin isn't hooked up properly, or the system
  591. * otherwise doesn't perform a reset command in the boot
  592. * sequence, it's impossible to 100% protect against unexpected
  593. * reboots (e.g., crashes). Warn the user (or hopefully, system
  594. * designer) that this is bad.
  595. */
  596. if (nor->flags & SNOR_F_BROKEN_RESET)
  597. printf("enabling reset hack; may not recover from unexpected reboots\n");
  598. set_4byte(nor, nor->info, 1);
  599. }
  600. return 0;
  601. }
  602. int spi_nor_scan(struct spi_nor *nor)
  603. {
  604. struct spi_nor_flash_parameter params;
  605. const struct flash_info *info = NULL;
  606. struct mtd_info *mtd = &nor->mtd;
  607. struct spi_nor_hwcaps hwcaps = {
  608. .mask = SNOR_HWCAPS_READ |
  609. SNOR_HWCAPS_READ_FAST
  610. };
  611. struct spi_slave *spi = nor->spi;
  612. int ret;
  613. /* Reset SPI protocol for all commands. */
  614. nor->reg_proto = SNOR_PROTO_1_1_1;
  615. nor->read_proto = SNOR_PROTO_1_1_1;
  616. nor->write_proto = SNOR_PROTO_1_1_1;
  617. if (spi->mode & SPI_RX_QUAD)
  618. hwcaps.mask |= SNOR_HWCAPS_READ_1_1_4;
  619. info = spi_nor_read_id(nor);
  620. if (IS_ERR_OR_NULL(info))
  621. return -ENOENT;
  622. /* Parse the Serial Flash Discoverable Parameters table. */
  623. ret = spi_nor_init_params(nor, info, &params);
  624. if (ret)
  625. return ret;
  626. mtd->name = "spi-flash";
  627. mtd->priv = nor;
  628. mtd->type = MTD_NORFLASH;
  629. mtd->writesize = 1;
  630. mtd->flags = MTD_CAP_NORFLASH;
  631. mtd->size = info->sector_size * info->n_sectors;
  632. mtd->_erase = spi_nor_erase;
  633. mtd->_read = spi_nor_read;
  634. mtd->_write = spi_nor_write;
  635. nor->size = mtd->size;
  636. if (info->flags & USE_FSR)
  637. nor->flags |= SNOR_F_USE_FSR;
  638. if (info->flags & USE_CLSR)
  639. nor->flags |= SNOR_F_USE_CLSR;
  640. if (info->flags & SPI_NOR_NO_FR)
  641. params.hwcaps.mask &= ~SNOR_HWCAPS_READ_FAST;
  642. /*
  643. * Configure the SPI memory:
  644. * - select op codes for (Fast) Read, Page Program and Sector Erase.
  645. * - set the number of dummy cycles (mode cycles + wait states).
  646. * - set the SPI protocols for register and memory accesses.
  647. * - set the Quad Enable bit if needed (required by SPI x-y-4 protos).
  648. */
  649. ret = spi_nor_setup(nor, info, &params, &hwcaps);
  650. if (ret)
  651. return ret;
  652. if (nor->addr_width) {
  653. /* already configured from SFDP */
  654. } else if (info->addr_width) {
  655. nor->addr_width = info->addr_width;
  656. } else if (mtd->size > 0x1000000) {
  657. /* enable 4-byte addressing if the device exceeds 16MiB */
  658. nor->addr_width = 4;
  659. if (JEDEC_MFR(info) == SNOR_MFR_SPANSION ||
  660. info->flags & SPI_NOR_4B_OPCODES)
  661. spi_nor_set_4byte_opcodes(nor, info);
  662. } else {
  663. nor->addr_width = 3;
  664. }
  665. if (nor->addr_width > SPI_NOR_MAX_ADDR_WIDTH) {
  666. dev_dbg(dev, "address width is too large: %u\n",
  667. nor->addr_width);
  668. return -EINVAL;
  669. }
  670. /* Send all the required SPI flash commands to initialize device */
  671. nor->info = info;
  672. ret = spi_nor_init(nor);
  673. if (ret)
  674. return ret;
  675. return 0;
  676. }