spi-nor-core.c 68 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Based on m25p80.c, by Mike Lavender (mike@steroidmicros.com), with
  4. * influence from lart.c (Abraham Van Der Merwe) and mtd_dataflash.c
  5. *
  6. * Copyright (C) 2005, Intec Automation Inc.
  7. * Copyright (C) 2014, Freescale Semiconductor, Inc.
  8. *
  9. * Synced from Linux v4.19
  10. */
  11. #include <common.h>
  12. #include <log.h>
  13. #include <dm/device_compat.h>
  14. #include <dm/devres.h>
  15. #include <linux/bitops.h>
  16. #include <linux/err.h>
  17. #include <linux/errno.h>
  18. #include <linux/log2.h>
  19. #include <linux/math64.h>
  20. #include <linux/sizes.h>
  21. #include <linux/mtd/mtd.h>
  22. #include <linux/mtd/spi-nor.h>
  23. #include <spi-mem.h>
  24. #include <spi.h>
  25. #include "sf_internal.h"
  26. /* Define max times to check status register before we give up. */
  27. /*
  28. * For everything but full-chip erase; probably could be much smaller, but kept
  29. * around for safety for now
  30. */
  31. #define HZ CONFIG_SYS_HZ
  32. #define DEFAULT_READY_WAIT_JIFFIES (40UL * HZ)
  33. static int spi_nor_read_write_reg(struct spi_nor *nor, struct spi_mem_op
  34. *op, void *buf)
  35. {
  36. if (op->data.dir == SPI_MEM_DATA_IN)
  37. op->data.buf.in = buf;
  38. else
  39. op->data.buf.out = buf;
  40. return spi_mem_exec_op(nor->spi, op);
  41. }
  42. static int spi_nor_read_reg(struct spi_nor *nor, u8 code, u8 *val, int len)
  43. {
  44. struct spi_mem_op op = SPI_MEM_OP(SPI_MEM_OP_CMD(code, 1),
  45. SPI_MEM_OP_NO_ADDR,
  46. SPI_MEM_OP_NO_DUMMY,
  47. SPI_MEM_OP_DATA_IN(len, NULL, 1));
  48. int ret;
  49. ret = spi_nor_read_write_reg(nor, &op, val);
  50. if (ret < 0)
  51. dev_dbg(nor->dev, "error %d reading %x\n", ret, code);
  52. return ret;
  53. }
  54. static int spi_nor_write_reg(struct spi_nor *nor, u8 opcode, u8 *buf, int len)
  55. {
  56. struct spi_mem_op op = SPI_MEM_OP(SPI_MEM_OP_CMD(opcode, 1),
  57. SPI_MEM_OP_NO_ADDR,
  58. SPI_MEM_OP_NO_DUMMY,
  59. SPI_MEM_OP_DATA_OUT(len, NULL, 1));
  60. return spi_nor_read_write_reg(nor, &op, buf);
  61. }
  62. static ssize_t spi_nor_read_data(struct spi_nor *nor, loff_t from, size_t len,
  63. u_char *buf)
  64. {
  65. struct spi_mem_op op =
  66. SPI_MEM_OP(SPI_MEM_OP_CMD(nor->read_opcode, 1),
  67. SPI_MEM_OP_ADDR(nor->addr_width, from, 1),
  68. SPI_MEM_OP_DUMMY(nor->read_dummy, 1),
  69. SPI_MEM_OP_DATA_IN(len, buf, 1));
  70. size_t remaining = len;
  71. int ret;
  72. /* get transfer protocols. */
  73. op.cmd.buswidth = spi_nor_get_protocol_inst_nbits(nor->read_proto);
  74. op.addr.buswidth = spi_nor_get_protocol_addr_nbits(nor->read_proto);
  75. op.dummy.buswidth = op.addr.buswidth;
  76. op.data.buswidth = spi_nor_get_protocol_data_nbits(nor->read_proto);
  77. /* convert the dummy cycles to the number of bytes */
  78. op.dummy.nbytes = (nor->read_dummy * op.dummy.buswidth) / 8;
  79. while (remaining) {
  80. op.data.nbytes = remaining < UINT_MAX ? remaining : UINT_MAX;
  81. ret = spi_mem_adjust_op_size(nor->spi, &op);
  82. if (ret)
  83. return ret;
  84. ret = spi_mem_exec_op(nor->spi, &op);
  85. if (ret)
  86. return ret;
  87. op.addr.val += op.data.nbytes;
  88. remaining -= op.data.nbytes;
  89. op.data.buf.in += op.data.nbytes;
  90. }
  91. return len;
  92. }
  93. static ssize_t spi_nor_write_data(struct spi_nor *nor, loff_t to, size_t len,
  94. const u_char *buf)
  95. {
  96. struct spi_mem_op op =
  97. SPI_MEM_OP(SPI_MEM_OP_CMD(nor->program_opcode, 1),
  98. SPI_MEM_OP_ADDR(nor->addr_width, to, 1),
  99. SPI_MEM_OP_NO_DUMMY,
  100. SPI_MEM_OP_DATA_OUT(len, buf, 1));
  101. int ret;
  102. /* get transfer protocols. */
  103. op.cmd.buswidth = spi_nor_get_protocol_inst_nbits(nor->write_proto);
  104. op.addr.buswidth = spi_nor_get_protocol_addr_nbits(nor->write_proto);
  105. op.data.buswidth = spi_nor_get_protocol_data_nbits(nor->write_proto);
  106. if (nor->program_opcode == SPINOR_OP_AAI_WP && nor->sst_write_second)
  107. op.addr.nbytes = 0;
  108. ret = spi_mem_adjust_op_size(nor->spi, &op);
  109. if (ret)
  110. return ret;
  111. op.data.nbytes = len < op.data.nbytes ? len : op.data.nbytes;
  112. ret = spi_mem_exec_op(nor->spi, &op);
  113. if (ret)
  114. return ret;
  115. return op.data.nbytes;
  116. }
  117. /*
  118. * Read the status register, returning its value in the location
  119. * Return the status register value.
  120. * Returns negative if error occurred.
  121. */
  122. static int read_sr(struct spi_nor *nor)
  123. {
  124. int ret;
  125. u8 val;
  126. ret = nor->read_reg(nor, SPINOR_OP_RDSR, &val, 1);
  127. if (ret < 0) {
  128. pr_debug("error %d reading SR\n", (int)ret);
  129. return ret;
  130. }
  131. return val;
  132. }
  133. /*
  134. * Read the flag status register, returning its value in the location
  135. * Return the status register value.
  136. * Returns negative if error occurred.
  137. */
  138. static int read_fsr(struct spi_nor *nor)
  139. {
  140. int ret;
  141. u8 val;
  142. ret = nor->read_reg(nor, SPINOR_OP_RDFSR, &val, 1);
  143. if (ret < 0) {
  144. pr_debug("error %d reading FSR\n", ret);
  145. return ret;
  146. }
  147. return val;
  148. }
  149. /*
  150. * Read configuration register, returning its value in the
  151. * location. Return the configuration register value.
  152. * Returns negative if error occurred.
  153. */
  154. #if defined(CONFIG_SPI_FLASH_SPANSION) || defined(CONFIG_SPI_FLASH_WINBOND)
  155. static int read_cr(struct spi_nor *nor)
  156. {
  157. int ret;
  158. u8 val;
  159. ret = nor->read_reg(nor, SPINOR_OP_RDCR, &val, 1);
  160. if (ret < 0) {
  161. dev_dbg(nor->dev, "error %d reading CR\n", ret);
  162. return ret;
  163. }
  164. return val;
  165. }
  166. #endif
  167. /*
  168. * Write status register 1 byte
  169. * Returns negative if error occurred.
  170. */
  171. static int write_sr(struct spi_nor *nor, u8 val)
  172. {
  173. nor->cmd_buf[0] = val;
  174. return nor->write_reg(nor, SPINOR_OP_WRSR, nor->cmd_buf, 1);
  175. }
  176. /*
  177. * Set write enable latch with Write Enable command.
  178. * Returns negative if error occurred.
  179. */
  180. static int write_enable(struct spi_nor *nor)
  181. {
  182. return nor->write_reg(nor, SPINOR_OP_WREN, NULL, 0);
  183. }
  184. /*
  185. * Send write disable instruction to the chip.
  186. */
  187. static int write_disable(struct spi_nor *nor)
  188. {
  189. return nor->write_reg(nor, SPINOR_OP_WRDI, NULL, 0);
  190. }
  191. static struct spi_nor *mtd_to_spi_nor(struct mtd_info *mtd)
  192. {
  193. return mtd->priv;
  194. }
  195. #ifndef CONFIG_SPI_FLASH_BAR
  196. static u8 spi_nor_convert_opcode(u8 opcode, const u8 table[][2], size_t size)
  197. {
  198. size_t i;
  199. for (i = 0; i < size; i++)
  200. if (table[i][0] == opcode)
  201. return table[i][1];
  202. /* No conversion found, keep input op code. */
  203. return opcode;
  204. }
  205. static u8 spi_nor_convert_3to4_read(u8 opcode)
  206. {
  207. static const u8 spi_nor_3to4_read[][2] = {
  208. { SPINOR_OP_READ, SPINOR_OP_READ_4B },
  209. { SPINOR_OP_READ_FAST, SPINOR_OP_READ_FAST_4B },
  210. { SPINOR_OP_READ_1_1_2, SPINOR_OP_READ_1_1_2_4B },
  211. { SPINOR_OP_READ_1_2_2, SPINOR_OP_READ_1_2_2_4B },
  212. { SPINOR_OP_READ_1_1_4, SPINOR_OP_READ_1_1_4_4B },
  213. { SPINOR_OP_READ_1_4_4, SPINOR_OP_READ_1_4_4_4B },
  214. { SPINOR_OP_READ_1_1_8, SPINOR_OP_READ_1_1_8_4B },
  215. { SPINOR_OP_READ_1_8_8, SPINOR_OP_READ_1_8_8_4B },
  216. { SPINOR_OP_READ_1_1_1_DTR, SPINOR_OP_READ_1_1_1_DTR_4B },
  217. { SPINOR_OP_READ_1_2_2_DTR, SPINOR_OP_READ_1_2_2_DTR_4B },
  218. { SPINOR_OP_READ_1_4_4_DTR, SPINOR_OP_READ_1_4_4_DTR_4B },
  219. };
  220. return spi_nor_convert_opcode(opcode, spi_nor_3to4_read,
  221. ARRAY_SIZE(spi_nor_3to4_read));
  222. }
  223. static u8 spi_nor_convert_3to4_program(u8 opcode)
  224. {
  225. static const u8 spi_nor_3to4_program[][2] = {
  226. { SPINOR_OP_PP, SPINOR_OP_PP_4B },
  227. { SPINOR_OP_PP_1_1_4, SPINOR_OP_PP_1_1_4_4B },
  228. { SPINOR_OP_PP_1_4_4, SPINOR_OP_PP_1_4_4_4B },
  229. { SPINOR_OP_PP_1_1_8, SPINOR_OP_PP_1_1_8_4B },
  230. { SPINOR_OP_PP_1_8_8, SPINOR_OP_PP_1_8_8_4B },
  231. };
  232. return spi_nor_convert_opcode(opcode, spi_nor_3to4_program,
  233. ARRAY_SIZE(spi_nor_3to4_program));
  234. }
  235. static u8 spi_nor_convert_3to4_erase(u8 opcode)
  236. {
  237. static const u8 spi_nor_3to4_erase[][2] = {
  238. { SPINOR_OP_BE_4K, SPINOR_OP_BE_4K_4B },
  239. { SPINOR_OP_BE_32K, SPINOR_OP_BE_32K_4B },
  240. { SPINOR_OP_SE, SPINOR_OP_SE_4B },
  241. };
  242. return spi_nor_convert_opcode(opcode, spi_nor_3to4_erase,
  243. ARRAY_SIZE(spi_nor_3to4_erase));
  244. }
  245. static void spi_nor_set_4byte_opcodes(struct spi_nor *nor,
  246. const struct flash_info *info)
  247. {
  248. /* Do some manufacturer fixups first */
  249. switch (JEDEC_MFR(info)) {
  250. case SNOR_MFR_SPANSION:
  251. /* No small sector erase for 4-byte command set */
  252. nor->erase_opcode = SPINOR_OP_SE;
  253. nor->mtd.erasesize = info->sector_size;
  254. break;
  255. default:
  256. break;
  257. }
  258. nor->read_opcode = spi_nor_convert_3to4_read(nor->read_opcode);
  259. nor->program_opcode = spi_nor_convert_3to4_program(nor->program_opcode);
  260. nor->erase_opcode = spi_nor_convert_3to4_erase(nor->erase_opcode);
  261. }
  262. #endif /* !CONFIG_SPI_FLASH_BAR */
  263. /* Enable/disable 4-byte addressing mode. */
  264. static int set_4byte(struct spi_nor *nor, const struct flash_info *info,
  265. int enable)
  266. {
  267. int status;
  268. bool need_wren = false;
  269. u8 cmd;
  270. switch (JEDEC_MFR(info)) {
  271. case SNOR_MFR_ST:
  272. case SNOR_MFR_MICRON:
  273. /* Some Micron need WREN command; all will accept it */
  274. need_wren = true;
  275. case SNOR_MFR_ISSI:
  276. case SNOR_MFR_MACRONIX:
  277. case SNOR_MFR_WINBOND:
  278. if (need_wren)
  279. write_enable(nor);
  280. cmd = enable ? SPINOR_OP_EN4B : SPINOR_OP_EX4B;
  281. status = nor->write_reg(nor, cmd, NULL, 0);
  282. if (need_wren)
  283. write_disable(nor);
  284. if (!status && !enable &&
  285. JEDEC_MFR(info) == SNOR_MFR_WINBOND) {
  286. /*
  287. * On Winbond W25Q256FV, leaving 4byte mode causes
  288. * the Extended Address Register to be set to 1, so all
  289. * 3-byte-address reads come from the second 16M.
  290. * We must clear the register to enable normal behavior.
  291. */
  292. write_enable(nor);
  293. nor->cmd_buf[0] = 0;
  294. nor->write_reg(nor, SPINOR_OP_WREAR, nor->cmd_buf, 1);
  295. write_disable(nor);
  296. }
  297. return status;
  298. default:
  299. /* Spansion style */
  300. nor->cmd_buf[0] = enable << 7;
  301. return nor->write_reg(nor, SPINOR_OP_BRWR, nor->cmd_buf, 1);
  302. }
  303. }
  304. static int spi_nor_sr_ready(struct spi_nor *nor)
  305. {
  306. int sr = read_sr(nor);
  307. if (sr < 0)
  308. return sr;
  309. if (nor->flags & SNOR_F_USE_CLSR && sr & (SR_E_ERR | SR_P_ERR)) {
  310. if (sr & SR_E_ERR)
  311. dev_dbg(nor->dev, "Erase Error occurred\n");
  312. else
  313. dev_dbg(nor->dev, "Programming Error occurred\n");
  314. nor->write_reg(nor, SPINOR_OP_CLSR, NULL, 0);
  315. return -EIO;
  316. }
  317. return !(sr & SR_WIP);
  318. }
  319. static int spi_nor_fsr_ready(struct spi_nor *nor)
  320. {
  321. int fsr = read_fsr(nor);
  322. if (fsr < 0)
  323. return fsr;
  324. if (fsr & (FSR_E_ERR | FSR_P_ERR)) {
  325. if (fsr & FSR_E_ERR)
  326. dev_err(nor->dev, "Erase operation failed.\n");
  327. else
  328. dev_err(nor->dev, "Program operation failed.\n");
  329. if (fsr & FSR_PT_ERR)
  330. dev_err(nor->dev,
  331. "Attempted to modify a protected sector.\n");
  332. nor->write_reg(nor, SPINOR_OP_CLFSR, NULL, 0);
  333. return -EIO;
  334. }
  335. return fsr & FSR_READY;
  336. }
  337. static int spi_nor_ready(struct spi_nor *nor)
  338. {
  339. int sr, fsr;
  340. sr = spi_nor_sr_ready(nor);
  341. if (sr < 0)
  342. return sr;
  343. fsr = nor->flags & SNOR_F_USE_FSR ? spi_nor_fsr_ready(nor) : 1;
  344. if (fsr < 0)
  345. return fsr;
  346. return sr && fsr;
  347. }
  348. /*
  349. * Service routine to read status register until ready, or timeout occurs.
  350. * Returns non-zero if error.
  351. */
  352. static int spi_nor_wait_till_ready_with_timeout(struct spi_nor *nor,
  353. unsigned long timeout)
  354. {
  355. unsigned long timebase;
  356. int ret;
  357. timebase = get_timer(0);
  358. while (get_timer(timebase) < timeout) {
  359. ret = spi_nor_ready(nor);
  360. if (ret < 0)
  361. return ret;
  362. if (ret)
  363. return 0;
  364. }
  365. dev_err(nor->dev, "flash operation timed out\n");
  366. return -ETIMEDOUT;
  367. }
  368. static int spi_nor_wait_till_ready(struct spi_nor *nor)
  369. {
  370. return spi_nor_wait_till_ready_with_timeout(nor,
  371. DEFAULT_READY_WAIT_JIFFIES);
  372. }
  373. #ifdef CONFIG_SPI_FLASH_BAR
  374. /*
  375. * This "clean_bar" is necessary in a situation when one was accessing
  376. * spi flash memory > 16 MiB by using Bank Address Register's BA24 bit.
  377. *
  378. * After it the BA24 bit shall be cleared to allow access to correct
  379. * memory region after SW reset (by calling "reset" command).
  380. *
  381. * Otherwise, the BA24 bit may be left set and then after reset, the
  382. * ROM would read/write/erase SPL from 16 MiB * bank_sel address.
  383. */
  384. static int clean_bar(struct spi_nor *nor)
  385. {
  386. u8 cmd, bank_sel = 0;
  387. if (nor->bank_curr == 0)
  388. return 0;
  389. cmd = nor->bank_write_cmd;
  390. nor->bank_curr = 0;
  391. write_enable(nor);
  392. return nor->write_reg(nor, cmd, &bank_sel, 1);
  393. }
  394. static int write_bar(struct spi_nor *nor, u32 offset)
  395. {
  396. u8 cmd, bank_sel;
  397. int ret;
  398. bank_sel = offset / SZ_16M;
  399. if (bank_sel == nor->bank_curr)
  400. goto bar_end;
  401. cmd = nor->bank_write_cmd;
  402. write_enable(nor);
  403. ret = nor->write_reg(nor, cmd, &bank_sel, 1);
  404. if (ret < 0) {
  405. debug("SF: fail to write bank register\n");
  406. return ret;
  407. }
  408. bar_end:
  409. nor->bank_curr = bank_sel;
  410. return nor->bank_curr;
  411. }
  412. static int read_bar(struct spi_nor *nor, const struct flash_info *info)
  413. {
  414. u8 curr_bank = 0;
  415. int ret;
  416. switch (JEDEC_MFR(info)) {
  417. case SNOR_MFR_SPANSION:
  418. nor->bank_read_cmd = SPINOR_OP_BRRD;
  419. nor->bank_write_cmd = SPINOR_OP_BRWR;
  420. break;
  421. default:
  422. nor->bank_read_cmd = SPINOR_OP_RDEAR;
  423. nor->bank_write_cmd = SPINOR_OP_WREAR;
  424. }
  425. ret = nor->read_reg(nor, nor->bank_read_cmd,
  426. &curr_bank, 1);
  427. if (ret) {
  428. debug("SF: fail to read bank addr register\n");
  429. return ret;
  430. }
  431. nor->bank_curr = curr_bank;
  432. return 0;
  433. }
  434. #endif
  435. /*
  436. * Initiate the erasure of a single sector
  437. */
  438. static int spi_nor_erase_sector(struct spi_nor *nor, u32 addr)
  439. {
  440. struct spi_mem_op op =
  441. SPI_MEM_OP(SPI_MEM_OP_CMD(nor->erase_opcode, 1),
  442. SPI_MEM_OP_ADDR(nor->addr_width, addr, 1),
  443. SPI_MEM_OP_NO_DUMMY,
  444. SPI_MEM_OP_NO_DATA);
  445. if (nor->erase)
  446. return nor->erase(nor, addr);
  447. /*
  448. * Default implementation, if driver doesn't have a specialized HW
  449. * control
  450. */
  451. return spi_mem_exec_op(nor->spi, &op);
  452. }
  453. /*
  454. * Erase an address range on the nor chip. The address range may extend
  455. * one or more erase sectors. Return an error is there is a problem erasing.
  456. */
  457. static int spi_nor_erase(struct mtd_info *mtd, struct erase_info *instr)
  458. {
  459. struct spi_nor *nor = mtd_to_spi_nor(mtd);
  460. u32 addr, len, rem;
  461. int ret;
  462. dev_dbg(nor->dev, "at 0x%llx, len %lld\n", (long long)instr->addr,
  463. (long long)instr->len);
  464. if (!instr->len)
  465. return 0;
  466. div_u64_rem(instr->len, mtd->erasesize, &rem);
  467. if (rem)
  468. return -EINVAL;
  469. addr = instr->addr;
  470. len = instr->len;
  471. while (len) {
  472. #ifdef CONFIG_SPI_FLASH_BAR
  473. ret = write_bar(nor, addr);
  474. if (ret < 0)
  475. return ret;
  476. #endif
  477. write_enable(nor);
  478. ret = spi_nor_erase_sector(nor, addr);
  479. if (ret)
  480. goto erase_err;
  481. addr += mtd->erasesize;
  482. len -= mtd->erasesize;
  483. ret = spi_nor_wait_till_ready(nor);
  484. if (ret)
  485. goto erase_err;
  486. }
  487. erase_err:
  488. #ifdef CONFIG_SPI_FLASH_BAR
  489. ret = clean_bar(nor);
  490. #endif
  491. write_disable(nor);
  492. return ret;
  493. }
  494. #if defined(CONFIG_SPI_FLASH_STMICRO) || defined(CONFIG_SPI_FLASH_SST)
  495. /* Write status register and ensure bits in mask match written values */
  496. static int write_sr_and_check(struct spi_nor *nor, u8 status_new, u8 mask)
  497. {
  498. int ret;
  499. write_enable(nor);
  500. ret = write_sr(nor, status_new);
  501. if (ret)
  502. return ret;
  503. ret = spi_nor_wait_till_ready(nor);
  504. if (ret)
  505. return ret;
  506. ret = read_sr(nor);
  507. if (ret < 0)
  508. return ret;
  509. return ((ret & mask) != (status_new & mask)) ? -EIO : 0;
  510. }
  511. static void stm_get_locked_range(struct spi_nor *nor, u8 sr, loff_t *ofs,
  512. uint64_t *len)
  513. {
  514. struct mtd_info *mtd = &nor->mtd;
  515. u8 mask = SR_BP2 | SR_BP1 | SR_BP0;
  516. int shift = ffs(mask) - 1;
  517. int pow;
  518. if (!(sr & mask)) {
  519. /* No protection */
  520. *ofs = 0;
  521. *len = 0;
  522. } else {
  523. pow = ((sr & mask) ^ mask) >> shift;
  524. *len = mtd->size >> pow;
  525. if (nor->flags & SNOR_F_HAS_SR_TB && sr & SR_TB)
  526. *ofs = 0;
  527. else
  528. *ofs = mtd->size - *len;
  529. }
  530. }
  531. /*
  532. * Return 1 if the entire region is locked (if @locked is true) or unlocked (if
  533. * @locked is false); 0 otherwise
  534. */
  535. static int stm_check_lock_status_sr(struct spi_nor *nor, loff_t ofs, u64 len,
  536. u8 sr, bool locked)
  537. {
  538. loff_t lock_offs;
  539. uint64_t lock_len;
  540. if (!len)
  541. return 1;
  542. stm_get_locked_range(nor, sr, &lock_offs, &lock_len);
  543. if (locked)
  544. /* Requested range is a sub-range of locked range */
  545. return (ofs + len <= lock_offs + lock_len) && (ofs >= lock_offs);
  546. else
  547. /* Requested range does not overlap with locked range */
  548. return (ofs >= lock_offs + lock_len) || (ofs + len <= lock_offs);
  549. }
  550. static int stm_is_locked_sr(struct spi_nor *nor, loff_t ofs, uint64_t len,
  551. u8 sr)
  552. {
  553. return stm_check_lock_status_sr(nor, ofs, len, sr, true);
  554. }
  555. static int stm_is_unlocked_sr(struct spi_nor *nor, loff_t ofs, uint64_t len,
  556. u8 sr)
  557. {
  558. return stm_check_lock_status_sr(nor, ofs, len, sr, false);
  559. }
  560. /*
  561. * Lock a region of the flash. Compatible with ST Micro and similar flash.
  562. * Supports the block protection bits BP{0,1,2} in the status register
  563. * (SR). Does not support these features found in newer SR bitfields:
  564. * - SEC: sector/block protect - only handle SEC=0 (block protect)
  565. * - CMP: complement protect - only support CMP=0 (range is not complemented)
  566. *
  567. * Support for the following is provided conditionally for some flash:
  568. * - TB: top/bottom protect
  569. *
  570. * Sample table portion for 8MB flash (Winbond w25q64fw):
  571. *
  572. * SEC | TB | BP2 | BP1 | BP0 | Prot Length | Protected Portion
  573. * --------------------------------------------------------------------------
  574. * X | X | 0 | 0 | 0 | NONE | NONE
  575. * 0 | 0 | 0 | 0 | 1 | 128 KB | Upper 1/64
  576. * 0 | 0 | 0 | 1 | 0 | 256 KB | Upper 1/32
  577. * 0 | 0 | 0 | 1 | 1 | 512 KB | Upper 1/16
  578. * 0 | 0 | 1 | 0 | 0 | 1 MB | Upper 1/8
  579. * 0 | 0 | 1 | 0 | 1 | 2 MB | Upper 1/4
  580. * 0 | 0 | 1 | 1 | 0 | 4 MB | Upper 1/2
  581. * X | X | 1 | 1 | 1 | 8 MB | ALL
  582. * ------|-------|-------|-------|-------|---------------|-------------------
  583. * 0 | 1 | 0 | 0 | 1 | 128 KB | Lower 1/64
  584. * 0 | 1 | 0 | 1 | 0 | 256 KB | Lower 1/32
  585. * 0 | 1 | 0 | 1 | 1 | 512 KB | Lower 1/16
  586. * 0 | 1 | 1 | 0 | 0 | 1 MB | Lower 1/8
  587. * 0 | 1 | 1 | 0 | 1 | 2 MB | Lower 1/4
  588. * 0 | 1 | 1 | 1 | 0 | 4 MB | Lower 1/2
  589. *
  590. * Returns negative on errors, 0 on success.
  591. */
  592. static int stm_lock(struct spi_nor *nor, loff_t ofs, uint64_t len)
  593. {
  594. struct mtd_info *mtd = &nor->mtd;
  595. int status_old, status_new;
  596. u8 mask = SR_BP2 | SR_BP1 | SR_BP0;
  597. u8 shift = ffs(mask) - 1, pow, val;
  598. loff_t lock_len;
  599. bool can_be_top = true, can_be_bottom = nor->flags & SNOR_F_HAS_SR_TB;
  600. bool use_top;
  601. status_old = read_sr(nor);
  602. if (status_old < 0)
  603. return status_old;
  604. /* If nothing in our range is unlocked, we don't need to do anything */
  605. if (stm_is_locked_sr(nor, ofs, len, status_old))
  606. return 0;
  607. /* If anything below us is unlocked, we can't use 'bottom' protection */
  608. if (!stm_is_locked_sr(nor, 0, ofs, status_old))
  609. can_be_bottom = false;
  610. /* If anything above us is unlocked, we can't use 'top' protection */
  611. if (!stm_is_locked_sr(nor, ofs + len, mtd->size - (ofs + len),
  612. status_old))
  613. can_be_top = false;
  614. if (!can_be_bottom && !can_be_top)
  615. return -EINVAL;
  616. /* Prefer top, if both are valid */
  617. use_top = can_be_top;
  618. /* lock_len: length of region that should end up locked */
  619. if (use_top)
  620. lock_len = mtd->size - ofs;
  621. else
  622. lock_len = ofs + len;
  623. /*
  624. * Need smallest pow such that:
  625. *
  626. * 1 / (2^pow) <= (len / size)
  627. *
  628. * so (assuming power-of-2 size) we do:
  629. *
  630. * pow = ceil(log2(size / len)) = log2(size) - floor(log2(len))
  631. */
  632. pow = ilog2(mtd->size) - ilog2(lock_len);
  633. val = mask - (pow << shift);
  634. if (val & ~mask)
  635. return -EINVAL;
  636. /* Don't "lock" with no region! */
  637. if (!(val & mask))
  638. return -EINVAL;
  639. status_new = (status_old & ~mask & ~SR_TB) | val;
  640. /* Disallow further writes if WP pin is asserted */
  641. status_new |= SR_SRWD;
  642. if (!use_top)
  643. status_new |= SR_TB;
  644. /* Don't bother if they're the same */
  645. if (status_new == status_old)
  646. return 0;
  647. /* Only modify protection if it will not unlock other areas */
  648. if ((status_new & mask) < (status_old & mask))
  649. return -EINVAL;
  650. return write_sr_and_check(nor, status_new, mask);
  651. }
  652. /*
  653. * Unlock a region of the flash. See stm_lock() for more info
  654. *
  655. * Returns negative on errors, 0 on success.
  656. */
  657. static int stm_unlock(struct spi_nor *nor, loff_t ofs, uint64_t len)
  658. {
  659. struct mtd_info *mtd = &nor->mtd;
  660. int status_old, status_new;
  661. u8 mask = SR_BP2 | SR_BP1 | SR_BP0;
  662. u8 shift = ffs(mask) - 1, pow, val;
  663. loff_t lock_len;
  664. bool can_be_top = true, can_be_bottom = nor->flags & SNOR_F_HAS_SR_TB;
  665. bool use_top;
  666. status_old = read_sr(nor);
  667. if (status_old < 0)
  668. return status_old;
  669. /* If nothing in our range is locked, we don't need to do anything */
  670. if (stm_is_unlocked_sr(nor, ofs, len, status_old))
  671. return 0;
  672. /* If anything below us is locked, we can't use 'top' protection */
  673. if (!stm_is_unlocked_sr(nor, 0, ofs, status_old))
  674. can_be_top = false;
  675. /* If anything above us is locked, we can't use 'bottom' protection */
  676. if (!stm_is_unlocked_sr(nor, ofs + len, mtd->size - (ofs + len),
  677. status_old))
  678. can_be_bottom = false;
  679. if (!can_be_bottom && !can_be_top)
  680. return -EINVAL;
  681. /* Prefer top, if both are valid */
  682. use_top = can_be_top;
  683. /* lock_len: length of region that should remain locked */
  684. if (use_top)
  685. lock_len = mtd->size - (ofs + len);
  686. else
  687. lock_len = ofs;
  688. /*
  689. * Need largest pow such that:
  690. *
  691. * 1 / (2^pow) >= (len / size)
  692. *
  693. * so (assuming power-of-2 size) we do:
  694. *
  695. * pow = floor(log2(size / len)) = log2(size) - ceil(log2(len))
  696. */
  697. pow = ilog2(mtd->size) - order_base_2(lock_len);
  698. if (lock_len == 0) {
  699. val = 0; /* fully unlocked */
  700. } else {
  701. val = mask - (pow << shift);
  702. /* Some power-of-two sizes are not supported */
  703. if (val & ~mask)
  704. return -EINVAL;
  705. }
  706. status_new = (status_old & ~mask & ~SR_TB) | val;
  707. /* Don't protect status register if we're fully unlocked */
  708. if (lock_len == 0)
  709. status_new &= ~SR_SRWD;
  710. if (!use_top)
  711. status_new |= SR_TB;
  712. /* Don't bother if they're the same */
  713. if (status_new == status_old)
  714. return 0;
  715. /* Only modify protection if it will not lock other areas */
  716. if ((status_new & mask) > (status_old & mask))
  717. return -EINVAL;
  718. return write_sr_and_check(nor, status_new, mask);
  719. }
  720. /*
  721. * Check if a region of the flash is (completely) locked. See stm_lock() for
  722. * more info.
  723. *
  724. * Returns 1 if entire region is locked, 0 if any portion is unlocked, and
  725. * negative on errors.
  726. */
  727. static int stm_is_locked(struct spi_nor *nor, loff_t ofs, uint64_t len)
  728. {
  729. int status;
  730. status = read_sr(nor);
  731. if (status < 0)
  732. return status;
  733. return stm_is_locked_sr(nor, ofs, len, status);
  734. }
  735. #endif /* CONFIG_SPI_FLASH_STMICRO */
  736. static const struct flash_info *spi_nor_read_id(struct spi_nor *nor)
  737. {
  738. int tmp;
  739. u8 id[SPI_NOR_MAX_ID_LEN];
  740. const struct flash_info *info;
  741. tmp = nor->read_reg(nor, SPINOR_OP_RDID, id, SPI_NOR_MAX_ID_LEN);
  742. if (tmp < 0) {
  743. dev_dbg(nor->dev, "error %d reading JEDEC ID\n", tmp);
  744. return ERR_PTR(tmp);
  745. }
  746. info = spi_nor_ids;
  747. for (; info->name; info++) {
  748. if (info->id_len) {
  749. if (!memcmp(info->id, id, info->id_len))
  750. return info;
  751. }
  752. }
  753. dev_err(nor->dev, "unrecognized JEDEC id bytes: %02x, %02x, %02x\n",
  754. id[0], id[1], id[2]);
  755. return ERR_PTR(-ENODEV);
  756. }
  757. static int spi_nor_read(struct mtd_info *mtd, loff_t from, size_t len,
  758. size_t *retlen, u_char *buf)
  759. {
  760. struct spi_nor *nor = mtd_to_spi_nor(mtd);
  761. int ret;
  762. dev_dbg(nor->dev, "from 0x%08x, len %zd\n", (u32)from, len);
  763. while (len) {
  764. loff_t addr = from;
  765. size_t read_len = len;
  766. #ifdef CONFIG_SPI_FLASH_BAR
  767. u32 remain_len;
  768. ret = write_bar(nor, addr);
  769. if (ret < 0)
  770. return log_ret(ret);
  771. remain_len = (SZ_16M * (nor->bank_curr + 1)) - addr;
  772. if (len < remain_len)
  773. read_len = len;
  774. else
  775. read_len = remain_len;
  776. #endif
  777. ret = nor->read(nor, addr, read_len, buf);
  778. if (ret == 0) {
  779. /* We shouldn't see 0-length reads */
  780. ret = -EIO;
  781. goto read_err;
  782. }
  783. if (ret < 0)
  784. goto read_err;
  785. *retlen += ret;
  786. buf += ret;
  787. from += ret;
  788. len -= ret;
  789. }
  790. ret = 0;
  791. read_err:
  792. #ifdef CONFIG_SPI_FLASH_BAR
  793. ret = clean_bar(nor);
  794. #endif
  795. return ret;
  796. }
  797. #ifdef CONFIG_SPI_FLASH_SST
  798. /*
  799. * sst26 flash series has its own block protection implementation:
  800. * 4x - 8 KByte blocks - read & write protection bits - upper addresses
  801. * 1x - 32 KByte blocks - write protection bits
  802. * rest - 64 KByte blocks - write protection bits
  803. * 1x - 32 KByte blocks - write protection bits
  804. * 4x - 8 KByte blocks - read & write protection bits - lower addresses
  805. *
  806. * We'll support only per 64k lock/unlock so lower and upper 64 KByte region
  807. * will be treated as single block.
  808. */
  809. #define SST26_BPR_8K_NUM 4
  810. #define SST26_MAX_BPR_REG_LEN (18 + 1)
  811. #define SST26_BOUND_REG_SIZE ((32 + SST26_BPR_8K_NUM * 8) * SZ_1K)
  812. enum lock_ctl {
  813. SST26_CTL_LOCK,
  814. SST26_CTL_UNLOCK,
  815. SST26_CTL_CHECK
  816. };
  817. static bool sst26_process_bpr(u32 bpr_size, u8 *cmd, u32 bit, enum lock_ctl ctl)
  818. {
  819. switch (ctl) {
  820. case SST26_CTL_LOCK:
  821. cmd[bpr_size - (bit / 8) - 1] |= BIT(bit % 8);
  822. break;
  823. case SST26_CTL_UNLOCK:
  824. cmd[bpr_size - (bit / 8) - 1] &= ~BIT(bit % 8);
  825. break;
  826. case SST26_CTL_CHECK:
  827. return !!(cmd[bpr_size - (bit / 8) - 1] & BIT(bit % 8));
  828. }
  829. return false;
  830. }
  831. /*
  832. * Lock, unlock or check lock status of the flash region of the flash (depending
  833. * on the lock_ctl value)
  834. */
  835. static int sst26_lock_ctl(struct spi_nor *nor, loff_t ofs, uint64_t len, enum lock_ctl ctl)
  836. {
  837. struct mtd_info *mtd = &nor->mtd;
  838. u32 i, bpr_ptr, rptr_64k, lptr_64k, bpr_size;
  839. bool lower_64k = false, upper_64k = false;
  840. u8 bpr_buff[SST26_MAX_BPR_REG_LEN] = {};
  841. int ret;
  842. /* Check length and offset for 64k alignment */
  843. if ((ofs & (SZ_64K - 1)) || (len & (SZ_64K - 1))) {
  844. dev_err(nor->dev, "length or offset is not 64KiB allighned\n");
  845. return -EINVAL;
  846. }
  847. if (ofs + len > mtd->size) {
  848. dev_err(nor->dev, "range is more than device size: %#llx + %#llx > %#llx\n",
  849. ofs, len, mtd->size);
  850. return -EINVAL;
  851. }
  852. /* SST26 family has only 16 Mbit, 32 Mbit and 64 Mbit IC */
  853. if (mtd->size != SZ_2M &&
  854. mtd->size != SZ_4M &&
  855. mtd->size != SZ_8M)
  856. return -EINVAL;
  857. bpr_size = 2 + (mtd->size / SZ_64K / 8);
  858. ret = nor->read_reg(nor, SPINOR_OP_READ_BPR, bpr_buff, bpr_size);
  859. if (ret < 0) {
  860. dev_err(nor->dev, "fail to read block-protection register\n");
  861. return ret;
  862. }
  863. rptr_64k = min_t(u32, ofs + len, mtd->size - SST26_BOUND_REG_SIZE);
  864. lptr_64k = max_t(u32, ofs, SST26_BOUND_REG_SIZE);
  865. upper_64k = ((ofs + len) > (mtd->size - SST26_BOUND_REG_SIZE));
  866. lower_64k = (ofs < SST26_BOUND_REG_SIZE);
  867. /* Lower bits in block-protection register are about 64k region */
  868. bpr_ptr = lptr_64k / SZ_64K - 1;
  869. /* Process 64K blocks region */
  870. while (lptr_64k < rptr_64k) {
  871. if (sst26_process_bpr(bpr_size, bpr_buff, bpr_ptr, ctl))
  872. return EACCES;
  873. bpr_ptr++;
  874. lptr_64k += SZ_64K;
  875. }
  876. /* 32K and 8K region bits in BPR are after 64k region bits */
  877. bpr_ptr = (mtd->size - 2 * SST26_BOUND_REG_SIZE) / SZ_64K;
  878. /* Process lower 32K block region */
  879. if (lower_64k)
  880. if (sst26_process_bpr(bpr_size, bpr_buff, bpr_ptr, ctl))
  881. return EACCES;
  882. bpr_ptr++;
  883. /* Process upper 32K block region */
  884. if (upper_64k)
  885. if (sst26_process_bpr(bpr_size, bpr_buff, bpr_ptr, ctl))
  886. return EACCES;
  887. bpr_ptr++;
  888. /* Process lower 8K block regions */
  889. for (i = 0; i < SST26_BPR_8K_NUM; i++) {
  890. if (lower_64k)
  891. if (sst26_process_bpr(bpr_size, bpr_buff, bpr_ptr, ctl))
  892. return EACCES;
  893. /* In 8K area BPR has both read and write protection bits */
  894. bpr_ptr += 2;
  895. }
  896. /* Process upper 8K block regions */
  897. for (i = 0; i < SST26_BPR_8K_NUM; i++) {
  898. if (upper_64k)
  899. if (sst26_process_bpr(bpr_size, bpr_buff, bpr_ptr, ctl))
  900. return EACCES;
  901. /* In 8K area BPR has both read and write protection bits */
  902. bpr_ptr += 2;
  903. }
  904. /* If we check region status we don't need to write BPR back */
  905. if (ctl == SST26_CTL_CHECK)
  906. return 0;
  907. ret = nor->write_reg(nor, SPINOR_OP_WRITE_BPR, bpr_buff, bpr_size);
  908. if (ret < 0) {
  909. dev_err(nor->dev, "fail to write block-protection register\n");
  910. return ret;
  911. }
  912. return 0;
  913. }
  914. static int sst26_unlock(struct spi_nor *nor, loff_t ofs, uint64_t len)
  915. {
  916. return sst26_lock_ctl(nor, ofs, len, SST26_CTL_UNLOCK);
  917. }
  918. static int sst26_lock(struct spi_nor *nor, loff_t ofs, uint64_t len)
  919. {
  920. return sst26_lock_ctl(nor, ofs, len, SST26_CTL_LOCK);
  921. }
  922. /*
  923. * Returns EACCES (positive value) if region is locked, 0 if region is unlocked,
  924. * and negative on errors.
  925. */
  926. static int sst26_is_locked(struct spi_nor *nor, loff_t ofs, uint64_t len)
  927. {
  928. /*
  929. * is_locked function is used for check before reading or erasing flash
  930. * region, so offset and length might be not 64k allighned, so adjust
  931. * them to be 64k allighned as sst26_lock_ctl works only with 64k
  932. * allighned regions.
  933. */
  934. ofs -= ofs & (SZ_64K - 1);
  935. len = len & (SZ_64K - 1) ? (len & ~(SZ_64K - 1)) + SZ_64K : len;
  936. return sst26_lock_ctl(nor, ofs, len, SST26_CTL_CHECK);
  937. }
  938. static int sst_write_byteprogram(struct spi_nor *nor, loff_t to, size_t len,
  939. size_t *retlen, const u_char *buf)
  940. {
  941. size_t actual;
  942. int ret = 0;
  943. for (actual = 0; actual < len; actual++) {
  944. nor->program_opcode = SPINOR_OP_BP;
  945. write_enable(nor);
  946. /* write one byte. */
  947. ret = nor->write(nor, to, 1, buf + actual);
  948. if (ret < 0)
  949. goto sst_write_err;
  950. ret = spi_nor_wait_till_ready(nor);
  951. if (ret)
  952. goto sst_write_err;
  953. to++;
  954. }
  955. sst_write_err:
  956. write_disable(nor);
  957. return ret;
  958. }
  959. static int sst_write(struct mtd_info *mtd, loff_t to, size_t len,
  960. size_t *retlen, const u_char *buf)
  961. {
  962. struct spi_nor *nor = mtd_to_spi_nor(mtd);
  963. struct spi_slave *spi = nor->spi;
  964. size_t actual;
  965. int ret;
  966. dev_dbg(nor->dev, "to 0x%08x, len %zd\n", (u32)to, len);
  967. if (spi->mode & SPI_TX_BYTE)
  968. return sst_write_byteprogram(nor, to, len, retlen, buf);
  969. write_enable(nor);
  970. nor->sst_write_second = false;
  971. actual = to % 2;
  972. /* Start write from odd address. */
  973. if (actual) {
  974. nor->program_opcode = SPINOR_OP_BP;
  975. /* write one byte. */
  976. ret = nor->write(nor, to, 1, buf);
  977. if (ret < 0)
  978. goto sst_write_err;
  979. ret = spi_nor_wait_till_ready(nor);
  980. if (ret)
  981. goto sst_write_err;
  982. }
  983. to += actual;
  984. /* Write out most of the data here. */
  985. for (; actual < len - 1; actual += 2) {
  986. nor->program_opcode = SPINOR_OP_AAI_WP;
  987. /* write two bytes. */
  988. ret = nor->write(nor, to, 2, buf + actual);
  989. if (ret < 0)
  990. goto sst_write_err;
  991. ret = spi_nor_wait_till_ready(nor);
  992. if (ret)
  993. goto sst_write_err;
  994. to += 2;
  995. nor->sst_write_second = true;
  996. }
  997. nor->sst_write_second = false;
  998. write_disable(nor);
  999. ret = spi_nor_wait_till_ready(nor);
  1000. if (ret)
  1001. goto sst_write_err;
  1002. /* Write out trailing byte if it exists. */
  1003. if (actual != len) {
  1004. write_enable(nor);
  1005. nor->program_opcode = SPINOR_OP_BP;
  1006. ret = nor->write(nor, to, 1, buf + actual);
  1007. if (ret < 0)
  1008. goto sst_write_err;
  1009. ret = spi_nor_wait_till_ready(nor);
  1010. if (ret)
  1011. goto sst_write_err;
  1012. write_disable(nor);
  1013. actual += 1;
  1014. }
  1015. sst_write_err:
  1016. *retlen += actual;
  1017. return ret;
  1018. }
  1019. #endif
  1020. /*
  1021. * Write an address range to the nor chip. Data must be written in
  1022. * FLASH_PAGESIZE chunks. The address range may be any size provided
  1023. * it is within the physical boundaries.
  1024. */
  1025. static int spi_nor_write(struct mtd_info *mtd, loff_t to, size_t len,
  1026. size_t *retlen, const u_char *buf)
  1027. {
  1028. struct spi_nor *nor = mtd_to_spi_nor(mtd);
  1029. size_t page_offset, page_remain, i;
  1030. ssize_t ret;
  1031. #ifdef CONFIG_SPI_FLASH_SST
  1032. /* sst nor chips use AAI word program */
  1033. if (nor->info->flags & SST_WRITE)
  1034. return sst_write(mtd, to, len, retlen, buf);
  1035. #endif
  1036. dev_dbg(nor->dev, "to 0x%08x, len %zd\n", (u32)to, len);
  1037. if (!len)
  1038. return 0;
  1039. for (i = 0; i < len; ) {
  1040. ssize_t written;
  1041. loff_t addr = to + i;
  1042. /*
  1043. * If page_size is a power of two, the offset can be quickly
  1044. * calculated with an AND operation. On the other cases we
  1045. * need to do a modulus operation (more expensive).
  1046. */
  1047. if (is_power_of_2(nor->page_size)) {
  1048. page_offset = addr & (nor->page_size - 1);
  1049. } else {
  1050. u64 aux = addr;
  1051. page_offset = do_div(aux, nor->page_size);
  1052. }
  1053. /* the size of data remaining on the first page */
  1054. page_remain = min_t(size_t,
  1055. nor->page_size - page_offset, len - i);
  1056. #ifdef CONFIG_SPI_FLASH_BAR
  1057. ret = write_bar(nor, addr);
  1058. if (ret < 0)
  1059. return ret;
  1060. #endif
  1061. write_enable(nor);
  1062. ret = nor->write(nor, addr, page_remain, buf + i);
  1063. if (ret < 0)
  1064. goto write_err;
  1065. written = ret;
  1066. ret = spi_nor_wait_till_ready(nor);
  1067. if (ret)
  1068. goto write_err;
  1069. *retlen += written;
  1070. i += written;
  1071. }
  1072. write_err:
  1073. #ifdef CONFIG_SPI_FLASH_BAR
  1074. ret = clean_bar(nor);
  1075. #endif
  1076. return ret;
  1077. }
  1078. #ifdef CONFIG_SPI_FLASH_MACRONIX
  1079. /**
  1080. * macronix_quad_enable() - set QE bit in Status Register.
  1081. * @nor: pointer to a 'struct spi_nor'
  1082. *
  1083. * Set the Quad Enable (QE) bit in the Status Register.
  1084. *
  1085. * bit 6 of the Status Register is the QE bit for Macronix like QSPI memories.
  1086. *
  1087. * Return: 0 on success, -errno otherwise.
  1088. */
  1089. static int macronix_quad_enable(struct spi_nor *nor)
  1090. {
  1091. int ret, val;
  1092. val = read_sr(nor);
  1093. if (val < 0)
  1094. return val;
  1095. if (val & SR_QUAD_EN_MX)
  1096. return 0;
  1097. write_enable(nor);
  1098. write_sr(nor, val | SR_QUAD_EN_MX);
  1099. ret = spi_nor_wait_till_ready(nor);
  1100. if (ret)
  1101. return ret;
  1102. ret = read_sr(nor);
  1103. if (!(ret > 0 && (ret & SR_QUAD_EN_MX))) {
  1104. dev_err(nor->dev, "Macronix Quad bit not set\n");
  1105. return -EINVAL;
  1106. }
  1107. return 0;
  1108. }
  1109. #endif
  1110. #if defined(CONFIG_SPI_FLASH_SPANSION) || defined(CONFIG_SPI_FLASH_WINBOND)
  1111. /*
  1112. * Write status Register and configuration register with 2 bytes
  1113. * The first byte will be written to the status register, while the
  1114. * second byte will be written to the configuration register.
  1115. * Return negative if error occurred.
  1116. */
  1117. static int write_sr_cr(struct spi_nor *nor, u8 *sr_cr)
  1118. {
  1119. int ret;
  1120. write_enable(nor);
  1121. ret = nor->write_reg(nor, SPINOR_OP_WRSR, sr_cr, 2);
  1122. if (ret < 0) {
  1123. dev_dbg(nor->dev,
  1124. "error while writing configuration register\n");
  1125. return -EINVAL;
  1126. }
  1127. ret = spi_nor_wait_till_ready(nor);
  1128. if (ret) {
  1129. dev_dbg(nor->dev,
  1130. "timeout while writing configuration register\n");
  1131. return ret;
  1132. }
  1133. return 0;
  1134. }
  1135. /**
  1136. * spansion_read_cr_quad_enable() - set QE bit in Configuration Register.
  1137. * @nor: pointer to a 'struct spi_nor'
  1138. *
  1139. * Set the Quad Enable (QE) bit in the Configuration Register.
  1140. * This function should be used with QSPI memories supporting the Read
  1141. * Configuration Register (35h) instruction.
  1142. *
  1143. * bit 1 of the Configuration Register is the QE bit for Spansion like QSPI
  1144. * memories.
  1145. *
  1146. * Return: 0 on success, -errno otherwise.
  1147. */
  1148. static int spansion_read_cr_quad_enable(struct spi_nor *nor)
  1149. {
  1150. u8 sr_cr[2];
  1151. int ret;
  1152. /* Check current Quad Enable bit value. */
  1153. ret = read_cr(nor);
  1154. if (ret < 0) {
  1155. dev_dbg(nor->dev,
  1156. "error while reading configuration register\n");
  1157. return -EINVAL;
  1158. }
  1159. if (ret & CR_QUAD_EN_SPAN)
  1160. return 0;
  1161. sr_cr[1] = ret | CR_QUAD_EN_SPAN;
  1162. /* Keep the current value of the Status Register. */
  1163. ret = read_sr(nor);
  1164. if (ret < 0) {
  1165. dev_dbg(nor->dev, "error while reading status register\n");
  1166. return -EINVAL;
  1167. }
  1168. sr_cr[0] = ret;
  1169. ret = write_sr_cr(nor, sr_cr);
  1170. if (ret)
  1171. return ret;
  1172. /* Read back and check it. */
  1173. ret = read_cr(nor);
  1174. if (!(ret > 0 && (ret & CR_QUAD_EN_SPAN))) {
  1175. dev_dbg(nor->dev, "Spansion Quad bit not set\n");
  1176. return -EINVAL;
  1177. }
  1178. return 0;
  1179. }
  1180. #if CONFIG_IS_ENABLED(SPI_FLASH_SFDP_SUPPORT)
  1181. /**
  1182. * spansion_no_read_cr_quad_enable() - set QE bit in Configuration Register.
  1183. * @nor: pointer to a 'struct spi_nor'
  1184. *
  1185. * Set the Quad Enable (QE) bit in the Configuration Register.
  1186. * This function should be used with QSPI memories not supporting the Read
  1187. * Configuration Register (35h) instruction.
  1188. *
  1189. * bit 1 of the Configuration Register is the QE bit for Spansion like QSPI
  1190. * memories.
  1191. *
  1192. * Return: 0 on success, -errno otherwise.
  1193. */
  1194. static int spansion_no_read_cr_quad_enable(struct spi_nor *nor)
  1195. {
  1196. u8 sr_cr[2];
  1197. int ret;
  1198. /* Keep the current value of the Status Register. */
  1199. ret = read_sr(nor);
  1200. if (ret < 0) {
  1201. dev_dbg(nor->dev, "error while reading status register\n");
  1202. return -EINVAL;
  1203. }
  1204. sr_cr[0] = ret;
  1205. sr_cr[1] = CR_QUAD_EN_SPAN;
  1206. return write_sr_cr(nor, sr_cr);
  1207. }
  1208. #endif /* CONFIG_SPI_FLASH_SFDP_SUPPORT */
  1209. #endif /* CONFIG_SPI_FLASH_SPANSION */
  1210. struct spi_nor_read_command {
  1211. u8 num_mode_clocks;
  1212. u8 num_wait_states;
  1213. u8 opcode;
  1214. enum spi_nor_protocol proto;
  1215. };
  1216. struct spi_nor_pp_command {
  1217. u8 opcode;
  1218. enum spi_nor_protocol proto;
  1219. };
  1220. enum spi_nor_read_command_index {
  1221. SNOR_CMD_READ,
  1222. SNOR_CMD_READ_FAST,
  1223. SNOR_CMD_READ_1_1_1_DTR,
  1224. /* Dual SPI */
  1225. SNOR_CMD_READ_1_1_2,
  1226. SNOR_CMD_READ_1_2_2,
  1227. SNOR_CMD_READ_2_2_2,
  1228. SNOR_CMD_READ_1_2_2_DTR,
  1229. /* Quad SPI */
  1230. SNOR_CMD_READ_1_1_4,
  1231. SNOR_CMD_READ_1_4_4,
  1232. SNOR_CMD_READ_4_4_4,
  1233. SNOR_CMD_READ_1_4_4_DTR,
  1234. /* Octo SPI */
  1235. SNOR_CMD_READ_1_1_8,
  1236. SNOR_CMD_READ_1_8_8,
  1237. SNOR_CMD_READ_8_8_8,
  1238. SNOR_CMD_READ_1_8_8_DTR,
  1239. SNOR_CMD_READ_MAX
  1240. };
  1241. enum spi_nor_pp_command_index {
  1242. SNOR_CMD_PP,
  1243. /* Quad SPI */
  1244. SNOR_CMD_PP_1_1_4,
  1245. SNOR_CMD_PP_1_4_4,
  1246. SNOR_CMD_PP_4_4_4,
  1247. /* Octo SPI */
  1248. SNOR_CMD_PP_1_1_8,
  1249. SNOR_CMD_PP_1_8_8,
  1250. SNOR_CMD_PP_8_8_8,
  1251. SNOR_CMD_PP_MAX
  1252. };
  1253. struct spi_nor_flash_parameter {
  1254. u64 size;
  1255. u32 page_size;
  1256. struct spi_nor_hwcaps hwcaps;
  1257. struct spi_nor_read_command reads[SNOR_CMD_READ_MAX];
  1258. struct spi_nor_pp_command page_programs[SNOR_CMD_PP_MAX];
  1259. int (*quad_enable)(struct spi_nor *nor);
  1260. };
  1261. static void
  1262. spi_nor_set_read_settings(struct spi_nor_read_command *read,
  1263. u8 num_mode_clocks,
  1264. u8 num_wait_states,
  1265. u8 opcode,
  1266. enum spi_nor_protocol proto)
  1267. {
  1268. read->num_mode_clocks = num_mode_clocks;
  1269. read->num_wait_states = num_wait_states;
  1270. read->opcode = opcode;
  1271. read->proto = proto;
  1272. }
  1273. static void
  1274. spi_nor_set_pp_settings(struct spi_nor_pp_command *pp,
  1275. u8 opcode,
  1276. enum spi_nor_protocol proto)
  1277. {
  1278. pp->opcode = opcode;
  1279. pp->proto = proto;
  1280. }
  1281. #if CONFIG_IS_ENABLED(SPI_FLASH_SFDP_SUPPORT)
  1282. /*
  1283. * Serial Flash Discoverable Parameters (SFDP) parsing.
  1284. */
  1285. /**
  1286. * spi_nor_read_sfdp() - read Serial Flash Discoverable Parameters.
  1287. * @nor: pointer to a 'struct spi_nor'
  1288. * @addr: offset in the SFDP area to start reading data from
  1289. * @len: number of bytes to read
  1290. * @buf: buffer where the SFDP data are copied into (dma-safe memory)
  1291. *
  1292. * Whatever the actual numbers of bytes for address and dummy cycles are
  1293. * for (Fast) Read commands, the Read SFDP (5Ah) instruction is always
  1294. * followed by a 3-byte address and 8 dummy clock cycles.
  1295. *
  1296. * Return: 0 on success, -errno otherwise.
  1297. */
  1298. static int spi_nor_read_sfdp(struct spi_nor *nor, u32 addr,
  1299. size_t len, void *buf)
  1300. {
  1301. u8 addr_width, read_opcode, read_dummy;
  1302. int ret;
  1303. read_opcode = nor->read_opcode;
  1304. addr_width = nor->addr_width;
  1305. read_dummy = nor->read_dummy;
  1306. nor->read_opcode = SPINOR_OP_RDSFDP;
  1307. nor->addr_width = 3;
  1308. nor->read_dummy = 8;
  1309. while (len) {
  1310. ret = nor->read(nor, addr, len, (u8 *)buf);
  1311. if (!ret || ret > len) {
  1312. ret = -EIO;
  1313. goto read_err;
  1314. }
  1315. if (ret < 0)
  1316. goto read_err;
  1317. buf += ret;
  1318. addr += ret;
  1319. len -= ret;
  1320. }
  1321. ret = 0;
  1322. read_err:
  1323. nor->read_opcode = read_opcode;
  1324. nor->addr_width = addr_width;
  1325. nor->read_dummy = read_dummy;
  1326. return ret;
  1327. }
  1328. struct sfdp_parameter_header {
  1329. u8 id_lsb;
  1330. u8 minor;
  1331. u8 major;
  1332. u8 length; /* in double words */
  1333. u8 parameter_table_pointer[3]; /* byte address */
  1334. u8 id_msb;
  1335. };
  1336. #define SFDP_PARAM_HEADER_ID(p) (((p)->id_msb << 8) | (p)->id_lsb)
  1337. #define SFDP_PARAM_HEADER_PTP(p) \
  1338. (((p)->parameter_table_pointer[2] << 16) | \
  1339. ((p)->parameter_table_pointer[1] << 8) | \
  1340. ((p)->parameter_table_pointer[0] << 0))
  1341. #define SFDP_BFPT_ID 0xff00 /* Basic Flash Parameter Table */
  1342. #define SFDP_SECTOR_MAP_ID 0xff81 /* Sector Map Table */
  1343. #define SFDP_SST_ID 0x01bf /* Manufacturer specific Table */
  1344. #define SFDP_SIGNATURE 0x50444653U
  1345. #define SFDP_JESD216_MAJOR 1
  1346. #define SFDP_JESD216_MINOR 0
  1347. #define SFDP_JESD216A_MINOR 5
  1348. #define SFDP_JESD216B_MINOR 6
  1349. struct sfdp_header {
  1350. u32 signature; /* Ox50444653U <=> "SFDP" */
  1351. u8 minor;
  1352. u8 major;
  1353. u8 nph; /* 0-base number of parameter headers */
  1354. u8 unused;
  1355. /* Basic Flash Parameter Table. */
  1356. struct sfdp_parameter_header bfpt_header;
  1357. };
  1358. /* Basic Flash Parameter Table */
  1359. /*
  1360. * JESD216 rev B defines a Basic Flash Parameter Table of 16 DWORDs.
  1361. * They are indexed from 1 but C arrays are indexed from 0.
  1362. */
  1363. #define BFPT_DWORD(i) ((i) - 1)
  1364. #define BFPT_DWORD_MAX 16
  1365. /* The first version of JESB216 defined only 9 DWORDs. */
  1366. #define BFPT_DWORD_MAX_JESD216 9
  1367. /* 1st DWORD. */
  1368. #define BFPT_DWORD1_FAST_READ_1_1_2 BIT(16)
  1369. #define BFPT_DWORD1_ADDRESS_BYTES_MASK GENMASK(18, 17)
  1370. #define BFPT_DWORD1_ADDRESS_BYTES_3_ONLY (0x0UL << 17)
  1371. #define BFPT_DWORD1_ADDRESS_BYTES_3_OR_4 (0x1UL << 17)
  1372. #define BFPT_DWORD1_ADDRESS_BYTES_4_ONLY (0x2UL << 17)
  1373. #define BFPT_DWORD1_DTR BIT(19)
  1374. #define BFPT_DWORD1_FAST_READ_1_2_2 BIT(20)
  1375. #define BFPT_DWORD1_FAST_READ_1_4_4 BIT(21)
  1376. #define BFPT_DWORD1_FAST_READ_1_1_4 BIT(22)
  1377. /* 5th DWORD. */
  1378. #define BFPT_DWORD5_FAST_READ_2_2_2 BIT(0)
  1379. #define BFPT_DWORD5_FAST_READ_4_4_4 BIT(4)
  1380. /* 11th DWORD. */
  1381. #define BFPT_DWORD11_PAGE_SIZE_SHIFT 4
  1382. #define BFPT_DWORD11_PAGE_SIZE_MASK GENMASK(7, 4)
  1383. /* 15th DWORD. */
  1384. /*
  1385. * (from JESD216 rev B)
  1386. * Quad Enable Requirements (QER):
  1387. * - 000b: Device does not have a QE bit. Device detects 1-1-4 and 1-4-4
  1388. * reads based on instruction. DQ3/HOLD# functions are hold during
  1389. * instruction phase.
  1390. * - 001b: QE is bit 1 of status register 2. It is set via Write Status with
  1391. * two data bytes where bit 1 of the second byte is one.
  1392. * [...]
  1393. * Writing only one byte to the status register has the side-effect of
  1394. * clearing status register 2, including the QE bit. The 100b code is
  1395. * used if writing one byte to the status register does not modify
  1396. * status register 2.
  1397. * - 010b: QE is bit 6 of status register 1. It is set via Write Status with
  1398. * one data byte where bit 6 is one.
  1399. * [...]
  1400. * - 011b: QE is bit 7 of status register 2. It is set via Write status
  1401. * register 2 instruction 3Eh with one data byte where bit 7 is one.
  1402. * [...]
  1403. * The status register 2 is read using instruction 3Fh.
  1404. * - 100b: QE is bit 1 of status register 2. It is set via Write Status with
  1405. * two data bytes where bit 1 of the second byte is one.
  1406. * [...]
  1407. * In contrast to the 001b code, writing one byte to the status
  1408. * register does not modify status register 2.
  1409. * - 101b: QE is bit 1 of status register 2. Status register 1 is read using
  1410. * Read Status instruction 05h. Status register2 is read using
  1411. * instruction 35h. QE is set via Writ Status instruction 01h with
  1412. * two data bytes where bit 1 of the second byte is one.
  1413. * [...]
  1414. */
  1415. #define BFPT_DWORD15_QER_MASK GENMASK(22, 20)
  1416. #define BFPT_DWORD15_QER_NONE (0x0UL << 20) /* Micron */
  1417. #define BFPT_DWORD15_QER_SR2_BIT1_BUGGY (0x1UL << 20)
  1418. #define BFPT_DWORD15_QER_SR1_BIT6 (0x2UL << 20) /* Macronix */
  1419. #define BFPT_DWORD15_QER_SR2_BIT7 (0x3UL << 20)
  1420. #define BFPT_DWORD15_QER_SR2_BIT1_NO_RD (0x4UL << 20)
  1421. #define BFPT_DWORD15_QER_SR2_BIT1 (0x5UL << 20) /* Spansion */
  1422. struct sfdp_bfpt {
  1423. u32 dwords[BFPT_DWORD_MAX];
  1424. };
  1425. /* Fast Read settings. */
  1426. static void
  1427. spi_nor_set_read_settings_from_bfpt(struct spi_nor_read_command *read,
  1428. u16 half,
  1429. enum spi_nor_protocol proto)
  1430. {
  1431. read->num_mode_clocks = (half >> 5) & 0x07;
  1432. read->num_wait_states = (half >> 0) & 0x1f;
  1433. read->opcode = (half >> 8) & 0xff;
  1434. read->proto = proto;
  1435. }
  1436. struct sfdp_bfpt_read {
  1437. /* The Fast Read x-y-z hardware capability in params->hwcaps.mask. */
  1438. u32 hwcaps;
  1439. /*
  1440. * The <supported_bit> bit in <supported_dword> BFPT DWORD tells us
  1441. * whether the Fast Read x-y-z command is supported.
  1442. */
  1443. u32 supported_dword;
  1444. u32 supported_bit;
  1445. /*
  1446. * The half-word at offset <setting_shift> in <setting_dword> BFPT DWORD
  1447. * encodes the op code, the number of mode clocks and the number of wait
  1448. * states to be used by Fast Read x-y-z command.
  1449. */
  1450. u32 settings_dword;
  1451. u32 settings_shift;
  1452. /* The SPI protocol for this Fast Read x-y-z command. */
  1453. enum spi_nor_protocol proto;
  1454. };
  1455. static const struct sfdp_bfpt_read sfdp_bfpt_reads[] = {
  1456. /* Fast Read 1-1-2 */
  1457. {
  1458. SNOR_HWCAPS_READ_1_1_2,
  1459. BFPT_DWORD(1), BIT(16), /* Supported bit */
  1460. BFPT_DWORD(4), 0, /* Settings */
  1461. SNOR_PROTO_1_1_2,
  1462. },
  1463. /* Fast Read 1-2-2 */
  1464. {
  1465. SNOR_HWCAPS_READ_1_2_2,
  1466. BFPT_DWORD(1), BIT(20), /* Supported bit */
  1467. BFPT_DWORD(4), 16, /* Settings */
  1468. SNOR_PROTO_1_2_2,
  1469. },
  1470. /* Fast Read 2-2-2 */
  1471. {
  1472. SNOR_HWCAPS_READ_2_2_2,
  1473. BFPT_DWORD(5), BIT(0), /* Supported bit */
  1474. BFPT_DWORD(6), 16, /* Settings */
  1475. SNOR_PROTO_2_2_2,
  1476. },
  1477. /* Fast Read 1-1-4 */
  1478. {
  1479. SNOR_HWCAPS_READ_1_1_4,
  1480. BFPT_DWORD(1), BIT(22), /* Supported bit */
  1481. BFPT_DWORD(3), 16, /* Settings */
  1482. SNOR_PROTO_1_1_4,
  1483. },
  1484. /* Fast Read 1-4-4 */
  1485. {
  1486. SNOR_HWCAPS_READ_1_4_4,
  1487. BFPT_DWORD(1), BIT(21), /* Supported bit */
  1488. BFPT_DWORD(3), 0, /* Settings */
  1489. SNOR_PROTO_1_4_4,
  1490. },
  1491. /* Fast Read 4-4-4 */
  1492. {
  1493. SNOR_HWCAPS_READ_4_4_4,
  1494. BFPT_DWORD(5), BIT(4), /* Supported bit */
  1495. BFPT_DWORD(7), 16, /* Settings */
  1496. SNOR_PROTO_4_4_4,
  1497. },
  1498. };
  1499. struct sfdp_bfpt_erase {
  1500. /*
  1501. * The half-word at offset <shift> in DWORD <dwoard> encodes the
  1502. * op code and erase sector size to be used by Sector Erase commands.
  1503. */
  1504. u32 dword;
  1505. u32 shift;
  1506. };
  1507. static const struct sfdp_bfpt_erase sfdp_bfpt_erases[] = {
  1508. /* Erase Type 1 in DWORD8 bits[15:0] */
  1509. {BFPT_DWORD(8), 0},
  1510. /* Erase Type 2 in DWORD8 bits[31:16] */
  1511. {BFPT_DWORD(8), 16},
  1512. /* Erase Type 3 in DWORD9 bits[15:0] */
  1513. {BFPT_DWORD(9), 0},
  1514. /* Erase Type 4 in DWORD9 bits[31:16] */
  1515. {BFPT_DWORD(9), 16},
  1516. };
  1517. static int spi_nor_hwcaps_read2cmd(u32 hwcaps);
  1518. /**
  1519. * spi_nor_parse_bfpt() - read and parse the Basic Flash Parameter Table.
  1520. * @nor: pointer to a 'struct spi_nor'
  1521. * @bfpt_header: pointer to the 'struct sfdp_parameter_header' describing
  1522. * the Basic Flash Parameter Table length and version
  1523. * @params: pointer to the 'struct spi_nor_flash_parameter' to be
  1524. * filled
  1525. *
  1526. * The Basic Flash Parameter Table is the main and only mandatory table as
  1527. * defined by the SFDP (JESD216) specification.
  1528. * It provides us with the total size (memory density) of the data array and
  1529. * the number of address bytes for Fast Read, Page Program and Sector Erase
  1530. * commands.
  1531. * For Fast READ commands, it also gives the number of mode clock cycles and
  1532. * wait states (regrouped in the number of dummy clock cycles) for each
  1533. * supported instruction op code.
  1534. * For Page Program, the page size is now available since JESD216 rev A, however
  1535. * the supported instruction op codes are still not provided.
  1536. * For Sector Erase commands, this table stores the supported instruction op
  1537. * codes and the associated sector sizes.
  1538. * Finally, the Quad Enable Requirements (QER) are also available since JESD216
  1539. * rev A. The QER bits encode the manufacturer dependent procedure to be
  1540. * executed to set the Quad Enable (QE) bit in some internal register of the
  1541. * Quad SPI memory. Indeed the QE bit, when it exists, must be set before
  1542. * sending any Quad SPI command to the memory. Actually, setting the QE bit
  1543. * tells the memory to reassign its WP# and HOLD#/RESET# pins to functions IO2
  1544. * and IO3 hence enabling 4 (Quad) I/O lines.
  1545. *
  1546. * Return: 0 on success, -errno otherwise.
  1547. */
  1548. static int spi_nor_parse_bfpt(struct spi_nor *nor,
  1549. const struct sfdp_parameter_header *bfpt_header,
  1550. struct spi_nor_flash_parameter *params)
  1551. {
  1552. struct mtd_info *mtd = &nor->mtd;
  1553. struct sfdp_bfpt bfpt;
  1554. size_t len;
  1555. int i, cmd, err;
  1556. u32 addr;
  1557. u16 half;
  1558. /* JESD216 Basic Flash Parameter Table length is at least 9 DWORDs. */
  1559. if (bfpt_header->length < BFPT_DWORD_MAX_JESD216)
  1560. return -EINVAL;
  1561. /* Read the Basic Flash Parameter Table. */
  1562. len = min_t(size_t, sizeof(bfpt),
  1563. bfpt_header->length * sizeof(u32));
  1564. addr = SFDP_PARAM_HEADER_PTP(bfpt_header);
  1565. memset(&bfpt, 0, sizeof(bfpt));
  1566. err = spi_nor_read_sfdp(nor, addr, len, &bfpt);
  1567. if (err < 0)
  1568. return err;
  1569. /* Fix endianness of the BFPT DWORDs. */
  1570. for (i = 0; i < BFPT_DWORD_MAX; i++)
  1571. bfpt.dwords[i] = le32_to_cpu(bfpt.dwords[i]);
  1572. /* Number of address bytes. */
  1573. switch (bfpt.dwords[BFPT_DWORD(1)] & BFPT_DWORD1_ADDRESS_BYTES_MASK) {
  1574. case BFPT_DWORD1_ADDRESS_BYTES_3_ONLY:
  1575. nor->addr_width = 3;
  1576. break;
  1577. case BFPT_DWORD1_ADDRESS_BYTES_4_ONLY:
  1578. nor->addr_width = 4;
  1579. break;
  1580. default:
  1581. break;
  1582. }
  1583. /* Flash Memory Density (in bits). */
  1584. params->size = bfpt.dwords[BFPT_DWORD(2)];
  1585. if (params->size & BIT(31)) {
  1586. params->size &= ~BIT(31);
  1587. /*
  1588. * Prevent overflows on params->size. Anyway, a NOR of 2^64
  1589. * bits is unlikely to exist so this error probably means
  1590. * the BFPT we are reading is corrupted/wrong.
  1591. */
  1592. if (params->size > 63)
  1593. return -EINVAL;
  1594. params->size = 1ULL << params->size;
  1595. } else {
  1596. params->size++;
  1597. }
  1598. params->size >>= 3; /* Convert to bytes. */
  1599. /* Fast Read settings. */
  1600. for (i = 0; i < ARRAY_SIZE(sfdp_bfpt_reads); i++) {
  1601. const struct sfdp_bfpt_read *rd = &sfdp_bfpt_reads[i];
  1602. struct spi_nor_read_command *read;
  1603. if (!(bfpt.dwords[rd->supported_dword] & rd->supported_bit)) {
  1604. params->hwcaps.mask &= ~rd->hwcaps;
  1605. continue;
  1606. }
  1607. params->hwcaps.mask |= rd->hwcaps;
  1608. cmd = spi_nor_hwcaps_read2cmd(rd->hwcaps);
  1609. read = &params->reads[cmd];
  1610. half = bfpt.dwords[rd->settings_dword] >> rd->settings_shift;
  1611. spi_nor_set_read_settings_from_bfpt(read, half, rd->proto);
  1612. }
  1613. /* Sector Erase settings. */
  1614. for (i = 0; i < ARRAY_SIZE(sfdp_bfpt_erases); i++) {
  1615. const struct sfdp_bfpt_erase *er = &sfdp_bfpt_erases[i];
  1616. u32 erasesize;
  1617. u8 opcode;
  1618. half = bfpt.dwords[er->dword] >> er->shift;
  1619. erasesize = half & 0xff;
  1620. /* erasesize == 0 means this Erase Type is not supported. */
  1621. if (!erasesize)
  1622. continue;
  1623. erasesize = 1U << erasesize;
  1624. opcode = (half >> 8) & 0xff;
  1625. #ifdef CONFIG_SPI_FLASH_USE_4K_SECTORS
  1626. if (erasesize == SZ_4K) {
  1627. nor->erase_opcode = opcode;
  1628. mtd->erasesize = erasesize;
  1629. break;
  1630. }
  1631. #endif
  1632. if (!mtd->erasesize || mtd->erasesize < erasesize) {
  1633. nor->erase_opcode = opcode;
  1634. mtd->erasesize = erasesize;
  1635. }
  1636. }
  1637. /* Stop here if not JESD216 rev A or later. */
  1638. if (bfpt_header->length < BFPT_DWORD_MAX)
  1639. return 0;
  1640. /* Page size: this field specifies 'N' so the page size = 2^N bytes. */
  1641. params->page_size = bfpt.dwords[BFPT_DWORD(11)];
  1642. params->page_size &= BFPT_DWORD11_PAGE_SIZE_MASK;
  1643. params->page_size >>= BFPT_DWORD11_PAGE_SIZE_SHIFT;
  1644. params->page_size = 1U << params->page_size;
  1645. /* Quad Enable Requirements. */
  1646. switch (bfpt.dwords[BFPT_DWORD(15)] & BFPT_DWORD15_QER_MASK) {
  1647. case BFPT_DWORD15_QER_NONE:
  1648. params->quad_enable = NULL;
  1649. break;
  1650. #if defined(CONFIG_SPI_FLASH_SPANSION) || defined(CONFIG_SPI_FLASH_WINBOND)
  1651. case BFPT_DWORD15_QER_SR2_BIT1_BUGGY:
  1652. case BFPT_DWORD15_QER_SR2_BIT1_NO_RD:
  1653. params->quad_enable = spansion_no_read_cr_quad_enable;
  1654. break;
  1655. #endif
  1656. #ifdef CONFIG_SPI_FLASH_MACRONIX
  1657. case BFPT_DWORD15_QER_SR1_BIT6:
  1658. params->quad_enable = macronix_quad_enable;
  1659. break;
  1660. #endif
  1661. #if defined(CONFIG_SPI_FLASH_SPANSION) || defined(CONFIG_SPI_FLASH_WINBOND)
  1662. case BFPT_DWORD15_QER_SR2_BIT1:
  1663. params->quad_enable = spansion_read_cr_quad_enable;
  1664. break;
  1665. #endif
  1666. default:
  1667. return -EINVAL;
  1668. }
  1669. return 0;
  1670. }
  1671. /**
  1672. * spi_nor_parse_microchip_sfdp() - parse the Microchip manufacturer specific
  1673. * SFDP table.
  1674. * @nor: pointer to a 'struct spi_nor'.
  1675. * @param_header: pointer to the SFDP parameter header.
  1676. *
  1677. * Return: 0 on success, -errno otherwise.
  1678. */
  1679. static int
  1680. spi_nor_parse_microchip_sfdp(struct spi_nor *nor,
  1681. const struct sfdp_parameter_header *param_header)
  1682. {
  1683. size_t size;
  1684. u32 addr;
  1685. int ret;
  1686. size = param_header->length * sizeof(u32);
  1687. addr = SFDP_PARAM_HEADER_PTP(param_header);
  1688. nor->manufacturer_sfdp = devm_kmalloc(nor->dev, size, GFP_KERNEL);
  1689. if (!nor->manufacturer_sfdp)
  1690. return -ENOMEM;
  1691. ret = spi_nor_read_sfdp(nor, addr, size, nor->manufacturer_sfdp);
  1692. return ret;
  1693. }
  1694. /**
  1695. * spi_nor_parse_sfdp() - parse the Serial Flash Discoverable Parameters.
  1696. * @nor: pointer to a 'struct spi_nor'
  1697. * @params: pointer to the 'struct spi_nor_flash_parameter' to be
  1698. * filled
  1699. *
  1700. * The Serial Flash Discoverable Parameters are described by the JEDEC JESD216
  1701. * specification. This is a standard which tends to supported by almost all
  1702. * (Q)SPI memory manufacturers. Those hard-coded tables allow us to learn at
  1703. * runtime the main parameters needed to perform basic SPI flash operations such
  1704. * as Fast Read, Page Program or Sector Erase commands.
  1705. *
  1706. * Return: 0 on success, -errno otherwise.
  1707. */
  1708. static int spi_nor_parse_sfdp(struct spi_nor *nor,
  1709. struct spi_nor_flash_parameter *params)
  1710. {
  1711. const struct sfdp_parameter_header *param_header, *bfpt_header;
  1712. struct sfdp_parameter_header *param_headers = NULL;
  1713. struct sfdp_header header;
  1714. size_t psize;
  1715. int i, err;
  1716. /* Get the SFDP header. */
  1717. err = spi_nor_read_sfdp(nor, 0, sizeof(header), &header);
  1718. if (err < 0)
  1719. return err;
  1720. /* Check the SFDP header version. */
  1721. if (le32_to_cpu(header.signature) != SFDP_SIGNATURE ||
  1722. header.major != SFDP_JESD216_MAJOR)
  1723. return -EINVAL;
  1724. /*
  1725. * Verify that the first and only mandatory parameter header is a
  1726. * Basic Flash Parameter Table header as specified in JESD216.
  1727. */
  1728. bfpt_header = &header.bfpt_header;
  1729. if (SFDP_PARAM_HEADER_ID(bfpt_header) != SFDP_BFPT_ID ||
  1730. bfpt_header->major != SFDP_JESD216_MAJOR)
  1731. return -EINVAL;
  1732. /*
  1733. * Allocate memory then read all parameter headers with a single
  1734. * Read SFDP command. These parameter headers will actually be parsed
  1735. * twice: a first time to get the latest revision of the basic flash
  1736. * parameter table, then a second time to handle the supported optional
  1737. * tables.
  1738. * Hence we read the parameter headers once for all to reduce the
  1739. * processing time. Also we use kmalloc() instead of devm_kmalloc()
  1740. * because we don't need to keep these parameter headers: the allocated
  1741. * memory is always released with kfree() before exiting this function.
  1742. */
  1743. if (header.nph) {
  1744. psize = header.nph * sizeof(*param_headers);
  1745. param_headers = kmalloc(psize, GFP_KERNEL);
  1746. if (!param_headers)
  1747. return -ENOMEM;
  1748. err = spi_nor_read_sfdp(nor, sizeof(header),
  1749. psize, param_headers);
  1750. if (err < 0) {
  1751. dev_err(nor->dev,
  1752. "failed to read SFDP parameter headers\n");
  1753. goto exit;
  1754. }
  1755. }
  1756. /*
  1757. * Check other parameter headers to get the latest revision of
  1758. * the basic flash parameter table.
  1759. */
  1760. for (i = 0; i < header.nph; i++) {
  1761. param_header = &param_headers[i];
  1762. if (SFDP_PARAM_HEADER_ID(param_header) == SFDP_BFPT_ID &&
  1763. param_header->major == SFDP_JESD216_MAJOR &&
  1764. (param_header->minor > bfpt_header->minor ||
  1765. (param_header->minor == bfpt_header->minor &&
  1766. param_header->length > bfpt_header->length)))
  1767. bfpt_header = param_header;
  1768. }
  1769. err = spi_nor_parse_bfpt(nor, bfpt_header, params);
  1770. if (err)
  1771. goto exit;
  1772. /* Parse other parameter headers. */
  1773. for (i = 0; i < header.nph; i++) {
  1774. param_header = &param_headers[i];
  1775. switch (SFDP_PARAM_HEADER_ID(param_header)) {
  1776. case SFDP_SECTOR_MAP_ID:
  1777. dev_info(nor->dev,
  1778. "non-uniform erase sector maps are not supported yet.\n");
  1779. break;
  1780. case SFDP_SST_ID:
  1781. err = spi_nor_parse_microchip_sfdp(nor, param_header);
  1782. break;
  1783. default:
  1784. break;
  1785. }
  1786. if (err) {
  1787. dev_warn(nor->dev,
  1788. "Failed to parse optional parameter table: %04x\n",
  1789. SFDP_PARAM_HEADER_ID(param_header));
  1790. /*
  1791. * Let's not drop all information we extracted so far
  1792. * if optional table parsers fail. In case of failing,
  1793. * each optional parser is responsible to roll back to
  1794. * the previously known spi_nor data.
  1795. */
  1796. err = 0;
  1797. }
  1798. }
  1799. exit:
  1800. kfree(param_headers);
  1801. return err;
  1802. }
  1803. #else
  1804. static int spi_nor_parse_sfdp(struct spi_nor *nor,
  1805. struct spi_nor_flash_parameter *params)
  1806. {
  1807. return -EINVAL;
  1808. }
  1809. #endif /* SPI_FLASH_SFDP_SUPPORT */
  1810. static int spi_nor_init_params(struct spi_nor *nor,
  1811. const struct flash_info *info,
  1812. struct spi_nor_flash_parameter *params)
  1813. {
  1814. /* Set legacy flash parameters as default. */
  1815. memset(params, 0, sizeof(*params));
  1816. /* Set SPI NOR sizes. */
  1817. params->size = info->sector_size * info->n_sectors;
  1818. params->page_size = info->page_size;
  1819. /* (Fast) Read settings. */
  1820. params->hwcaps.mask |= SNOR_HWCAPS_READ;
  1821. spi_nor_set_read_settings(&params->reads[SNOR_CMD_READ],
  1822. 0, 0, SPINOR_OP_READ,
  1823. SNOR_PROTO_1_1_1);
  1824. if (!(info->flags & SPI_NOR_NO_FR)) {
  1825. params->hwcaps.mask |= SNOR_HWCAPS_READ_FAST;
  1826. spi_nor_set_read_settings(&params->reads[SNOR_CMD_READ_FAST],
  1827. 0, 8, SPINOR_OP_READ_FAST,
  1828. SNOR_PROTO_1_1_1);
  1829. }
  1830. if (info->flags & SPI_NOR_DUAL_READ) {
  1831. params->hwcaps.mask |= SNOR_HWCAPS_READ_1_1_2;
  1832. spi_nor_set_read_settings(&params->reads[SNOR_CMD_READ_1_1_2],
  1833. 0, 8, SPINOR_OP_READ_1_1_2,
  1834. SNOR_PROTO_1_1_2);
  1835. }
  1836. if (info->flags & SPI_NOR_QUAD_READ) {
  1837. params->hwcaps.mask |= SNOR_HWCAPS_READ_1_1_4;
  1838. spi_nor_set_read_settings(&params->reads[SNOR_CMD_READ_1_1_4],
  1839. 0, 8, SPINOR_OP_READ_1_1_4,
  1840. SNOR_PROTO_1_1_4);
  1841. }
  1842. if (info->flags & SPI_NOR_OCTAL_READ) {
  1843. params->hwcaps.mask |= SNOR_HWCAPS_READ_1_1_8;
  1844. spi_nor_set_read_settings(&params->reads[SNOR_CMD_READ_1_1_8],
  1845. 0, 8, SPINOR_OP_READ_1_1_8,
  1846. SNOR_PROTO_1_1_8);
  1847. }
  1848. /* Page Program settings. */
  1849. params->hwcaps.mask |= SNOR_HWCAPS_PP;
  1850. spi_nor_set_pp_settings(&params->page_programs[SNOR_CMD_PP],
  1851. SPINOR_OP_PP, SNOR_PROTO_1_1_1);
  1852. if (info->flags & SPI_NOR_QUAD_READ) {
  1853. params->hwcaps.mask |= SNOR_HWCAPS_PP_1_1_4;
  1854. spi_nor_set_pp_settings(&params->page_programs[SNOR_CMD_PP_1_1_4],
  1855. SPINOR_OP_PP_1_1_4, SNOR_PROTO_1_1_4);
  1856. }
  1857. /* Select the procedure to set the Quad Enable bit. */
  1858. if (params->hwcaps.mask & (SNOR_HWCAPS_READ_QUAD |
  1859. SNOR_HWCAPS_PP_QUAD)) {
  1860. switch (JEDEC_MFR(info)) {
  1861. #ifdef CONFIG_SPI_FLASH_MACRONIX
  1862. case SNOR_MFR_MACRONIX:
  1863. params->quad_enable = macronix_quad_enable;
  1864. break;
  1865. #endif
  1866. case SNOR_MFR_ST:
  1867. case SNOR_MFR_MICRON:
  1868. break;
  1869. default:
  1870. #if defined(CONFIG_SPI_FLASH_SPANSION) || defined(CONFIG_SPI_FLASH_WINBOND)
  1871. /* Kept only for backward compatibility purpose. */
  1872. params->quad_enable = spansion_read_cr_quad_enable;
  1873. #endif
  1874. break;
  1875. }
  1876. }
  1877. /* Override the parameters with data read from SFDP tables. */
  1878. nor->addr_width = 0;
  1879. nor->mtd.erasesize = 0;
  1880. if ((info->flags & (SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ)) &&
  1881. !(info->flags & SPI_NOR_SKIP_SFDP)) {
  1882. struct spi_nor_flash_parameter sfdp_params;
  1883. memcpy(&sfdp_params, params, sizeof(sfdp_params));
  1884. if (spi_nor_parse_sfdp(nor, &sfdp_params)) {
  1885. nor->addr_width = 0;
  1886. nor->mtd.erasesize = 0;
  1887. } else {
  1888. memcpy(params, &sfdp_params, sizeof(*params));
  1889. }
  1890. }
  1891. return 0;
  1892. }
  1893. static int spi_nor_hwcaps2cmd(u32 hwcaps, const int table[][2], size_t size)
  1894. {
  1895. size_t i;
  1896. for (i = 0; i < size; i++)
  1897. if (table[i][0] == (int)hwcaps)
  1898. return table[i][1];
  1899. return -EINVAL;
  1900. }
  1901. static int spi_nor_hwcaps_read2cmd(u32 hwcaps)
  1902. {
  1903. static const int hwcaps_read2cmd[][2] = {
  1904. { SNOR_HWCAPS_READ, SNOR_CMD_READ },
  1905. { SNOR_HWCAPS_READ_FAST, SNOR_CMD_READ_FAST },
  1906. { SNOR_HWCAPS_READ_1_1_1_DTR, SNOR_CMD_READ_1_1_1_DTR },
  1907. { SNOR_HWCAPS_READ_1_1_2, SNOR_CMD_READ_1_1_2 },
  1908. { SNOR_HWCAPS_READ_1_2_2, SNOR_CMD_READ_1_2_2 },
  1909. { SNOR_HWCAPS_READ_2_2_2, SNOR_CMD_READ_2_2_2 },
  1910. { SNOR_HWCAPS_READ_1_2_2_DTR, SNOR_CMD_READ_1_2_2_DTR },
  1911. { SNOR_HWCAPS_READ_1_1_4, SNOR_CMD_READ_1_1_4 },
  1912. { SNOR_HWCAPS_READ_1_4_4, SNOR_CMD_READ_1_4_4 },
  1913. { SNOR_HWCAPS_READ_4_4_4, SNOR_CMD_READ_4_4_4 },
  1914. { SNOR_HWCAPS_READ_1_4_4_DTR, SNOR_CMD_READ_1_4_4_DTR },
  1915. { SNOR_HWCAPS_READ_1_1_8, SNOR_CMD_READ_1_1_8 },
  1916. { SNOR_HWCAPS_READ_1_8_8, SNOR_CMD_READ_1_8_8 },
  1917. { SNOR_HWCAPS_READ_8_8_8, SNOR_CMD_READ_8_8_8 },
  1918. { SNOR_HWCAPS_READ_1_8_8_DTR, SNOR_CMD_READ_1_8_8_DTR },
  1919. };
  1920. return spi_nor_hwcaps2cmd(hwcaps, hwcaps_read2cmd,
  1921. ARRAY_SIZE(hwcaps_read2cmd));
  1922. }
  1923. static int spi_nor_hwcaps_pp2cmd(u32 hwcaps)
  1924. {
  1925. static const int hwcaps_pp2cmd[][2] = {
  1926. { SNOR_HWCAPS_PP, SNOR_CMD_PP },
  1927. { SNOR_HWCAPS_PP_1_1_4, SNOR_CMD_PP_1_1_4 },
  1928. { SNOR_HWCAPS_PP_1_4_4, SNOR_CMD_PP_1_4_4 },
  1929. { SNOR_HWCAPS_PP_4_4_4, SNOR_CMD_PP_4_4_4 },
  1930. { SNOR_HWCAPS_PP_1_1_8, SNOR_CMD_PP_1_1_8 },
  1931. { SNOR_HWCAPS_PP_1_8_8, SNOR_CMD_PP_1_8_8 },
  1932. { SNOR_HWCAPS_PP_8_8_8, SNOR_CMD_PP_8_8_8 },
  1933. };
  1934. return spi_nor_hwcaps2cmd(hwcaps, hwcaps_pp2cmd,
  1935. ARRAY_SIZE(hwcaps_pp2cmd));
  1936. }
  1937. static int spi_nor_select_read(struct spi_nor *nor,
  1938. const struct spi_nor_flash_parameter *params,
  1939. u32 shared_hwcaps)
  1940. {
  1941. int cmd, best_match = fls(shared_hwcaps & SNOR_HWCAPS_READ_MASK) - 1;
  1942. const struct spi_nor_read_command *read;
  1943. if (best_match < 0)
  1944. return -EINVAL;
  1945. cmd = spi_nor_hwcaps_read2cmd(BIT(best_match));
  1946. if (cmd < 0)
  1947. return -EINVAL;
  1948. read = &params->reads[cmd];
  1949. nor->read_opcode = read->opcode;
  1950. nor->read_proto = read->proto;
  1951. /*
  1952. * In the spi-nor framework, we don't need to make the difference
  1953. * between mode clock cycles and wait state clock cycles.
  1954. * Indeed, the value of the mode clock cycles is used by a QSPI
  1955. * flash memory to know whether it should enter or leave its 0-4-4
  1956. * (Continuous Read / XIP) mode.
  1957. * eXecution In Place is out of the scope of the mtd sub-system.
  1958. * Hence we choose to merge both mode and wait state clock cycles
  1959. * into the so called dummy clock cycles.
  1960. */
  1961. nor->read_dummy = read->num_mode_clocks + read->num_wait_states;
  1962. return 0;
  1963. }
  1964. static int spi_nor_select_pp(struct spi_nor *nor,
  1965. const struct spi_nor_flash_parameter *params,
  1966. u32 shared_hwcaps)
  1967. {
  1968. int cmd, best_match = fls(shared_hwcaps & SNOR_HWCAPS_PP_MASK) - 1;
  1969. const struct spi_nor_pp_command *pp;
  1970. if (best_match < 0)
  1971. return -EINVAL;
  1972. cmd = spi_nor_hwcaps_pp2cmd(BIT(best_match));
  1973. if (cmd < 0)
  1974. return -EINVAL;
  1975. pp = &params->page_programs[cmd];
  1976. nor->program_opcode = pp->opcode;
  1977. nor->write_proto = pp->proto;
  1978. return 0;
  1979. }
  1980. static int spi_nor_select_erase(struct spi_nor *nor,
  1981. const struct flash_info *info)
  1982. {
  1983. struct mtd_info *mtd = &nor->mtd;
  1984. /* Do nothing if already configured from SFDP. */
  1985. if (mtd->erasesize)
  1986. return 0;
  1987. #ifdef CONFIG_SPI_FLASH_USE_4K_SECTORS
  1988. /* prefer "small sector" erase if possible */
  1989. if (info->flags & SECT_4K) {
  1990. nor->erase_opcode = SPINOR_OP_BE_4K;
  1991. mtd->erasesize = 4096;
  1992. } else if (info->flags & SECT_4K_PMC) {
  1993. nor->erase_opcode = SPINOR_OP_BE_4K_PMC;
  1994. mtd->erasesize = 4096;
  1995. } else
  1996. #endif
  1997. {
  1998. nor->erase_opcode = SPINOR_OP_SE;
  1999. mtd->erasesize = info->sector_size;
  2000. }
  2001. return 0;
  2002. }
  2003. static int spi_nor_setup(struct spi_nor *nor, const struct flash_info *info,
  2004. const struct spi_nor_flash_parameter *params,
  2005. const struct spi_nor_hwcaps *hwcaps)
  2006. {
  2007. u32 ignored_mask, shared_mask;
  2008. bool enable_quad_io;
  2009. int err;
  2010. /*
  2011. * Keep only the hardware capabilities supported by both the SPI
  2012. * controller and the SPI flash memory.
  2013. */
  2014. shared_mask = hwcaps->mask & params->hwcaps.mask;
  2015. /* SPI n-n-n protocols are not supported yet. */
  2016. ignored_mask = (SNOR_HWCAPS_READ_2_2_2 |
  2017. SNOR_HWCAPS_READ_4_4_4 |
  2018. SNOR_HWCAPS_READ_8_8_8 |
  2019. SNOR_HWCAPS_PP_4_4_4 |
  2020. SNOR_HWCAPS_PP_8_8_8);
  2021. if (shared_mask & ignored_mask) {
  2022. dev_dbg(nor->dev,
  2023. "SPI n-n-n protocols are not supported yet.\n");
  2024. shared_mask &= ~ignored_mask;
  2025. }
  2026. /* Select the (Fast) Read command. */
  2027. err = spi_nor_select_read(nor, params, shared_mask);
  2028. if (err) {
  2029. dev_dbg(nor->dev,
  2030. "can't select read settings supported by both the SPI controller and memory.\n");
  2031. return err;
  2032. }
  2033. /* Select the Page Program command. */
  2034. err = spi_nor_select_pp(nor, params, shared_mask);
  2035. if (err) {
  2036. dev_dbg(nor->dev,
  2037. "can't select write settings supported by both the SPI controller and memory.\n");
  2038. return err;
  2039. }
  2040. /* Select the Sector Erase command. */
  2041. err = spi_nor_select_erase(nor, info);
  2042. if (err) {
  2043. dev_dbg(nor->dev,
  2044. "can't select erase settings supported by both the SPI controller and memory.\n");
  2045. return err;
  2046. }
  2047. /* Enable Quad I/O if needed. */
  2048. enable_quad_io = (spi_nor_get_protocol_width(nor->read_proto) == 4 ||
  2049. spi_nor_get_protocol_width(nor->write_proto) == 4);
  2050. if (enable_quad_io && params->quad_enable)
  2051. nor->quad_enable = params->quad_enable;
  2052. else
  2053. nor->quad_enable = NULL;
  2054. return 0;
  2055. }
  2056. static int spi_nor_init(struct spi_nor *nor)
  2057. {
  2058. int err;
  2059. /*
  2060. * Atmel, SST, Intel/Numonyx, and others serial NOR tend to power up
  2061. * with the software protection bits set
  2062. */
  2063. if (JEDEC_MFR(nor->info) == SNOR_MFR_ATMEL ||
  2064. JEDEC_MFR(nor->info) == SNOR_MFR_INTEL ||
  2065. JEDEC_MFR(nor->info) == SNOR_MFR_SST ||
  2066. nor->info->flags & SPI_NOR_HAS_LOCK) {
  2067. write_enable(nor);
  2068. write_sr(nor, 0);
  2069. spi_nor_wait_till_ready(nor);
  2070. }
  2071. if (nor->quad_enable) {
  2072. err = nor->quad_enable(nor);
  2073. if (err) {
  2074. dev_dbg(nor->dev, "quad mode not supported\n");
  2075. return err;
  2076. }
  2077. }
  2078. if (nor->addr_width == 4 &&
  2079. (JEDEC_MFR(nor->info) != SNOR_MFR_SPANSION) &&
  2080. !(nor->info->flags & SPI_NOR_4B_OPCODES)) {
  2081. /*
  2082. * If the RESET# pin isn't hooked up properly, or the system
  2083. * otherwise doesn't perform a reset command in the boot
  2084. * sequence, it's impossible to 100% protect against unexpected
  2085. * reboots (e.g., crashes). Warn the user (or hopefully, system
  2086. * designer) that this is bad.
  2087. */
  2088. if (nor->flags & SNOR_F_BROKEN_RESET)
  2089. printf("enabling reset hack; may not recover from unexpected reboots\n");
  2090. set_4byte(nor, nor->info, 1);
  2091. }
  2092. return 0;
  2093. }
  2094. int spi_nor_scan(struct spi_nor *nor)
  2095. {
  2096. struct spi_nor_flash_parameter params;
  2097. const struct flash_info *info = NULL;
  2098. struct mtd_info *mtd = &nor->mtd;
  2099. struct spi_nor_hwcaps hwcaps = {
  2100. .mask = SNOR_HWCAPS_READ |
  2101. SNOR_HWCAPS_READ_FAST |
  2102. SNOR_HWCAPS_PP,
  2103. };
  2104. struct spi_slave *spi = nor->spi;
  2105. int ret;
  2106. /* Reset SPI protocol for all commands. */
  2107. nor->reg_proto = SNOR_PROTO_1_1_1;
  2108. nor->read_proto = SNOR_PROTO_1_1_1;
  2109. nor->write_proto = SNOR_PROTO_1_1_1;
  2110. nor->read = spi_nor_read_data;
  2111. nor->write = spi_nor_write_data;
  2112. nor->read_reg = spi_nor_read_reg;
  2113. nor->write_reg = spi_nor_write_reg;
  2114. if (spi->mode & SPI_RX_OCTAL) {
  2115. hwcaps.mask |= SNOR_HWCAPS_READ_1_1_8;
  2116. if (spi->mode & SPI_TX_OCTAL)
  2117. hwcaps.mask |= (SNOR_HWCAPS_READ_1_8_8 |
  2118. SNOR_HWCAPS_PP_1_1_8 |
  2119. SNOR_HWCAPS_PP_1_8_8);
  2120. } else if (spi->mode & SPI_RX_QUAD) {
  2121. hwcaps.mask |= SNOR_HWCAPS_READ_1_1_4;
  2122. if (spi->mode & SPI_TX_QUAD)
  2123. hwcaps.mask |= (SNOR_HWCAPS_READ_1_4_4 |
  2124. SNOR_HWCAPS_PP_1_1_4 |
  2125. SNOR_HWCAPS_PP_1_4_4);
  2126. } else if (spi->mode & SPI_RX_DUAL) {
  2127. hwcaps.mask |= SNOR_HWCAPS_READ_1_1_2;
  2128. if (spi->mode & SPI_TX_DUAL)
  2129. hwcaps.mask |= SNOR_HWCAPS_READ_1_2_2;
  2130. }
  2131. info = spi_nor_read_id(nor);
  2132. if (IS_ERR_OR_NULL(info))
  2133. return -ENOENT;
  2134. /* Parse the Serial Flash Discoverable Parameters table. */
  2135. ret = spi_nor_init_params(nor, info, &params);
  2136. if (ret)
  2137. return ret;
  2138. if (!mtd->name)
  2139. mtd->name = info->name;
  2140. mtd->priv = nor;
  2141. mtd->type = MTD_NORFLASH;
  2142. mtd->writesize = 1;
  2143. mtd->flags = MTD_CAP_NORFLASH;
  2144. mtd->size = params.size;
  2145. mtd->_erase = spi_nor_erase;
  2146. mtd->_read = spi_nor_read;
  2147. mtd->_write = spi_nor_write;
  2148. #if defined(CONFIG_SPI_FLASH_STMICRO) || defined(CONFIG_SPI_FLASH_SST)
  2149. /* NOR protection support for STmicro/Micron chips and similar */
  2150. if (JEDEC_MFR(info) == SNOR_MFR_ST ||
  2151. JEDEC_MFR(info) == SNOR_MFR_MICRON ||
  2152. JEDEC_MFR(info) == SNOR_MFR_SST ||
  2153. info->flags & SPI_NOR_HAS_LOCK) {
  2154. nor->flash_lock = stm_lock;
  2155. nor->flash_unlock = stm_unlock;
  2156. nor->flash_is_locked = stm_is_locked;
  2157. }
  2158. #endif
  2159. #ifdef CONFIG_SPI_FLASH_SST
  2160. /*
  2161. * sst26 series block protection implementation differs from other
  2162. * series.
  2163. */
  2164. if (info->flags & SPI_NOR_HAS_SST26LOCK) {
  2165. nor->flash_lock = sst26_lock;
  2166. nor->flash_unlock = sst26_unlock;
  2167. nor->flash_is_locked = sst26_is_locked;
  2168. }
  2169. #endif
  2170. if (info->flags & USE_FSR)
  2171. nor->flags |= SNOR_F_USE_FSR;
  2172. if (info->flags & SPI_NOR_HAS_TB)
  2173. nor->flags |= SNOR_F_HAS_SR_TB;
  2174. if (info->flags & NO_CHIP_ERASE)
  2175. nor->flags |= SNOR_F_NO_OP_CHIP_ERASE;
  2176. if (info->flags & USE_CLSR)
  2177. nor->flags |= SNOR_F_USE_CLSR;
  2178. if (info->flags & SPI_NOR_NO_ERASE)
  2179. mtd->flags |= MTD_NO_ERASE;
  2180. nor->page_size = params.page_size;
  2181. mtd->writebufsize = nor->page_size;
  2182. /* Some devices cannot do fast-read, no matter what DT tells us */
  2183. if ((info->flags & SPI_NOR_NO_FR) || (spi->mode & SPI_RX_SLOW))
  2184. params.hwcaps.mask &= ~SNOR_HWCAPS_READ_FAST;
  2185. /*
  2186. * Configure the SPI memory:
  2187. * - select op codes for (Fast) Read, Page Program and Sector Erase.
  2188. * - set the number of dummy cycles (mode cycles + wait states).
  2189. * - set the SPI protocols for register and memory accesses.
  2190. * - set the Quad Enable bit if needed (required by SPI x-y-4 protos).
  2191. */
  2192. ret = spi_nor_setup(nor, info, &params, &hwcaps);
  2193. if (ret)
  2194. return ret;
  2195. if (nor->addr_width) {
  2196. /* already configured from SFDP */
  2197. } else if (info->addr_width) {
  2198. nor->addr_width = info->addr_width;
  2199. } else if (mtd->size > SZ_16M) {
  2200. #ifndef CONFIG_SPI_FLASH_BAR
  2201. /* enable 4-byte addressing if the device exceeds 16MiB */
  2202. nor->addr_width = 4;
  2203. if (JEDEC_MFR(info) == SNOR_MFR_SPANSION ||
  2204. info->flags & SPI_NOR_4B_OPCODES)
  2205. spi_nor_set_4byte_opcodes(nor, info);
  2206. #else
  2207. /* Configure the BAR - discover bank cmds and read current bank */
  2208. nor->addr_width = 3;
  2209. ret = read_bar(nor, info);
  2210. if (ret < 0)
  2211. return ret;
  2212. #endif
  2213. } else {
  2214. nor->addr_width = 3;
  2215. }
  2216. if (nor->addr_width > SPI_NOR_MAX_ADDR_WIDTH) {
  2217. dev_dbg(nor->dev, "address width is too large: %u\n",
  2218. nor->addr_width);
  2219. return -EINVAL;
  2220. }
  2221. /* Send all the required SPI flash commands to initialize device */
  2222. nor->info = info;
  2223. ret = spi_nor_init(nor);
  2224. if (ret)
  2225. return ret;
  2226. nor->name = mtd->name;
  2227. nor->size = mtd->size;
  2228. nor->erase_size = mtd->erasesize;
  2229. nor->sector_size = mtd->erasesize;
  2230. #ifndef CONFIG_SPL_BUILD
  2231. printf("SF: Detected %s with page size ", nor->name);
  2232. print_size(nor->page_size, ", erase size ");
  2233. print_size(nor->erase_size, ", total ");
  2234. print_size(nor->size, "");
  2235. puts("\n");
  2236. #endif
  2237. return 0;
  2238. }