sf_internal.h 2.6 KB

1234567891011121314151617181920212223242526272829303132333435363738394041424344454647484950515253545556575859606162636465666768697071727374757677787980818283848586878889909192
  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * SPI flash internal definitions
  4. *
  5. * Copyright (C) 2008 Atmel Corporation
  6. * Copyright (C) 2013 Jagannadha Sutradharudu Teki, Xilinx Inc.
  7. */
  8. #ifndef _SF_INTERNAL_H_
  9. #define _SF_INTERNAL_H_
  10. #include <linux/bitops.h>
  11. #include <linux/types.h>
  12. #include <linux/compiler.h>
  13. #define SPI_NOR_MAX_ID_LEN 6
  14. #define SPI_NOR_MAX_ADDR_WIDTH 4
  15. struct flash_info {
  16. #if !CONFIG_IS_ENABLED(SPI_FLASH_TINY)
  17. char *name;
  18. #endif
  19. /*
  20. * This array stores the ID bytes.
  21. * The first three bytes are the JEDIC ID.
  22. * JEDEC ID zero means "no ID" (mostly older chips).
  23. */
  24. u8 id[SPI_NOR_MAX_ID_LEN];
  25. u8 id_len;
  26. /* The size listed here is what works with SPINOR_OP_SE, which isn't
  27. * necessarily called a "sector" by the vendor.
  28. */
  29. unsigned int sector_size;
  30. u16 n_sectors;
  31. u16 page_size;
  32. u16 addr_width;
  33. u32 flags;
  34. #define SECT_4K BIT(0) /* SPINOR_OP_BE_4K works uniformly */
  35. #define SPI_NOR_NO_ERASE BIT(1) /* No erase command needed */
  36. #define SST_WRITE BIT(2) /* use SST byte programming */
  37. #define SPI_NOR_NO_FR BIT(3) /* Can't do fastread */
  38. #define SECT_4K_PMC BIT(4) /* SPINOR_OP_BE_4K_PMC works uniformly */
  39. #define SPI_NOR_DUAL_READ BIT(5) /* Flash supports Dual Read */
  40. #define SPI_NOR_QUAD_READ BIT(6) /* Flash supports Quad Read */
  41. #define USE_FSR BIT(7) /* use flag status register */
  42. #define SPI_NOR_HAS_LOCK BIT(8) /* Flash supports lock/unlock via SR */
  43. #define SPI_NOR_HAS_TB BIT(9) /*
  44. * Flash SR has Top/Bottom (TB) protect
  45. * bit. Must be used with
  46. * SPI_NOR_HAS_LOCK.
  47. */
  48. #define SPI_S3AN BIT(10) /*
  49. * Xilinx Spartan 3AN In-System Flash
  50. * (MFR cannot be used for probing
  51. * because it has the same value as
  52. * ATMEL flashes)
  53. */
  54. #define SPI_NOR_4B_OPCODES BIT(11) /*
  55. * Use dedicated 4byte address op codes
  56. * to support memory size above 128Mib.
  57. */
  58. #define NO_CHIP_ERASE BIT(12) /* Chip does not support chip erase */
  59. #define SPI_NOR_SKIP_SFDP BIT(13) /* Skip parsing of SFDP tables */
  60. #define USE_CLSR BIT(14) /* use CLSR command */
  61. #define SPI_NOR_HAS_SST26LOCK BIT(15) /* Flash supports lock/unlock via BPR */
  62. #define SPI_NOR_OCTAL_READ BIT(16) /* Flash supports Octal Read */
  63. };
  64. extern const struct flash_info spi_nor_ids[];
  65. #define JEDEC_MFR(info) ((info)->id[0])
  66. #define JEDEC_ID(info) (((info)->id[1]) << 8 | ((info)->id[2]))
  67. #if CONFIG_IS_ENABLED(SPI_FLASH_MTD)
  68. int spi_flash_mtd_register(struct spi_flash *flash);
  69. void spi_flash_mtd_unregister(void);
  70. #else
  71. static inline int spi_flash_mtd_register(struct spi_flash *flash)
  72. {
  73. return 0;
  74. }
  75. static inline void spi_flash_mtd_unregister(void)
  76. {
  77. }
  78. #endif
  79. #endif /* _SF_INTERNAL_H_ */