board_f.c 25 KB

12345678910111213141516171819202122232425262728293031323334353637383940414243444546474849505152535455565758596061626364656667686970717273747576777879808182838485868788899091929394959697989910010110210310410510610710810911011111211311411511611711811912012112212312412512612712812913013113213313413513613713813914014114214314414514614714814915015115215315415515615715815916016116216316416516616716816917017117217317417517617717817918018118218318418518618718818919019119219319419519619719819920020120220320420520620720820921021121221321421521621721821922022122222322422522622722822923023123223323423523623723823924024124224324424524624724824925025125225325425525625725825926026126226326426526626726826927027127227327427527627727827928028128228328428528628728828929029129229329429529629729829930030130230330430530630730830931031131231331431531631731831932032132232332432532632732832933033133233333433533633733833934034134234334434534634734834935035135235335435535635735835936036136236336436536636736836937037137237337437537637737837938038138238338438538638738838939039139239339439539639739839940040140240340440540640740840941041141241341441541641741841942042142242342442542642742842943043143243343443543643743843944044144244344444544644744844945045145245345445545645745845946046146246346446546646746846947047147247347447547647747847948048148248348448548648748848949049149249349449549649749849950050150250350450550650750850951051151251351451551651751851952052152252352452552652752852953053153253353453553653753853954054154254354454554654754854955055155255355455555655755855956056156256356456556656756856957057157257357457557657757857958058158258358458558658758858959059159259359459559659759859960060160260360460560660760860961061161261361461561661761861962062162262362462562662762862963063163263363463563663763863964064164264364464564664764864965065165265365465565665765865966066166266366466566666766866967067167267367467567667767867968068168268368468568668768868969069169269369469569669769869970070170270370470570670770870971071171271371471571671771871972072172272372472572672772872973073173273373473573673773873974074174274374474574674774874975075175275375475575675775875976076176276376476576676776876977077177277377477577677777877978078178278378478578678778878979079179279379479579679779879980080180280380480580680780880981081181281381481581681781881982082182282382482582682782882983083183283383483583683783883984084184284384484584684784884985085185285385485585685785885986086186286386486586686786886987087187287387487587687787887988088188288388488588688788888989089189289389489589689789889990090190290390490590690790890991091191291391491591691791891992092192292392492592692792892993093193293393493593693793893994094194294394494594694794894995095195295395495595695795895996096196296396496596696796896997097197297397497597697797897998098198298398498598698798898999099199299399499599699799899910001001100210031004100510061007100810091010101110121013101410151016101710181019102010211022102310241025102610271028102910301031103210331034103510361037103810391040104110421043104410451046104710481049105010511052105310541055105610571058105910601061106210631064106510661067106810691070107110721073107410751076
  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (c) 2011 The Chromium OS Authors.
  4. * (C) Copyright 2002-2006
  5. * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  6. *
  7. * (C) Copyright 2002
  8. * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
  9. * Marius Groeger <mgroeger@sysgo.de>
  10. */
  11. #include <common.h>
  12. #include <bloblist.h>
  13. #include <bootstage.h>
  14. #include <clock_legacy.h>
  15. #include <console.h>
  16. #include <cpu.h>
  17. #include <cpu_func.h>
  18. #include <dm.h>
  19. #include <env.h>
  20. #include <env_internal.h>
  21. #include <fdtdec.h>
  22. #include <fs.h>
  23. #include <hang.h>
  24. #include <i2c.h>
  25. #include <init.h>
  26. #include <initcall.h>
  27. #include <lcd.h>
  28. #include <log.h>
  29. #include <malloc.h>
  30. #include <mapmem.h>
  31. #include <os.h>
  32. #include <post.h>
  33. #include <relocate.h>
  34. #include <serial.h>
  35. #ifdef CONFIG_SPL
  36. #include <spl.h>
  37. #endif
  38. #include <status_led.h>
  39. #include <sysreset.h>
  40. #include <timer.h>
  41. #include <trace.h>
  42. #include <video.h>
  43. #include <watchdog.h>
  44. #include <asm/cache.h>
  45. #ifdef CONFIG_MACH_TYPE
  46. #include <asm/mach-types.h>
  47. #endif
  48. #if defined(CONFIG_MP) && defined(CONFIG_PPC)
  49. #include <asm/mp.h>
  50. #endif
  51. #include <asm/io.h>
  52. #include <asm/sections.h>
  53. #include <dm/root.h>
  54. #include <linux/errno.h>
  55. /*
  56. * Pointer to initial global data area
  57. *
  58. * Here we initialize it if needed.
  59. */
  60. #ifdef XTRN_DECLARE_GLOBAL_DATA_PTR
  61. #undef XTRN_DECLARE_GLOBAL_DATA_PTR
  62. #define XTRN_DECLARE_GLOBAL_DATA_PTR /* empty = allocate here */
  63. DECLARE_GLOBAL_DATA_PTR = (gd_t *)(CONFIG_SYS_INIT_GD_ADDR);
  64. #else
  65. DECLARE_GLOBAL_DATA_PTR;
  66. #endif
  67. /*
  68. * TODO(sjg@chromium.org): IMO this code should be
  69. * refactored to a single function, something like:
  70. *
  71. * void led_set_state(enum led_colour_t colour, int on);
  72. */
  73. /************************************************************************
  74. * Coloured LED functionality
  75. ************************************************************************
  76. * May be supplied by boards if desired
  77. */
  78. __weak void coloured_LED_init(void) {}
  79. __weak void red_led_on(void) {}
  80. __weak void red_led_off(void) {}
  81. __weak void green_led_on(void) {}
  82. __weak void green_led_off(void) {}
  83. __weak void yellow_led_on(void) {}
  84. __weak void yellow_led_off(void) {}
  85. __weak void blue_led_on(void) {}
  86. __weak void blue_led_off(void) {}
  87. /*
  88. * Why is gd allocated a register? Prior to reloc it might be better to
  89. * just pass it around to each function in this file?
  90. *
  91. * After reloc one could argue that it is hardly used and doesn't need
  92. * to be in a register. Or if it is it should perhaps hold pointers to all
  93. * global data for all modules, so that post-reloc we can avoid the massive
  94. * literal pool we get on ARM. Or perhaps just encourage each module to use
  95. * a structure...
  96. */
  97. #if defined(CONFIG_WATCHDOG) || defined(CONFIG_HW_WATCHDOG)
  98. static int init_func_watchdog_init(void)
  99. {
  100. # if defined(CONFIG_HW_WATCHDOG) && \
  101. (defined(CONFIG_M68K) || defined(CONFIG_MICROBLAZE) || \
  102. defined(CONFIG_SH) || \
  103. defined(CONFIG_DESIGNWARE_WATCHDOG) || \
  104. defined(CONFIG_IMX_WATCHDOG))
  105. hw_watchdog_init();
  106. puts(" Watchdog enabled\n");
  107. # endif
  108. WATCHDOG_RESET();
  109. return 0;
  110. }
  111. int init_func_watchdog_reset(void)
  112. {
  113. WATCHDOG_RESET();
  114. return 0;
  115. }
  116. #endif /* CONFIG_WATCHDOG */
  117. __weak void board_add_ram_info(int use_default)
  118. {
  119. /* please define platform specific board_add_ram_info() */
  120. }
  121. static int init_baud_rate(void)
  122. {
  123. gd->baudrate = env_get_ulong("baudrate", 10, CONFIG_BAUDRATE);
  124. return 0;
  125. }
  126. static int display_text_info(void)
  127. {
  128. #if !defined(CONFIG_SANDBOX) && !defined(CONFIG_EFI_APP)
  129. ulong bss_start, bss_end, text_base;
  130. bss_start = (ulong)&__bss_start;
  131. bss_end = (ulong)&__bss_end;
  132. #ifdef CONFIG_SYS_TEXT_BASE
  133. text_base = CONFIG_SYS_TEXT_BASE;
  134. #else
  135. text_base = CONFIG_SYS_MONITOR_BASE;
  136. #endif
  137. debug("U-Boot code: %08lX -> %08lX BSS: -> %08lX\n",
  138. text_base, bss_start, bss_end);
  139. #endif
  140. return 0;
  141. }
  142. #ifdef CONFIG_SYSRESET
  143. static int print_resetinfo(void)
  144. {
  145. struct udevice *dev;
  146. char status[256];
  147. int ret;
  148. ret = uclass_first_device_err(UCLASS_SYSRESET, &dev);
  149. if (ret) {
  150. debug("%s: No sysreset device found (error: %d)\n",
  151. __func__, ret);
  152. /* Not all boards have sysreset drivers available during early
  153. * boot, so don't fail if one can't be found.
  154. */
  155. return 0;
  156. }
  157. if (!sysreset_get_status(dev, status, sizeof(status)))
  158. printf("%s", status);
  159. return 0;
  160. }
  161. #endif
  162. #if defined(CONFIG_DISPLAY_CPUINFO) && CONFIG_IS_ENABLED(CPU)
  163. static int print_cpuinfo(void)
  164. {
  165. struct udevice *dev;
  166. char desc[512];
  167. int ret;
  168. dev = cpu_get_current_dev();
  169. if (!dev) {
  170. debug("%s: Could not get CPU device\n",
  171. __func__);
  172. return -ENODEV;
  173. }
  174. ret = cpu_get_desc(dev, desc, sizeof(desc));
  175. if (ret) {
  176. debug("%s: Could not get CPU description (err = %d)\n",
  177. dev->name, ret);
  178. return ret;
  179. }
  180. printf("CPU: %s\n", desc);
  181. return 0;
  182. }
  183. #endif
  184. static int announce_dram_init(void)
  185. {
  186. puts("DRAM: ");
  187. return 0;
  188. }
  189. static int show_dram_config(void)
  190. {
  191. unsigned long long size;
  192. #ifdef CONFIG_NR_DRAM_BANKS
  193. int i;
  194. debug("\nRAM Configuration:\n");
  195. for (i = size = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
  196. size += gd->bd->bi_dram[i].size;
  197. debug("Bank #%d: %llx ", i,
  198. (unsigned long long)(gd->bd->bi_dram[i].start));
  199. #ifdef DEBUG
  200. print_size(gd->bd->bi_dram[i].size, "\n");
  201. #endif
  202. }
  203. debug("\nDRAM: ");
  204. #else
  205. size = gd->ram_size;
  206. #endif
  207. print_size(size, "");
  208. board_add_ram_info(0);
  209. putc('\n');
  210. return 0;
  211. }
  212. __weak int dram_init_banksize(void)
  213. {
  214. #if defined(CONFIG_NR_DRAM_BANKS) && defined(CONFIG_SYS_SDRAM_BASE)
  215. gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
  216. gd->bd->bi_dram[0].size = get_effective_memsize();
  217. #endif
  218. return 0;
  219. }
  220. #if defined(CONFIG_SYS_I2C)
  221. static int init_func_i2c(void)
  222. {
  223. puts("I2C: ");
  224. #ifdef CONFIG_SYS_I2C
  225. i2c_init_all();
  226. #else
  227. i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
  228. #endif
  229. puts("ready\n");
  230. return 0;
  231. }
  232. #endif
  233. #if defined(CONFIG_VID)
  234. __weak int init_func_vid(void)
  235. {
  236. return 0;
  237. }
  238. #endif
  239. static int setup_mon_len(void)
  240. {
  241. #if defined(__ARM__) || defined(__MICROBLAZE__)
  242. gd->mon_len = (ulong)&__bss_end - (ulong)_start;
  243. #elif defined(CONFIG_SANDBOX) || defined(CONFIG_EFI_APP)
  244. gd->mon_len = (ulong)&_end - (ulong)_init;
  245. #elif defined(CONFIG_NIOS2) || defined(CONFIG_XTENSA)
  246. gd->mon_len = CONFIG_SYS_MONITOR_LEN;
  247. #elif defined(CONFIG_NDS32) || defined(CONFIG_SH) || defined(CONFIG_RISCV)
  248. gd->mon_len = (ulong)(&__bss_end) - (ulong)(&_start);
  249. #elif defined(CONFIG_SYS_MONITOR_BASE)
  250. /* TODO: use (ulong)&__bss_end - (ulong)&__text_start; ? */
  251. gd->mon_len = (ulong)&__bss_end - CONFIG_SYS_MONITOR_BASE;
  252. #endif
  253. return 0;
  254. }
  255. static int setup_spl_handoff(void)
  256. {
  257. #if CONFIG_IS_ENABLED(HANDOFF)
  258. gd->spl_handoff = bloblist_find(BLOBLISTT_SPL_HANDOFF,
  259. sizeof(struct spl_handoff));
  260. debug("Found SPL hand-off info %p\n", gd->spl_handoff);
  261. #endif
  262. return 0;
  263. }
  264. __weak int arch_cpu_init(void)
  265. {
  266. return 0;
  267. }
  268. __weak int mach_cpu_init(void)
  269. {
  270. return 0;
  271. }
  272. /* Get the top of usable RAM */
  273. __weak ulong board_get_usable_ram_top(ulong total_size)
  274. {
  275. #if defined(CONFIG_SYS_SDRAM_BASE) && CONFIG_SYS_SDRAM_BASE > 0
  276. /*
  277. * Detect whether we have so much RAM that it goes past the end of our
  278. * 32-bit address space. If so, clip the usable RAM so it doesn't.
  279. */
  280. if (gd->ram_top < CONFIG_SYS_SDRAM_BASE)
  281. /*
  282. * Will wrap back to top of 32-bit space when reservations
  283. * are made.
  284. */
  285. return 0;
  286. #endif
  287. return gd->ram_top;
  288. }
  289. static int setup_dest_addr(void)
  290. {
  291. debug("Monitor len: %08lX\n", gd->mon_len);
  292. /*
  293. * Ram is setup, size stored in gd !!
  294. */
  295. debug("Ram size: %08lX\n", (ulong)gd->ram_size);
  296. #if defined(CONFIG_SYS_MEM_TOP_HIDE)
  297. /*
  298. * Subtract specified amount of memory to hide so that it won't
  299. * get "touched" at all by U-Boot. By fixing up gd->ram_size
  300. * the Linux kernel should now get passed the now "corrected"
  301. * memory size and won't touch it either. This should work
  302. * for arch/ppc and arch/powerpc. Only Linux board ports in
  303. * arch/powerpc with bootwrapper support, that recalculate the
  304. * memory size from the SDRAM controller setup will have to
  305. * get fixed.
  306. */
  307. gd->ram_size -= CONFIG_SYS_MEM_TOP_HIDE;
  308. #endif
  309. #ifdef CONFIG_SYS_SDRAM_BASE
  310. gd->ram_base = CONFIG_SYS_SDRAM_BASE;
  311. #endif
  312. gd->ram_top = gd->ram_base + get_effective_memsize();
  313. gd->ram_top = board_get_usable_ram_top(gd->mon_len);
  314. gd->relocaddr = gd->ram_top;
  315. debug("Ram top: %08lX\n", (ulong)gd->ram_top);
  316. #if defined(CONFIG_MP) && (defined(CONFIG_MPC86xx) || defined(CONFIG_E500))
  317. /*
  318. * We need to make sure the location we intend to put secondary core
  319. * boot code is reserved and not used by any part of u-boot
  320. */
  321. if (gd->relocaddr > determine_mp_bootpg(NULL)) {
  322. gd->relocaddr = determine_mp_bootpg(NULL);
  323. debug("Reserving MP boot page to %08lx\n", gd->relocaddr);
  324. }
  325. #endif
  326. return 0;
  327. }
  328. #ifdef CONFIG_PRAM
  329. /* reserve protected RAM */
  330. static int reserve_pram(void)
  331. {
  332. ulong reg;
  333. reg = env_get_ulong("pram", 10, CONFIG_PRAM);
  334. gd->relocaddr -= (reg << 10); /* size is in kB */
  335. debug("Reserving %ldk for protected RAM at %08lx\n", reg,
  336. gd->relocaddr);
  337. return 0;
  338. }
  339. #endif /* CONFIG_PRAM */
  340. /* Round memory pointer down to next 4 kB limit */
  341. static int reserve_round_4k(void)
  342. {
  343. gd->relocaddr &= ~(4096 - 1);
  344. return 0;
  345. }
  346. __weak int arch_reserve_mmu(void)
  347. {
  348. return 0;
  349. }
  350. static int reserve_video(void)
  351. {
  352. #ifdef CONFIG_DM_VIDEO
  353. ulong addr;
  354. int ret;
  355. addr = gd->relocaddr;
  356. ret = video_reserve(&addr);
  357. if (ret)
  358. return ret;
  359. gd->relocaddr = addr;
  360. #elif defined(CONFIG_LCD)
  361. # ifdef CONFIG_FB_ADDR
  362. gd->fb_base = CONFIG_FB_ADDR;
  363. # else
  364. /* reserve memory for LCD display (always full pages) */
  365. gd->relocaddr = lcd_setmem(gd->relocaddr);
  366. gd->fb_base = gd->relocaddr;
  367. # endif /* CONFIG_FB_ADDR */
  368. #endif
  369. return 0;
  370. }
  371. static int reserve_trace(void)
  372. {
  373. #ifdef CONFIG_TRACE
  374. gd->relocaddr -= CONFIG_TRACE_BUFFER_SIZE;
  375. gd->trace_buff = map_sysmem(gd->relocaddr, CONFIG_TRACE_BUFFER_SIZE);
  376. debug("Reserving %luk for trace data at: %08lx\n",
  377. (unsigned long)CONFIG_TRACE_BUFFER_SIZE >> 10, gd->relocaddr);
  378. #endif
  379. return 0;
  380. }
  381. static int reserve_uboot(void)
  382. {
  383. if (!(gd->flags & GD_FLG_SKIP_RELOC)) {
  384. /*
  385. * reserve memory for U-Boot code, data & bss
  386. * round down to next 4 kB limit
  387. */
  388. gd->relocaddr -= gd->mon_len;
  389. gd->relocaddr &= ~(4096 - 1);
  390. #if defined(CONFIG_E500) || defined(CONFIG_MIPS)
  391. /* round down to next 64 kB limit so that IVPR stays aligned */
  392. gd->relocaddr &= ~(65536 - 1);
  393. #endif
  394. debug("Reserving %ldk for U-Boot at: %08lx\n",
  395. gd->mon_len >> 10, gd->relocaddr);
  396. }
  397. gd->start_addr_sp = gd->relocaddr;
  398. return 0;
  399. }
  400. /*
  401. * reserve after start_addr_sp the requested size and make the stack pointer
  402. * 16-byte aligned, this alignment is needed for cast on the reserved memory
  403. * ref = x86_64 ABI: https://reviews.llvm.org/D30049: 16 bytes
  404. * = ARMv8 Instruction Set Overview: quad word, 16 bytes
  405. */
  406. static unsigned long reserve_stack_aligned(size_t size)
  407. {
  408. return ALIGN_DOWN(gd->start_addr_sp - size, 16);
  409. }
  410. #ifdef CONFIG_SYS_NONCACHED_MEMORY
  411. static int reserve_noncached(void)
  412. {
  413. /*
  414. * The value of gd->start_addr_sp must match the value of malloc_start
  415. * calculated in boatrd_f.c:initr_malloc(), which is passed to
  416. * board_r.c:mem_malloc_init() and then used by
  417. * cache.c:noncached_init()
  418. *
  419. * These calculations must match the code in cache.c:noncached_init()
  420. */
  421. gd->start_addr_sp = ALIGN(gd->start_addr_sp, MMU_SECTION_SIZE) -
  422. MMU_SECTION_SIZE;
  423. gd->start_addr_sp -= ALIGN(CONFIG_SYS_NONCACHED_MEMORY,
  424. MMU_SECTION_SIZE);
  425. debug("Reserving %dM for noncached_alloc() at: %08lx\n",
  426. CONFIG_SYS_NONCACHED_MEMORY >> 20, gd->start_addr_sp);
  427. return 0;
  428. }
  429. #endif
  430. /* reserve memory for malloc() area */
  431. static int reserve_malloc(void)
  432. {
  433. gd->start_addr_sp = reserve_stack_aligned(TOTAL_MALLOC_LEN);
  434. debug("Reserving %dk for malloc() at: %08lx\n",
  435. TOTAL_MALLOC_LEN >> 10, gd->start_addr_sp);
  436. #ifdef CONFIG_SYS_NONCACHED_MEMORY
  437. reserve_noncached();
  438. #endif
  439. return 0;
  440. }
  441. /* (permanently) allocate a Board Info struct */
  442. static int reserve_board(void)
  443. {
  444. if (!gd->bd) {
  445. gd->start_addr_sp = reserve_stack_aligned(sizeof(struct bd_info));
  446. gd->bd = (struct bd_info *)map_sysmem(gd->start_addr_sp,
  447. sizeof(struct bd_info));
  448. memset(gd->bd, '\0', sizeof(struct bd_info));
  449. debug("Reserving %zu Bytes for Board Info at: %08lx\n",
  450. sizeof(struct bd_info), gd->start_addr_sp);
  451. }
  452. return 0;
  453. }
  454. static int setup_machine(void)
  455. {
  456. #ifdef CONFIG_MACH_TYPE
  457. gd->bd->bi_arch_number = CONFIG_MACH_TYPE; /* board id for Linux */
  458. #endif
  459. return 0;
  460. }
  461. static int reserve_global_data(void)
  462. {
  463. gd->start_addr_sp = reserve_stack_aligned(sizeof(gd_t));
  464. gd->new_gd = (gd_t *)map_sysmem(gd->start_addr_sp, sizeof(gd_t));
  465. debug("Reserving %zu Bytes for Global Data at: %08lx\n",
  466. sizeof(gd_t), gd->start_addr_sp);
  467. return 0;
  468. }
  469. static int reserve_fdt(void)
  470. {
  471. #ifndef CONFIG_OF_EMBED
  472. /*
  473. * If the device tree is sitting immediately above our image then we
  474. * must relocate it. If it is embedded in the data section, then it
  475. * will be relocated with other data.
  476. */
  477. if (gd->fdt_blob) {
  478. gd->fdt_size = ALIGN(fdt_totalsize(gd->fdt_blob), 32);
  479. gd->start_addr_sp = reserve_stack_aligned(gd->fdt_size);
  480. gd->new_fdt = map_sysmem(gd->start_addr_sp, gd->fdt_size);
  481. debug("Reserving %lu Bytes for FDT at: %08lx\n",
  482. gd->fdt_size, gd->start_addr_sp);
  483. }
  484. #endif
  485. return 0;
  486. }
  487. static int reserve_bootstage(void)
  488. {
  489. #ifdef CONFIG_BOOTSTAGE
  490. int size = bootstage_get_size();
  491. gd->start_addr_sp = reserve_stack_aligned(size);
  492. gd->new_bootstage = map_sysmem(gd->start_addr_sp, size);
  493. debug("Reserving %#x Bytes for bootstage at: %08lx\n", size,
  494. gd->start_addr_sp);
  495. #endif
  496. return 0;
  497. }
  498. __weak int arch_reserve_stacks(void)
  499. {
  500. return 0;
  501. }
  502. static int reserve_stacks(void)
  503. {
  504. /* make stack pointer 16-byte aligned */
  505. gd->start_addr_sp = reserve_stack_aligned(16);
  506. /*
  507. * let the architecture-specific code tailor gd->start_addr_sp and
  508. * gd->irq_sp
  509. */
  510. return arch_reserve_stacks();
  511. }
  512. static int reserve_bloblist(void)
  513. {
  514. #ifdef CONFIG_BLOBLIST
  515. gd->start_addr_sp = reserve_stack_aligned(CONFIG_BLOBLIST_SIZE);
  516. gd->new_bloblist = map_sysmem(gd->start_addr_sp, CONFIG_BLOBLIST_SIZE);
  517. #endif
  518. return 0;
  519. }
  520. static int display_new_sp(void)
  521. {
  522. debug("New Stack Pointer is: %08lx\n", gd->start_addr_sp);
  523. return 0;
  524. }
  525. #if defined(CONFIG_M68K) || defined(CONFIG_MIPS) || defined(CONFIG_PPC) || \
  526. defined(CONFIG_SH)
  527. static int setup_board_part1(void)
  528. {
  529. struct bd_info *bd = gd->bd;
  530. /*
  531. * Save local variables to board info struct
  532. */
  533. bd->bi_memstart = CONFIG_SYS_SDRAM_BASE; /* start of memory */
  534. bd->bi_memsize = gd->ram_size; /* size in bytes */
  535. #ifdef CONFIG_SYS_SRAM_BASE
  536. bd->bi_sramstart = CONFIG_SYS_SRAM_BASE; /* start of SRAM */
  537. bd->bi_sramsize = CONFIG_SYS_SRAM_SIZE; /* size of SRAM */
  538. #endif
  539. #if defined(CONFIG_E500) || defined(CONFIG_MPC86xx)
  540. bd->bi_immr_base = CONFIG_SYS_IMMR; /* base of IMMR register */
  541. #endif
  542. #if defined(CONFIG_M68K)
  543. bd->bi_mbar_base = CONFIG_SYS_MBAR; /* base of internal registers */
  544. #endif
  545. #if defined(CONFIG_MPC83xx)
  546. bd->bi_immrbar = CONFIG_SYS_IMMR;
  547. #endif
  548. return 0;
  549. }
  550. #endif
  551. #if defined(CONFIG_PPC) || defined(CONFIG_M68K)
  552. static int setup_board_part2(void)
  553. {
  554. struct bd_info *bd = gd->bd;
  555. bd->bi_intfreq = gd->cpu_clk; /* Internal Freq, in Hz */
  556. bd->bi_busfreq = gd->bus_clk; /* Bus Freq, in Hz */
  557. #if defined(CONFIG_CPM2)
  558. bd->bi_cpmfreq = gd->arch.cpm_clk;
  559. bd->bi_brgfreq = gd->arch.brg_clk;
  560. bd->bi_sccfreq = gd->arch.scc_clk;
  561. bd->bi_vco = gd->arch.vco_out;
  562. #endif /* CONFIG_CPM2 */
  563. #if defined(CONFIG_M68K) && defined(CONFIG_PCI)
  564. bd->bi_pcifreq = gd->pci_clk;
  565. #endif
  566. #if defined(CONFIG_EXTRA_CLOCK)
  567. bd->bi_inpfreq = gd->arch.inp_clk; /* input Freq in Hz */
  568. bd->bi_vcofreq = gd->arch.vco_clk; /* vco Freq in Hz */
  569. bd->bi_flbfreq = gd->arch.flb_clk; /* flexbus Freq in Hz */
  570. #endif
  571. return 0;
  572. }
  573. #endif
  574. #ifdef CONFIG_POST
  575. static int init_post(void)
  576. {
  577. post_bootmode_init();
  578. post_run(NULL, POST_ROM | post_bootmode_get(0));
  579. return 0;
  580. }
  581. #endif
  582. static int reloc_fdt(void)
  583. {
  584. #ifndef CONFIG_OF_EMBED
  585. if (gd->flags & GD_FLG_SKIP_RELOC)
  586. return 0;
  587. if (gd->new_fdt) {
  588. memcpy(gd->new_fdt, gd->fdt_blob, fdt_totalsize(gd->fdt_blob));
  589. gd->fdt_blob = gd->new_fdt;
  590. }
  591. #endif
  592. return 0;
  593. }
  594. static int reloc_bootstage(void)
  595. {
  596. #ifdef CONFIG_BOOTSTAGE
  597. if (gd->flags & GD_FLG_SKIP_RELOC)
  598. return 0;
  599. if (gd->new_bootstage) {
  600. int size = bootstage_get_size();
  601. debug("Copying bootstage from %p to %p, size %x\n",
  602. gd->bootstage, gd->new_bootstage, size);
  603. memcpy(gd->new_bootstage, gd->bootstage, size);
  604. gd->bootstage = gd->new_bootstage;
  605. bootstage_relocate();
  606. }
  607. #endif
  608. return 0;
  609. }
  610. static int reloc_bloblist(void)
  611. {
  612. #ifdef CONFIG_BLOBLIST
  613. if (gd->flags & GD_FLG_SKIP_RELOC)
  614. return 0;
  615. if (gd->new_bloblist) {
  616. int size = CONFIG_BLOBLIST_SIZE;
  617. debug("Copying bloblist from %p to %p, size %x\n",
  618. gd->bloblist, gd->new_bloblist, size);
  619. memcpy(gd->new_bloblist, gd->bloblist, size);
  620. gd->bloblist = gd->new_bloblist;
  621. }
  622. #endif
  623. return 0;
  624. }
  625. static int setup_reloc(void)
  626. {
  627. if (gd->flags & GD_FLG_SKIP_RELOC) {
  628. debug("Skipping relocation due to flag\n");
  629. return 0;
  630. }
  631. #ifdef CONFIG_SYS_TEXT_BASE
  632. #ifdef ARM
  633. gd->reloc_off = gd->relocaddr - (unsigned long)__image_copy_start;
  634. #elif defined(CONFIG_M68K)
  635. /*
  636. * On all ColdFire arch cpu, monitor code starts always
  637. * just after the default vector table location, so at 0x400
  638. */
  639. gd->reloc_off = gd->relocaddr - (CONFIG_SYS_TEXT_BASE + 0x400);
  640. #elif !defined(CONFIG_SANDBOX)
  641. gd->reloc_off = gd->relocaddr - CONFIG_SYS_TEXT_BASE;
  642. #endif
  643. #endif
  644. memcpy(gd->new_gd, (char *)gd, sizeof(gd_t));
  645. debug("Relocation Offset is: %08lx\n", gd->reloc_off);
  646. debug("Relocating to %08lx, new gd at %08lx, sp at %08lx\n",
  647. gd->relocaddr, (ulong)map_to_sysmem(gd->new_gd),
  648. gd->start_addr_sp);
  649. return 0;
  650. }
  651. #ifdef CONFIG_OF_BOARD_FIXUP
  652. static int fix_fdt(void)
  653. {
  654. return board_fix_fdt((void *)gd->fdt_blob);
  655. }
  656. #endif
  657. /* ARM calls relocate_code from its crt0.S */
  658. #if !defined(CONFIG_ARM) && !defined(CONFIG_SANDBOX) && \
  659. !CONFIG_IS_ENABLED(X86_64)
  660. static int jump_to_copy(void)
  661. {
  662. if (gd->flags & GD_FLG_SKIP_RELOC)
  663. return 0;
  664. /*
  665. * x86 is special, but in a nice way. It uses a trampoline which
  666. * enables the dcache if possible.
  667. *
  668. * For now, other archs use relocate_code(), which is implemented
  669. * similarly for all archs. When we do generic relocation, hopefully
  670. * we can make all archs enable the dcache prior to relocation.
  671. */
  672. #if defined(CONFIG_X86) || defined(CONFIG_ARC)
  673. /*
  674. * SDRAM and console are now initialised. The final stack can now
  675. * be setup in SDRAM. Code execution will continue in Flash, but
  676. * with the stack in SDRAM and Global Data in temporary memory
  677. * (CPU cache)
  678. */
  679. arch_setup_gd(gd->new_gd);
  680. board_init_f_r_trampoline(gd->start_addr_sp);
  681. #else
  682. relocate_code(gd->start_addr_sp, gd->new_gd, gd->relocaddr);
  683. #endif
  684. return 0;
  685. }
  686. #endif
  687. /* Record the board_init_f() bootstage (after arch_cpu_init()) */
  688. static int initf_bootstage(void)
  689. {
  690. bool from_spl = IS_ENABLED(CONFIG_SPL_BOOTSTAGE) &&
  691. IS_ENABLED(CONFIG_BOOTSTAGE_STASH);
  692. int ret;
  693. ret = bootstage_init(!from_spl);
  694. if (ret)
  695. return ret;
  696. if (from_spl) {
  697. const void *stash = map_sysmem(CONFIG_BOOTSTAGE_STASH_ADDR,
  698. CONFIG_BOOTSTAGE_STASH_SIZE);
  699. ret = bootstage_unstash(stash, CONFIG_BOOTSTAGE_STASH_SIZE);
  700. if (ret && ret != -ENOENT) {
  701. debug("Failed to unstash bootstage: err=%d\n", ret);
  702. return ret;
  703. }
  704. }
  705. bootstage_mark_name(BOOTSTAGE_ID_START_UBOOT_F, "board_init_f");
  706. return 0;
  707. }
  708. static int initf_console_record(void)
  709. {
  710. #if defined(CONFIG_CONSOLE_RECORD) && CONFIG_VAL(SYS_MALLOC_F_LEN)
  711. return console_record_init();
  712. #else
  713. return 0;
  714. #endif
  715. }
  716. static int initf_dm(void)
  717. {
  718. #if defined(CONFIG_DM) && CONFIG_VAL(SYS_MALLOC_F_LEN)
  719. int ret;
  720. bootstage_start(BOOTSTAGE_ID_ACCUM_DM_F, "dm_f");
  721. ret = dm_init_and_scan(true);
  722. bootstage_accum(BOOTSTAGE_ID_ACCUM_DM_F);
  723. if (ret)
  724. return ret;
  725. #endif
  726. #ifdef CONFIG_TIMER_EARLY
  727. ret = dm_timer_init();
  728. if (ret)
  729. return ret;
  730. #endif
  731. return 0;
  732. }
  733. /* Architecture-specific memory reservation */
  734. __weak int reserve_arch(void)
  735. {
  736. return 0;
  737. }
  738. __weak int arch_cpu_init_dm(void)
  739. {
  740. return 0;
  741. }
  742. __weak int checkcpu(void)
  743. {
  744. return 0;
  745. }
  746. __weak int clear_bss(void)
  747. {
  748. return 0;
  749. }
  750. static const init_fnc_t init_sequence_f[] = {
  751. setup_mon_len,
  752. #ifdef CONFIG_OF_CONTROL
  753. fdtdec_setup,
  754. #endif
  755. #ifdef CONFIG_TRACE_EARLY
  756. trace_early_init,
  757. #endif
  758. initf_malloc,
  759. log_init,
  760. initf_bootstage, /* uses its own timer, so does not need DM */
  761. #ifdef CONFIG_BLOBLIST
  762. bloblist_init,
  763. #endif
  764. setup_spl_handoff,
  765. initf_console_record,
  766. #if defined(CONFIG_HAVE_FSP)
  767. arch_fsp_init,
  768. #endif
  769. arch_cpu_init, /* basic arch cpu dependent setup */
  770. mach_cpu_init, /* SoC/machine dependent CPU setup */
  771. initf_dm,
  772. arch_cpu_init_dm,
  773. #if defined(CONFIG_BOARD_EARLY_INIT_F)
  774. board_early_init_f,
  775. #endif
  776. #if defined(CONFIG_PPC) || defined(CONFIG_SYS_FSL_CLK) || defined(CONFIG_M68K)
  777. /* get CPU and bus clocks according to the environment variable */
  778. get_clocks, /* get CPU and bus clocks (etc.) */
  779. #endif
  780. #if !defined(CONFIG_M68K)
  781. timer_init, /* initialize timer */
  782. #endif
  783. #if defined(CONFIG_BOARD_POSTCLK_INIT)
  784. board_postclk_init,
  785. #endif
  786. env_init, /* initialize environment */
  787. init_baud_rate, /* initialze baudrate settings */
  788. serial_init, /* serial communications setup */
  789. console_init_f, /* stage 1 init of console */
  790. display_options, /* say that we are here */
  791. display_text_info, /* show debugging info if required */
  792. checkcpu,
  793. #if defined(CONFIG_SYSRESET)
  794. print_resetinfo,
  795. #endif
  796. #if defined(CONFIG_DISPLAY_CPUINFO)
  797. print_cpuinfo, /* display cpu info (and speed) */
  798. #endif
  799. #if defined(CONFIG_DTB_RESELECT)
  800. embedded_dtb_select,
  801. #endif
  802. #if defined(CONFIG_DISPLAY_BOARDINFO)
  803. show_board_info,
  804. #endif
  805. INIT_FUNC_WATCHDOG_INIT
  806. #if defined(CONFIG_MISC_INIT_F)
  807. misc_init_f,
  808. #endif
  809. INIT_FUNC_WATCHDOG_RESET
  810. #if defined(CONFIG_SYS_I2C)
  811. init_func_i2c,
  812. #endif
  813. #if defined(CONFIG_VID) && !defined(CONFIG_SPL)
  814. init_func_vid,
  815. #endif
  816. announce_dram_init,
  817. dram_init, /* configure available RAM banks */
  818. #ifdef CONFIG_POST
  819. post_init_f,
  820. #endif
  821. INIT_FUNC_WATCHDOG_RESET
  822. #if defined(CONFIG_SYS_DRAM_TEST)
  823. testdram,
  824. #endif /* CONFIG_SYS_DRAM_TEST */
  825. INIT_FUNC_WATCHDOG_RESET
  826. #ifdef CONFIG_POST
  827. init_post,
  828. #endif
  829. INIT_FUNC_WATCHDOG_RESET
  830. /*
  831. * Now that we have DRAM mapped and working, we can
  832. * relocate the code and continue running from DRAM.
  833. *
  834. * Reserve memory at end of RAM for (top down in that order):
  835. * - area that won't get touched by U-Boot and Linux (optional)
  836. * - kernel log buffer
  837. * - protected RAM
  838. * - LCD framebuffer
  839. * - monitor code
  840. * - board info struct
  841. */
  842. setup_dest_addr,
  843. #ifdef CONFIG_PRAM
  844. reserve_pram,
  845. #endif
  846. reserve_round_4k,
  847. arch_reserve_mmu,
  848. reserve_video,
  849. reserve_trace,
  850. reserve_uboot,
  851. reserve_malloc,
  852. reserve_board,
  853. setup_machine,
  854. reserve_global_data,
  855. reserve_fdt,
  856. reserve_bootstage,
  857. reserve_bloblist,
  858. reserve_arch,
  859. reserve_stacks,
  860. dram_init_banksize,
  861. show_dram_config,
  862. #if defined(CONFIG_M68K) || defined(CONFIG_MIPS) || defined(CONFIG_PPC) || \
  863. defined(CONFIG_SH)
  864. setup_board_part1,
  865. #endif
  866. #if defined(CONFIG_PPC) || defined(CONFIG_M68K)
  867. INIT_FUNC_WATCHDOG_RESET
  868. setup_board_part2,
  869. #endif
  870. display_new_sp,
  871. #ifdef CONFIG_OF_BOARD_FIXUP
  872. fix_fdt,
  873. #endif
  874. INIT_FUNC_WATCHDOG_RESET
  875. reloc_fdt,
  876. reloc_bootstage,
  877. reloc_bloblist,
  878. setup_reloc,
  879. #if defined(CONFIG_X86) || defined(CONFIG_ARC)
  880. copy_uboot_to_ram,
  881. do_elf_reloc_fixups,
  882. #endif
  883. clear_bss,
  884. #if !defined(CONFIG_ARM) && !defined(CONFIG_SANDBOX) && \
  885. !CONFIG_IS_ENABLED(X86_64)
  886. jump_to_copy,
  887. #endif
  888. NULL,
  889. };
  890. void board_init_f(ulong boot_flags)
  891. {
  892. gd->flags = boot_flags;
  893. gd->have_console = 0;
  894. if (initcall_run_list(init_sequence_f))
  895. hang();
  896. #if !defined(CONFIG_ARM) && !defined(CONFIG_SANDBOX) && \
  897. !defined(CONFIG_EFI_APP) && !CONFIG_IS_ENABLED(X86_64) && \
  898. !defined(CONFIG_ARC)
  899. /* NOTREACHED - jump_to_copy() does not return */
  900. hang();
  901. #endif
  902. }
  903. #if defined(CONFIG_X86) || defined(CONFIG_ARC)
  904. /*
  905. * For now this code is only used on x86.
  906. *
  907. * init_sequence_f_r is the list of init functions which are run when
  908. * U-Boot is executing from Flash with a semi-limited 'C' environment.
  909. * The following limitations must be considered when implementing an
  910. * '_f_r' function:
  911. * - 'static' variables are read-only
  912. * - Global Data (gd->xxx) is read/write
  913. *
  914. * The '_f_r' sequence must, as a minimum, copy U-Boot to RAM (if
  915. * supported). It _should_, if possible, copy global data to RAM and
  916. * initialise the CPU caches (to speed up the relocation process)
  917. *
  918. * NOTE: At present only x86 uses this route, but it is intended that
  919. * all archs will move to this when generic relocation is implemented.
  920. */
  921. static const init_fnc_t init_sequence_f_r[] = {
  922. #if !CONFIG_IS_ENABLED(X86_64)
  923. init_cache_f_r,
  924. #endif
  925. NULL,
  926. };
  927. void board_init_f_r(void)
  928. {
  929. if (initcall_run_list(init_sequence_f_r))
  930. hang();
  931. /*
  932. * The pre-relocation drivers may be using memory that has now gone
  933. * away. Mark serial as unavailable - this will fall back to the debug
  934. * UART if available.
  935. *
  936. * Do the same with log drivers since the memory may not be available.
  937. */
  938. gd->flags &= ~(GD_FLG_SERIAL_READY | GD_FLG_LOG_READY);
  939. #ifdef CONFIG_TIMER
  940. gd->timer = NULL;
  941. #endif
  942. /*
  943. * U-Boot has been copied into SDRAM, the BSS has been cleared etc.
  944. * Transfer execution from Flash to RAM by calculating the address
  945. * of the in-RAM copy of board_init_r() and calling it
  946. */
  947. (board_init_r + gd->reloc_off)((gd_t *)gd, gd->relocaddr);
  948. /* NOTREACHED - board_init_r() does not return */
  949. hang();
  950. }
  951. #endif /* CONFIG_X86 */