serial_mtk.c 11 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * MediaTek High-speed UART driver
  4. *
  5. * Copyright (C) 2018 MediaTek Inc.
  6. * Author: Weijie Gao <weijie.gao@mediatek.com>
  7. */
  8. #include <clk.h>
  9. #include <common.h>
  10. #include <div64.h>
  11. #include <dm.h>
  12. #include <errno.h>
  13. #include <log.h>
  14. #include <serial.h>
  15. #include <watchdog.h>
  16. #include <asm/global_data.h>
  17. #include <asm/io.h>
  18. #include <asm/types.h>
  19. #include <linux/err.h>
  20. struct mtk_serial_regs {
  21. u32 rbr;
  22. u32 ier;
  23. u32 fcr;
  24. u32 lcr;
  25. u32 mcr;
  26. u32 lsr;
  27. u32 msr;
  28. u32 spr;
  29. u32 mdr1;
  30. u32 highspeed;
  31. u32 sample_count;
  32. u32 sample_point;
  33. u32 fracdiv_l;
  34. u32 fracdiv_m;
  35. u32 escape_en;
  36. u32 guard;
  37. u32 rx_sel;
  38. };
  39. #define thr rbr
  40. #define iir fcr
  41. #define dll rbr
  42. #define dlm ier
  43. #define UART_LCR_WLS_8 0x03 /* 8 bit character length */
  44. #define UART_LCR_DLAB 0x80 /* Divisor latch access bit */
  45. #define UART_LSR_DR 0x01 /* Data ready */
  46. #define UART_LSR_THRE 0x20 /* Xmit holding register empty */
  47. #define UART_LSR_TEMT 0x40 /* Xmitter empty */
  48. #define UART_MCR_DTR 0x01 /* DTR */
  49. #define UART_MCR_RTS 0x02 /* RTS */
  50. #define UART_FCR_FIFO_EN 0x01 /* Fifo enable */
  51. #define UART_FCR_RXSR 0x02 /* Receiver soft reset */
  52. #define UART_FCR_TXSR 0x04 /* Transmitter soft reset */
  53. #define UART_MCRVAL (UART_MCR_DTR | \
  54. UART_MCR_RTS)
  55. /* Clear & enable FIFOs */
  56. #define UART_FCRVAL (UART_FCR_FIFO_EN | \
  57. UART_FCR_RXSR | \
  58. UART_FCR_TXSR)
  59. /* the data is correct if the real baud is within 3%. */
  60. #define BAUD_ALLOW_MAX(baud) ((baud) + (baud) * 3 / 100)
  61. #define BAUD_ALLOW_MIX(baud) ((baud) - (baud) * 3 / 100)
  62. struct mtk_serial_priv {
  63. struct mtk_serial_regs __iomem *regs;
  64. u32 clock;
  65. bool force_highspeed;
  66. };
  67. static void _mtk_serial_setbrg(struct mtk_serial_priv *priv, int baud)
  68. {
  69. u32 quot, realbaud, samplecount = 1;
  70. /* Special case for low baud clock */
  71. if (baud <= 115200 && priv->clock <= 12000000) {
  72. writel(3, &priv->regs->highspeed);
  73. quot = DIV_ROUND_CLOSEST(priv->clock, 256 * baud);
  74. if (quot == 0)
  75. quot = 1;
  76. samplecount = DIV_ROUND_CLOSEST(priv->clock, quot * baud);
  77. realbaud = priv->clock / samplecount / quot;
  78. if (realbaud > BAUD_ALLOW_MAX(baud) ||
  79. realbaud < BAUD_ALLOW_MIX(baud)) {
  80. pr_info("baud %d can't be handled\n", baud);
  81. }
  82. goto set_baud;
  83. }
  84. if (priv->force_highspeed)
  85. goto use_hs3;
  86. if (baud <= 115200) {
  87. writel(0, &priv->regs->highspeed);
  88. quot = DIV_ROUND_CLOSEST(priv->clock, 16 * baud);
  89. } else if (baud <= 576000) {
  90. writel(2, &priv->regs->highspeed);
  91. /* Set to next lower baudrate supported */
  92. if ((baud == 500000) || (baud == 576000))
  93. baud = 460800;
  94. quot = DIV_ROUND_UP(priv->clock, 4 * baud);
  95. } else {
  96. use_hs3:
  97. writel(3, &priv->regs->highspeed);
  98. quot = DIV_ROUND_UP(priv->clock, 256 * baud);
  99. samplecount = DIV_ROUND_CLOSEST(priv->clock, quot * baud);
  100. }
  101. set_baud:
  102. /* set divisor */
  103. writel(UART_LCR_WLS_8 | UART_LCR_DLAB, &priv->regs->lcr);
  104. writel(quot & 0xff, &priv->regs->dll);
  105. writel((quot >> 8) & 0xff, &priv->regs->dlm);
  106. writel(UART_LCR_WLS_8, &priv->regs->lcr);
  107. /* set highspeed mode sample count & point */
  108. writel(samplecount - 1, &priv->regs->sample_count);
  109. writel((samplecount - 2) >> 1, &priv->regs->sample_point);
  110. }
  111. static int _mtk_serial_putc(struct mtk_serial_priv *priv, const char ch)
  112. {
  113. if (!(readl(&priv->regs->lsr) & UART_LSR_THRE))
  114. return -EAGAIN;
  115. writel(ch, &priv->regs->thr);
  116. if (ch == '\n')
  117. WATCHDOG_RESET();
  118. return 0;
  119. }
  120. static int _mtk_serial_getc(struct mtk_serial_priv *priv)
  121. {
  122. if (!(readl(&priv->regs->lsr) & UART_LSR_DR))
  123. return -EAGAIN;
  124. return readl(&priv->regs->rbr);
  125. }
  126. static int _mtk_serial_pending(struct mtk_serial_priv *priv, bool input)
  127. {
  128. if (input)
  129. return (readl(&priv->regs->lsr) & UART_LSR_DR) ? 1 : 0;
  130. else
  131. return (readl(&priv->regs->lsr) & UART_LSR_THRE) ? 0 : 1;
  132. }
  133. #if defined(CONFIG_DM_SERIAL) && \
  134. (!defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_DM))
  135. static int mtk_serial_setbrg(struct udevice *dev, int baudrate)
  136. {
  137. struct mtk_serial_priv *priv = dev_get_priv(dev);
  138. _mtk_serial_setbrg(priv, baudrate);
  139. return 0;
  140. }
  141. static int mtk_serial_putc(struct udevice *dev, const char ch)
  142. {
  143. struct mtk_serial_priv *priv = dev_get_priv(dev);
  144. return _mtk_serial_putc(priv, ch);
  145. }
  146. static int mtk_serial_getc(struct udevice *dev)
  147. {
  148. struct mtk_serial_priv *priv = dev_get_priv(dev);
  149. return _mtk_serial_getc(priv);
  150. }
  151. static int mtk_serial_pending(struct udevice *dev, bool input)
  152. {
  153. struct mtk_serial_priv *priv = dev_get_priv(dev);
  154. return _mtk_serial_pending(priv, input);
  155. }
  156. static int mtk_serial_probe(struct udevice *dev)
  157. {
  158. struct mtk_serial_priv *priv = dev_get_priv(dev);
  159. /* Disable interrupt */
  160. writel(0, &priv->regs->ier);
  161. writel(UART_MCRVAL, &priv->regs->mcr);
  162. writel(UART_FCRVAL, &priv->regs->fcr);
  163. return 0;
  164. }
  165. static int mtk_serial_of_to_plat(struct udevice *dev)
  166. {
  167. struct mtk_serial_priv *priv = dev_get_priv(dev);
  168. fdt_addr_t addr;
  169. struct clk clk;
  170. int err;
  171. addr = dev_read_addr(dev);
  172. if (addr == FDT_ADDR_T_NONE)
  173. return -EINVAL;
  174. priv->regs = map_physmem(addr, 0, MAP_NOCACHE);
  175. err = clk_get_by_index(dev, 0, &clk);
  176. if (!err) {
  177. err = clk_get_rate(&clk);
  178. if (!IS_ERR_VALUE(err))
  179. priv->clock = err;
  180. } else if (err != -ENOENT && err != -ENODEV && err != -ENOSYS) {
  181. debug("mtk_serial: failed to get clock\n");
  182. return err;
  183. }
  184. if (!priv->clock)
  185. priv->clock = dev_read_u32_default(dev, "clock-frequency", 0);
  186. if (!priv->clock) {
  187. debug("mtk_serial: clock not defined\n");
  188. return -EINVAL;
  189. }
  190. priv->force_highspeed = dev_read_bool(dev, "mediatek,force-highspeed");
  191. return 0;
  192. }
  193. static const struct dm_serial_ops mtk_serial_ops = {
  194. .putc = mtk_serial_putc,
  195. .pending = mtk_serial_pending,
  196. .getc = mtk_serial_getc,
  197. .setbrg = mtk_serial_setbrg,
  198. };
  199. static const struct udevice_id mtk_serial_ids[] = {
  200. { .compatible = "mediatek,hsuart" },
  201. { .compatible = "mediatek,mt6577-uart" },
  202. { }
  203. };
  204. U_BOOT_DRIVER(serial_mtk) = {
  205. .name = "serial_mtk",
  206. .id = UCLASS_SERIAL,
  207. .of_match = mtk_serial_ids,
  208. .of_to_plat = mtk_serial_of_to_plat,
  209. .priv_auto = sizeof(struct mtk_serial_priv),
  210. .probe = mtk_serial_probe,
  211. .ops = &mtk_serial_ops,
  212. .flags = DM_FLAG_PRE_RELOC,
  213. };
  214. #else
  215. DECLARE_GLOBAL_DATA_PTR;
  216. #define DECLARE_HSUART_PRIV(port) \
  217. static struct mtk_serial_priv mtk_hsuart##port = { \
  218. .regs = (struct mtk_serial_regs *)CONFIG_SYS_NS16550_COM##port, \
  219. .clock = CONFIG_SYS_NS16550_CLK \
  220. };
  221. #define DECLARE_HSUART_FUNCTIONS(port) \
  222. static int mtk_serial##port##_init(void) \
  223. { \
  224. writel(0, &mtk_hsuart##port.regs->ier); \
  225. writel(UART_MCRVAL, &mtk_hsuart##port.regs->mcr); \
  226. writel(UART_FCRVAL, &mtk_hsuart##port.regs->fcr); \
  227. _mtk_serial_setbrg(&mtk_hsuart##port, gd->baudrate); \
  228. return 0 ; \
  229. } \
  230. static void mtk_serial##port##_setbrg(void) \
  231. { \
  232. _mtk_serial_setbrg(&mtk_hsuart##port, gd->baudrate); \
  233. } \
  234. static int mtk_serial##port##_getc(void) \
  235. { \
  236. int err; \
  237. do { \
  238. err = _mtk_serial_getc(&mtk_hsuart##port); \
  239. if (err == -EAGAIN) \
  240. WATCHDOG_RESET(); \
  241. } while (err == -EAGAIN); \
  242. return err >= 0 ? err : 0; \
  243. } \
  244. static int mtk_serial##port##_tstc(void) \
  245. { \
  246. return _mtk_serial_pending(&mtk_hsuart##port, true); \
  247. } \
  248. static void mtk_serial##port##_putc(const char c) \
  249. { \
  250. int err; \
  251. if (c == '\n') \
  252. mtk_serial##port##_putc('\r'); \
  253. do { \
  254. err = _mtk_serial_putc(&mtk_hsuart##port, c); \
  255. } while (err == -EAGAIN); \
  256. } \
  257. static void mtk_serial##port##_puts(const char *s) \
  258. { \
  259. while (*s) { \
  260. mtk_serial##port##_putc(*s++); \
  261. } \
  262. }
  263. /* Serial device descriptor */
  264. #define INIT_HSUART_STRUCTURE(port, __name) { \
  265. .name = __name, \
  266. .start = mtk_serial##port##_init, \
  267. .stop = NULL, \
  268. .setbrg = mtk_serial##port##_setbrg, \
  269. .getc = mtk_serial##port##_getc, \
  270. .tstc = mtk_serial##port##_tstc, \
  271. .putc = mtk_serial##port##_putc, \
  272. .puts = mtk_serial##port##_puts, \
  273. }
  274. #define DECLARE_HSUART(port, __name) \
  275. DECLARE_HSUART_PRIV(port); \
  276. DECLARE_HSUART_FUNCTIONS(port); \
  277. struct serial_device mtk_hsuart##port##_device = \
  278. INIT_HSUART_STRUCTURE(port, __name);
  279. #if !defined(CONFIG_CONS_INDEX)
  280. #elif (CONFIG_CONS_INDEX < 1) || (CONFIG_CONS_INDEX > 6)
  281. #error "Invalid console index value."
  282. #endif
  283. #if CONFIG_CONS_INDEX == 1 && !defined(CONFIG_SYS_NS16550_COM1)
  284. #error "Console port 1 defined but not configured."
  285. #elif CONFIG_CONS_INDEX == 2 && !defined(CONFIG_SYS_NS16550_COM2)
  286. #error "Console port 2 defined but not configured."
  287. #elif CONFIG_CONS_INDEX == 3 && !defined(CONFIG_SYS_NS16550_COM3)
  288. #error "Console port 3 defined but not configured."
  289. #elif CONFIG_CONS_INDEX == 4 && !defined(CONFIG_SYS_NS16550_COM4)
  290. #error "Console port 4 defined but not configured."
  291. #elif CONFIG_CONS_INDEX == 5 && !defined(CONFIG_SYS_NS16550_COM5)
  292. #error "Console port 5 defined but not configured."
  293. #elif CONFIG_CONS_INDEX == 6 && !defined(CONFIG_SYS_NS16550_COM6)
  294. #error "Console port 6 defined but not configured."
  295. #endif
  296. #if defined(CONFIG_SYS_NS16550_COM1)
  297. DECLARE_HSUART(1, "mtk-hsuart0");
  298. #endif
  299. #if defined(CONFIG_SYS_NS16550_COM2)
  300. DECLARE_HSUART(2, "mtk-hsuart1");
  301. #endif
  302. #if defined(CONFIG_SYS_NS16550_COM3)
  303. DECLARE_HSUART(3, "mtk-hsuart2");
  304. #endif
  305. #if defined(CONFIG_SYS_NS16550_COM4)
  306. DECLARE_HSUART(4, "mtk-hsuart3");
  307. #endif
  308. #if defined(CONFIG_SYS_NS16550_COM5)
  309. DECLARE_HSUART(5, "mtk-hsuart4");
  310. #endif
  311. #if defined(CONFIG_SYS_NS16550_COM6)
  312. DECLARE_HSUART(6, "mtk-hsuart5");
  313. #endif
  314. __weak struct serial_device *default_serial_console(void)
  315. {
  316. #if CONFIG_CONS_INDEX == 1
  317. return &mtk_hsuart1_device;
  318. #elif CONFIG_CONS_INDEX == 2
  319. return &mtk_hsuart2_device;
  320. #elif CONFIG_CONS_INDEX == 3
  321. return &mtk_hsuart3_device;
  322. #elif CONFIG_CONS_INDEX == 4
  323. return &mtk_hsuart4_device;
  324. #elif CONFIG_CONS_INDEX == 5
  325. return &mtk_hsuart5_device;
  326. #elif CONFIG_CONS_INDEX == 6
  327. return &mtk_hsuart6_device;
  328. #else
  329. #error "Bad CONFIG_CONS_INDEX."
  330. #endif
  331. }
  332. void mtk_serial_initialize(void)
  333. {
  334. #if defined(CONFIG_SYS_NS16550_COM1)
  335. serial_register(&mtk_hsuart1_device);
  336. #endif
  337. #if defined(CONFIG_SYS_NS16550_COM2)
  338. serial_register(&mtk_hsuart2_device);
  339. #endif
  340. #if defined(CONFIG_SYS_NS16550_COM3)
  341. serial_register(&mtk_hsuart3_device);
  342. #endif
  343. #if defined(CONFIG_SYS_NS16550_COM4)
  344. serial_register(&mtk_hsuart4_device);
  345. #endif
  346. #if defined(CONFIG_SYS_NS16550_COM5)
  347. serial_register(&mtk_hsuart5_device);
  348. #endif
  349. #if defined(CONFIG_SYS_NS16550_COM6)
  350. serial_register(&mtk_hsuart6_device);
  351. #endif
  352. }
  353. #endif
  354. #ifdef CONFIG_DEBUG_UART_MTK
  355. #include <debug_uart.h>
  356. static inline void _debug_uart_init(void)
  357. {
  358. struct mtk_serial_priv priv;
  359. priv.regs = (void *) CONFIG_DEBUG_UART_BASE;
  360. priv.clock = CONFIG_DEBUG_UART_CLOCK;
  361. writel(0, &priv.regs->ier);
  362. writel(UART_MCRVAL, &priv.regs->mcr);
  363. writel(UART_FCRVAL, &priv.regs->fcr);
  364. _mtk_serial_setbrg(&priv, CONFIG_BAUDRATE);
  365. }
  366. static inline void _debug_uart_putc(int ch)
  367. {
  368. struct mtk_serial_regs __iomem *regs =
  369. (void *) CONFIG_DEBUG_UART_BASE;
  370. while (!(readl(&regs->lsr) & UART_LSR_THRE))
  371. ;
  372. writel(ch, &regs->thr);
  373. }
  374. DEBUG_UART_FUNCS
  375. #endif