tpm-v2.h 17 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Defines APIs and structures that allow software to interact with a
  4. * TPM2 device
  5. *
  6. * Copyright (c) 2020 Linaro
  7. * Copyright (c) 2018 Bootlin
  8. *
  9. * https://trustedcomputinggroup.org/resource/tss-overview-common-structures-specification/
  10. *
  11. * Author: Miquel Raynal <miquel.raynal@bootlin.com>
  12. */
  13. #ifndef __TPM_V2_H
  14. #define __TPM_V2_H
  15. #include <tpm-common.h>
  16. struct udevice;
  17. #define TPM2_DIGEST_LEN 32
  18. #define TPM2_SHA1_DIGEST_SIZE 20
  19. #define TPM2_SHA256_DIGEST_SIZE 32
  20. #define TPM2_SHA384_DIGEST_SIZE 48
  21. #define TPM2_SHA512_DIGEST_SIZE 64
  22. #define TPM2_SM3_256_DIGEST_SIZE 32
  23. #define TPM2_MAX_PCRS 32
  24. #define TPM2_PCR_SELECT_MAX ((TPM2_MAX_PCRS + 7) / 8)
  25. #define TPM2_MAX_CAP_BUFFER 1024
  26. #define TPM2_MAX_TPM_PROPERTIES ((TPM2_MAX_CAP_BUFFER - sizeof(u32) /* TPM2_CAP */ - \
  27. sizeof(u32)) / sizeof(struct tpms_tagged_property))
  28. #define TPM2_HDR_LEN 10
  29. /*
  30. * We deviate from this draft of the specification by increasing the value of
  31. * TPM2_NUM_PCR_BANKS from 3 to 16 to ensure compatibility with TPM2
  32. * implementations that have enabled a larger than typical number of PCR
  33. * banks. This larger value for TPM2_NUM_PCR_BANKS is expected to be included
  34. * in a future revision of the specification.
  35. */
  36. #define TPM2_NUM_PCR_BANKS 16
  37. /* Definition of (UINT32) TPM2_CAP Constants */
  38. #define TPM2_CAP_PCRS 0x00000005U
  39. #define TPM2_CAP_TPM_PROPERTIES 0x00000006U
  40. /* Definition of (UINT32) TPM2_PT Constants */
  41. #define TPM2_PT_GROUP (u32)(0x00000100)
  42. #define TPM2_PT_FIXED (u32)(TPM2_PT_GROUP * 1)
  43. #define TPM2_PT_MANUFACTURER (u32)(TPM2_PT_FIXED + 5)
  44. #define TPM2_PT_PCR_COUNT (u32)(TPM2_PT_FIXED + 18)
  45. #define TPM2_PT_MAX_COMMAND_SIZE (u32)(TPM2_PT_FIXED + 30)
  46. #define TPM2_PT_MAX_RESPONSE_SIZE (u32)(TPM2_PT_FIXED + 31)
  47. /*
  48. * event types, cf.
  49. * "TCG Server Management Domain Firmware Profile Specification",
  50. * rev 1.00, 2020-05-01
  51. */
  52. #define EV_POST_CODE ((u32)0x00000001)
  53. #define EV_NO_ACTION ((u32)0x00000003)
  54. #define EV_SEPARATOR ((u32)0x00000004)
  55. #define EV_ACTION ((u32)0x00000005)
  56. #define EV_TAG ((u32)0x00000006)
  57. #define EV_S_CRTM_CONTENTS ((u32)0x00000007)
  58. #define EV_S_CRTM_VERSION ((u32)0x00000008)
  59. #define EV_CPU_MICROCODE ((u32)0x00000009)
  60. #define EV_PLATFORM_CONFIG_FLAGS ((u32)0x0000000A)
  61. #define EV_TABLE_OF_DEVICES ((u32)0x0000000B)
  62. #define EV_COMPACT_HASH ((u32)0x0000000C)
  63. /*
  64. * event types, cf.
  65. * "TCG PC Client Platform Firmware Profile Specification", Family "2.0"
  66. * rev 1.04, June 3, 2019
  67. */
  68. #define EV_EFI_EVENT_BASE ((u32)0x80000000)
  69. #define EV_EFI_VARIABLE_DRIVER_CONFIG ((u32)0x80000001)
  70. #define EV_EFI_VARIABLE_BOOT ((u32)0x80000002)
  71. #define EV_EFI_BOOT_SERVICES_APPLICATION ((u32)0x80000003)
  72. #define EV_EFI_BOOT_SERVICES_DRIVER ((u32)0x80000004)
  73. #define EV_EFI_RUNTIME_SERVICES_DRIVER ((u32)0x80000005)
  74. #define EV_EFI_GPT_EVENT ((u32)0x80000006)
  75. #define EV_EFI_ACTION ((u32)0x80000007)
  76. #define EV_EFI_PLATFORM_FIRMWARE_BLOB ((u32)0x80000008)
  77. #define EV_EFI_HANDOFF_TABLES ((u32)0x80000009)
  78. #define EV_EFI_HCRTM_EVENT ((u32)0x80000010)
  79. #define EV_EFI_VARIABLE_AUTHORITY ((u32)0x800000E0)
  80. /* TPMS_TAGGED_PROPERTY Structure */
  81. struct tpms_tagged_property {
  82. u32 property;
  83. u32 value;
  84. } __packed;
  85. /* TPMS_PCR_SELECTION Structure */
  86. struct tpms_pcr_selection {
  87. u16 hash;
  88. u8 size_of_select;
  89. u8 pcr_select[TPM2_PCR_SELECT_MAX];
  90. } __packed;
  91. /* TPML_PCR_SELECTION Structure */
  92. struct tpml_pcr_selection {
  93. u32 count;
  94. struct tpms_pcr_selection selection[TPM2_NUM_PCR_BANKS];
  95. } __packed;
  96. /* TPML_TAGGED_TPM_PROPERTY Structure */
  97. struct tpml_tagged_tpm_property {
  98. u32 count;
  99. struct tpms_tagged_property tpm_property[TPM2_MAX_TPM_PROPERTIES];
  100. } __packed;
  101. /* TPMU_CAPABILITIES Union */
  102. union tpmu_capabilities {
  103. /*
  104. * Non exhaustive. Only added the structs needed for our
  105. * current code
  106. */
  107. struct tpml_pcr_selection assigned_pcr;
  108. struct tpml_tagged_tpm_property tpm_properties;
  109. } __packed;
  110. /* TPMS_CAPABILITY_DATA Structure */
  111. struct tpms_capability_data {
  112. u32 capability;
  113. union tpmu_capabilities data;
  114. } __packed;
  115. /**
  116. * SHA1 Event Log Entry Format
  117. *
  118. * @pcr_index: PCRIndex event extended to
  119. * @event_type: Type of event (see EFI specs)
  120. * @digest: Value extended into PCR index
  121. * @event_size: Size of event
  122. * @event: Event data
  123. */
  124. struct tcg_pcr_event {
  125. u32 pcr_index;
  126. u32 event_type;
  127. u8 digest[TPM2_SHA1_DIGEST_SIZE];
  128. u32 event_size;
  129. u8 event[];
  130. } __packed;
  131. /**
  132. * Definition of TPMU_HA Union
  133. */
  134. union tmpu_ha {
  135. u8 sha1[TPM2_SHA1_DIGEST_SIZE];
  136. u8 sha256[TPM2_SHA256_DIGEST_SIZE];
  137. u8 sm3_256[TPM2_SM3_256_DIGEST_SIZE];
  138. u8 sha384[TPM2_SHA384_DIGEST_SIZE];
  139. u8 sha512[TPM2_SHA512_DIGEST_SIZE];
  140. } __packed;
  141. /**
  142. * Definition of TPMT_HA Structure
  143. *
  144. * @hash_alg: Hash algorithm defined in enum tpm2_algorithms
  145. * @digest: Digest value for a given algorithm
  146. */
  147. struct tpmt_ha {
  148. u16 hash_alg;
  149. union tmpu_ha digest;
  150. } __packed;
  151. /**
  152. * Definition of TPML_DIGEST_VALUES Structure
  153. *
  154. * @count: Number of algorithms supported by hardware
  155. * @digests: struct for algorithm id and hash value
  156. */
  157. struct tpml_digest_values {
  158. u32 count;
  159. struct tpmt_ha digests[TPM2_NUM_PCR_BANKS];
  160. } __packed;
  161. /**
  162. * Crypto Agile Log Entry Format
  163. *
  164. * @pcr_index: PCRIndex event extended to
  165. * @event_type: Type of event
  166. * @digests: List of digestsextended to PCR index
  167. * @event_size: Size of the event data
  168. * @event: Event data
  169. */
  170. struct tcg_pcr_event2 {
  171. u32 pcr_index;
  172. u32 event_type;
  173. struct tpml_digest_values digests;
  174. u32 event_size;
  175. u8 event[];
  176. } __packed;
  177. /**
  178. * TPM2 Structure Tags for command/response buffers.
  179. *
  180. * @TPM2_ST_NO_SESSIONS: the command does not need an authentication.
  181. * @TPM2_ST_SESSIONS: the command needs an authentication.
  182. */
  183. enum tpm2_structures {
  184. TPM2_ST_NO_SESSIONS = 0x8001,
  185. TPM2_ST_SESSIONS = 0x8002,
  186. };
  187. /**
  188. * TPM2 type of boolean.
  189. */
  190. enum tpm2_yes_no {
  191. TPMI_YES = 1,
  192. TPMI_NO = 0,
  193. };
  194. /**
  195. * TPM2 startup values.
  196. *
  197. * @TPM2_SU_CLEAR: reset the internal state.
  198. * @TPM2_SU_STATE: restore saved state (if any).
  199. */
  200. enum tpm2_startup_types {
  201. TPM2_SU_CLEAR = 0x0000,
  202. TPM2_SU_STATE = 0x0001,
  203. };
  204. /**
  205. * TPM2 permanent handles.
  206. *
  207. * @TPM2_RH_OWNER: refers to the 'owner' hierarchy.
  208. * @TPM2_RS_PW: indicates a password.
  209. * @TPM2_RH_LOCKOUT: refers to the 'lockout' hierarchy.
  210. * @TPM2_RH_ENDORSEMENT: refers to the 'endorsement' hierarchy.
  211. * @TPM2_RH_PLATFORM: refers to the 'platform' hierarchy.
  212. */
  213. enum tpm2_handles {
  214. TPM2_RH_OWNER = 0x40000001,
  215. TPM2_RS_PW = 0x40000009,
  216. TPM2_RH_LOCKOUT = 0x4000000A,
  217. TPM2_RH_ENDORSEMENT = 0x4000000B,
  218. TPM2_RH_PLATFORM = 0x4000000C,
  219. };
  220. /**
  221. * TPM2 command codes used at the beginning of a buffer, gives the command.
  222. *
  223. * @TPM2_CC_STARTUP: TPM2_Startup().
  224. * @TPM2_CC_SELF_TEST: TPM2_SelfTest().
  225. * @TPM2_CC_CLEAR: TPM2_Clear().
  226. * @TPM2_CC_CLEARCONTROL: TPM2_ClearControl().
  227. * @TPM2_CC_HIERCHANGEAUTH: TPM2_HierarchyChangeAuth().
  228. * @TPM2_CC_PCR_SETAUTHPOL: TPM2_PCR_SetAuthPolicy().
  229. * @TPM2_CC_DAM_RESET: TPM2_DictionaryAttackLockReset().
  230. * @TPM2_CC_DAM_PARAMETERS: TPM2_DictionaryAttackParameters().
  231. * @TPM2_CC_GET_CAPABILITY: TPM2_GetCapibility().
  232. * @TPM2_CC_GET_RANDOM: TPM2_GetRandom().
  233. * @TPM2_CC_PCR_READ: TPM2_PCR_Read().
  234. * @TPM2_CC_PCR_EXTEND: TPM2_PCR_Extend().
  235. * @TPM2_CC_PCR_SETAUTHVAL: TPM2_PCR_SetAuthValue().
  236. */
  237. enum tpm2_command_codes {
  238. TPM2_CC_STARTUP = 0x0144,
  239. TPM2_CC_SELF_TEST = 0x0143,
  240. TPM2_CC_HIER_CONTROL = 0x0121,
  241. TPM2_CC_CLEAR = 0x0126,
  242. TPM2_CC_CLEARCONTROL = 0x0127,
  243. TPM2_CC_HIERCHANGEAUTH = 0x0129,
  244. TPM2_CC_NV_DEFINE_SPACE = 0x012a,
  245. TPM2_CC_PCR_SETAUTHPOL = 0x012C,
  246. TPM2_CC_NV_WRITE = 0x0137,
  247. TPM2_CC_NV_WRITELOCK = 0x0138,
  248. TPM2_CC_DAM_RESET = 0x0139,
  249. TPM2_CC_DAM_PARAMETERS = 0x013A,
  250. TPM2_CC_NV_READ = 0x014E,
  251. TPM2_CC_GET_CAPABILITY = 0x017A,
  252. TPM2_CC_GET_RANDOM = 0x017B,
  253. TPM2_CC_PCR_READ = 0x017E,
  254. TPM2_CC_PCR_EXTEND = 0x0182,
  255. TPM2_CC_PCR_SETAUTHVAL = 0x0183,
  256. };
  257. /**
  258. * TPM2 return codes.
  259. */
  260. enum tpm2_return_codes {
  261. TPM2_RC_SUCCESS = 0x0000,
  262. TPM2_RC_BAD_TAG = 0x001E,
  263. TPM2_RC_FMT1 = 0x0080,
  264. TPM2_RC_HASH = TPM2_RC_FMT1 + 0x0003,
  265. TPM2_RC_VALUE = TPM2_RC_FMT1 + 0x0004,
  266. TPM2_RC_SIZE = TPM2_RC_FMT1 + 0x0015,
  267. TPM2_RC_BAD_AUTH = TPM2_RC_FMT1 + 0x0022,
  268. TPM2_RC_HANDLE = TPM2_RC_FMT1 + 0x000B,
  269. TPM2_RC_VER1 = 0x0100,
  270. TPM2_RC_INITIALIZE = TPM2_RC_VER1 + 0x0000,
  271. TPM2_RC_FAILURE = TPM2_RC_VER1 + 0x0001,
  272. TPM2_RC_DISABLED = TPM2_RC_VER1 + 0x0020,
  273. TPM2_RC_AUTH_MISSING = TPM2_RC_VER1 + 0x0025,
  274. TPM2_RC_COMMAND_CODE = TPM2_RC_VER1 + 0x0043,
  275. TPM2_RC_AUTHSIZE = TPM2_RC_VER1 + 0x0044,
  276. TPM2_RC_AUTH_CONTEXT = TPM2_RC_VER1 + 0x0045,
  277. TPM2_RC_NV_DEFINED = TPM2_RC_VER1 + 0x004c,
  278. TPM2_RC_NEEDS_TEST = TPM2_RC_VER1 + 0x0053,
  279. TPM2_RC_WARN = 0x0900,
  280. TPM2_RC_TESTING = TPM2_RC_WARN + 0x000A,
  281. TPM2_RC_REFERENCE_H0 = TPM2_RC_WARN + 0x0010,
  282. TPM2_RC_LOCKOUT = TPM2_RC_WARN + 0x0021,
  283. };
  284. /**
  285. * TPM2 algorithms.
  286. */
  287. enum tpm2_algorithms {
  288. TPM2_ALG_SHA1 = 0x04,
  289. TPM2_ALG_XOR = 0x0A,
  290. TPM2_ALG_SHA256 = 0x0B,
  291. TPM2_ALG_SHA384 = 0x0C,
  292. TPM2_ALG_SHA512 = 0x0D,
  293. TPM2_ALG_NULL = 0x10,
  294. TPM2_ALG_SM3_256 = 0x12,
  295. };
  296. /* NV index attributes */
  297. enum tpm_index_attrs {
  298. TPMA_NV_PPWRITE = 1UL << 0,
  299. TPMA_NV_OWNERWRITE = 1UL << 1,
  300. TPMA_NV_AUTHWRITE = 1UL << 2,
  301. TPMA_NV_POLICYWRITE = 1UL << 3,
  302. TPMA_NV_COUNTER = 1UL << 4,
  303. TPMA_NV_BITS = 1UL << 5,
  304. TPMA_NV_EXTEND = 1UL << 6,
  305. TPMA_NV_POLICY_DELETE = 1UL << 10,
  306. TPMA_NV_WRITELOCKED = 1UL << 11,
  307. TPMA_NV_WRITEALL = 1UL << 12,
  308. TPMA_NV_WRITEDEFINE = 1UL << 13,
  309. TPMA_NV_WRITE_STCLEAR = 1UL << 14,
  310. TPMA_NV_GLOBALLOCK = 1UL << 15,
  311. TPMA_NV_PPREAD = 1UL << 16,
  312. TPMA_NV_OWNERREAD = 1UL << 17,
  313. TPMA_NV_AUTHREAD = 1UL << 18,
  314. TPMA_NV_POLICYREAD = 1UL << 19,
  315. TPMA_NV_NO_DA = 1UL << 25,
  316. TPMA_NV_ORDERLY = 1UL << 26,
  317. TPMA_NV_CLEAR_STCLEAR = 1UL << 27,
  318. TPMA_NV_READLOCKED = 1UL << 28,
  319. TPMA_NV_WRITTEN = 1UL << 29,
  320. TPMA_NV_PLATFORMCREATE = 1UL << 30,
  321. TPMA_NV_READ_STCLEAR = 1UL << 31,
  322. TPMA_NV_MASK_READ = TPMA_NV_PPREAD | TPMA_NV_OWNERREAD |
  323. TPMA_NV_AUTHREAD | TPMA_NV_POLICYREAD,
  324. TPMA_NV_MASK_WRITE = TPMA_NV_PPWRITE | TPMA_NV_OWNERWRITE |
  325. TPMA_NV_AUTHWRITE | TPMA_NV_POLICYWRITE,
  326. };
  327. enum {
  328. TPM_ACCESS_VALID = 1 << 7,
  329. TPM_ACCESS_ACTIVE_LOCALITY = 1 << 5,
  330. TPM_ACCESS_REQUEST_PENDING = 1 << 2,
  331. TPM_ACCESS_REQUEST_USE = 1 << 1,
  332. TPM_ACCESS_ESTABLISHMENT = 1 << 0,
  333. };
  334. enum {
  335. TPM_STS_FAMILY_SHIFT = 26,
  336. TPM_STS_FAMILY_MASK = 0x3 << TPM_STS_FAMILY_SHIFT,
  337. TPM_STS_FAMILY_TPM2 = 1 << TPM_STS_FAMILY_SHIFT,
  338. TPM_STS_RESE_TESTABLISMENT_BIT = 1 << 25,
  339. TPM_STS_COMMAND_CANCEL = 1 << 24,
  340. TPM_STS_BURST_COUNT_SHIFT = 8,
  341. TPM_STS_BURST_COUNT_MASK = 0xffff << TPM_STS_BURST_COUNT_SHIFT,
  342. TPM_STS_VALID = 1 << 7,
  343. TPM_STS_COMMAND_READY = 1 << 6,
  344. TPM_STS_GO = 1 << 5,
  345. TPM_STS_DATA_AVAIL = 1 << 4,
  346. TPM_STS_DATA_EXPECT = 1 << 3,
  347. TPM_STS_SELF_TEST_DONE = 1 << 2,
  348. TPM_STS_RESPONSE_RETRY = 1 << 1,
  349. };
  350. enum {
  351. TPM_CMD_COUNT_OFFSET = 2,
  352. TPM_CMD_ORDINAL_OFFSET = 6,
  353. TPM_MAX_BUF_SIZE = 1260,
  354. };
  355. enum {
  356. /* Secure storage for firmware settings */
  357. TPM_HT_PCR = 0,
  358. TPM_HT_NV_INDEX,
  359. TPM_HT_HMAC_SESSION,
  360. TPM_HT_POLICY_SESSION,
  361. HR_SHIFT = 24,
  362. HR_PCR = TPM_HT_PCR << HR_SHIFT,
  363. HR_HMAC_SESSION = TPM_HT_HMAC_SESSION << HR_SHIFT,
  364. HR_POLICY_SESSION = TPM_HT_POLICY_SESSION << HR_SHIFT,
  365. HR_NV_INDEX = TPM_HT_NV_INDEX << HR_SHIFT,
  366. };
  367. /**
  368. * Issue a TPM2_Startup command.
  369. *
  370. * @dev TPM device
  371. * @mode TPM startup mode
  372. *
  373. * @return code of the operation
  374. */
  375. u32 tpm2_startup(struct udevice *dev, enum tpm2_startup_types mode);
  376. /**
  377. * Issue a TPM2_SelfTest command.
  378. *
  379. * @dev TPM device
  380. * @full_test Asking to perform all tests or only the untested ones
  381. *
  382. * @return code of the operation
  383. */
  384. u32 tpm2_self_test(struct udevice *dev, enum tpm2_yes_no full_test);
  385. /**
  386. * Issue a TPM2_Clear command.
  387. *
  388. * @dev TPM device
  389. * @handle Handle
  390. * @pw Password
  391. * @pw_sz Length of the password
  392. *
  393. * @return code of the operation
  394. */
  395. u32 tpm2_clear(struct udevice *dev, u32 handle, const char *pw,
  396. const ssize_t pw_sz);
  397. /**
  398. * Issue a TPM_NV_DefineSpace command
  399. *
  400. * This allows a space to be defined with given attributes and policy
  401. *
  402. * @dev TPM device
  403. * @space_index index of the area
  404. * @space_size size of area in bytes
  405. * @nv_attributes TPM_NV_ATTRIBUTES of the area
  406. * @nv_policy policy to use
  407. * @nv_policy_size size of the policy
  408. * @return return code of the operation
  409. */
  410. u32 tpm2_nv_define_space(struct udevice *dev, u32 space_index,
  411. size_t space_size, u32 nv_attributes,
  412. const u8 *nv_policy, size_t nv_policy_size);
  413. /**
  414. * Issue a TPM2_PCR_Extend command.
  415. *
  416. * @dev TPM device
  417. * @index Index of the PCR
  418. * @algorithm Algorithm used, defined in 'enum tpm2_algorithms'
  419. * @digest Value representing the event to be recorded
  420. * @digest_len len of the hash
  421. *
  422. * @return code of the operation
  423. */
  424. u32 tpm2_pcr_extend(struct udevice *dev, u32 index, u32 algorithm,
  425. const u8 *digest, u32 digest_len);
  426. /**
  427. * Read data from the secure storage
  428. *
  429. * @dev TPM device
  430. * @index Index of data to read
  431. * @data Place to put data
  432. * @count Number of bytes of data
  433. * @return code of the operation
  434. */
  435. u32 tpm2_nv_read_value(struct udevice *dev, u32 index, void *data, u32 count);
  436. /**
  437. * Write data to the secure storage
  438. *
  439. * @dev TPM device
  440. * @index Index of data to write
  441. * @data Data to write
  442. * @count Number of bytes of data
  443. * @return code of the operation
  444. */
  445. u32 tpm2_nv_write_value(struct udevice *dev, u32 index, const void *data,
  446. u32 count);
  447. /**
  448. * Issue a TPM2_PCR_Read command.
  449. *
  450. * @dev TPM device
  451. * @idx Index of the PCR
  452. * @idx_min_sz Minimum size in bytes of the pcrSelect array
  453. * @data Output buffer for contents of the named PCR
  454. * @updates Optional out parameter: number of updates for this PCR
  455. *
  456. * @return code of the operation
  457. */
  458. u32 tpm2_pcr_read(struct udevice *dev, u32 idx, unsigned int idx_min_sz,
  459. void *data, unsigned int *updates);
  460. /**
  461. * Issue a TPM2_GetCapability command. This implementation is limited
  462. * to query property index that is 4-byte wide.
  463. *
  464. * @dev TPM device
  465. * @capability Partition of capabilities
  466. * @property Further definition of capability, limited to be 4 bytes wide
  467. * @buf Output buffer for capability information
  468. * @prop_count Size of output buffer
  469. *
  470. * @return code of the operation
  471. */
  472. u32 tpm2_get_capability(struct udevice *dev, u32 capability, u32 property,
  473. void *buf, size_t prop_count);
  474. /**
  475. * Issue a TPM2_DictionaryAttackLockReset command.
  476. *
  477. * @dev TPM device
  478. * @pw Password
  479. * @pw_sz Length of the password
  480. *
  481. * @return code of the operation
  482. */
  483. u32 tpm2_dam_reset(struct udevice *dev, const char *pw, const ssize_t pw_sz);
  484. /**
  485. * Issue a TPM2_DictionaryAttackParameters command.
  486. *
  487. * @dev TPM device
  488. * @pw Password
  489. * @pw_sz Length of the password
  490. * @max_tries Count of authorizations before lockout
  491. * @recovery_time Time before decrementation of the failure count
  492. * @lockout_recovery Time to wait after a lockout
  493. *
  494. * @return code of the operation
  495. */
  496. u32 tpm2_dam_parameters(struct udevice *dev, const char *pw,
  497. const ssize_t pw_sz, unsigned int max_tries,
  498. unsigned int recovery_time,
  499. unsigned int lockout_recovery);
  500. /**
  501. * Issue a TPM2_HierarchyChangeAuth command.
  502. *
  503. * @dev TPM device
  504. * @handle Handle
  505. * @newpw New password
  506. * @newpw_sz Length of the new password
  507. * @oldpw Old password
  508. * @oldpw_sz Length of the old password
  509. *
  510. * @return code of the operation
  511. */
  512. int tpm2_change_auth(struct udevice *dev, u32 handle, const char *newpw,
  513. const ssize_t newpw_sz, const char *oldpw,
  514. const ssize_t oldpw_sz);
  515. /**
  516. * Issue a TPM_PCR_SetAuthPolicy command.
  517. *
  518. * @dev TPM device
  519. * @pw Platform password
  520. * @pw_sz Length of the password
  521. * @index Index of the PCR
  522. * @digest New key to access the PCR
  523. *
  524. * @return code of the operation
  525. */
  526. u32 tpm2_pcr_setauthpolicy(struct udevice *dev, const char *pw,
  527. const ssize_t pw_sz, u32 index, const char *key);
  528. /**
  529. * Issue a TPM_PCR_SetAuthValue command.
  530. *
  531. * @dev TPM device
  532. * @pw Platform password
  533. * @pw_sz Length of the password
  534. * @index Index of the PCR
  535. * @digest New key to access the PCR
  536. * @key_sz Length of the new key
  537. *
  538. * @return code of the operation
  539. */
  540. u32 tpm2_pcr_setauthvalue(struct udevice *dev, const char *pw,
  541. const ssize_t pw_sz, u32 index, const char *key,
  542. const ssize_t key_sz);
  543. /**
  544. * Issue a TPM2_GetRandom command.
  545. *
  546. * @dev TPM device
  547. * @param data output buffer for the random bytes
  548. * @param count size of output buffer
  549. *
  550. * @return return code of the operation
  551. */
  552. u32 tpm2_get_random(struct udevice *dev, void *data, u32 count);
  553. /**
  554. * Lock data in the TPM
  555. *
  556. * Once locked the data cannot be written until after a reboot
  557. *
  558. * @dev TPM device
  559. * @index Index of data to lock
  560. * @return code of the operation
  561. */
  562. u32 tpm2_write_lock(struct udevice *dev, u32 index);
  563. /**
  564. * Disable access to any platform data
  565. *
  566. * This can be called to close off access to the firmware data in the data,
  567. * before calling the kernel.
  568. *
  569. * @dev TPM device
  570. * @return code of the operation
  571. */
  572. u32 tpm2_disable_platform_hierarchy(struct udevice *dev);
  573. #endif /* __TPM_V2_H */