phy-mipi-dphy.h 6.2 KB

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  1. /* SPDX-License-Identifier: GPL-2.0 */
  2. /*
  3. * Copyright (C) 2018 Cadence Design Systems Inc.
  4. */
  5. #ifndef __PHY_MIPI_DPHY_H_
  6. #define __PHY_MIPI_DPHY_H_
  7. /**
  8. * struct phy_configure_opts_mipi_dphy - MIPI D-PHY configuration set
  9. *
  10. * This structure is used to represent the configuration state of a
  11. * MIPI D-PHY phy.
  12. */
  13. struct phy_configure_opts_mipi_dphy {
  14. /**
  15. * @clk_miss:
  16. *
  17. * Timeout, in picoseconds, for receiver to detect absence of
  18. * Clock transitions and disable the Clock Lane HS-RX.
  19. *
  20. * Maximum value: 60000 ps
  21. */
  22. unsigned int clk_miss;
  23. /**
  24. * @clk_post:
  25. *
  26. * Time, in picoseconds, that the transmitter continues to
  27. * send HS clock after the last associated Data Lane has
  28. * transitioned to LP Mode. Interval is defined as the period
  29. * from the end of @hs_trail to the beginning of @clk_trail.
  30. *
  31. * Minimum value: 60000 ps + 52 * @hs_clk_rate period in ps
  32. */
  33. unsigned int clk_post;
  34. /**
  35. * @clk_pre:
  36. *
  37. * Time, in UI, that the HS clock shall be driven by
  38. * the transmitter prior to any associated Data Lane beginning
  39. * the transition from LP to HS mode.
  40. *
  41. * Minimum value: 8 UI
  42. */
  43. unsigned int clk_pre;
  44. /**
  45. * @clk_prepare:
  46. *
  47. * Time, in picoseconds, that the transmitter drives the Clock
  48. * Lane LP-00 Line state immediately before the HS-0 Line
  49. * state starting the HS transmission.
  50. *
  51. * Minimum value: 38000 ps
  52. * Maximum value: 95000 ps
  53. */
  54. unsigned int clk_prepare;
  55. /**
  56. * @clk_settle:
  57. *
  58. * Time interval, in picoseconds, during which the HS receiver
  59. * should ignore any Clock Lane HS transitions, starting from
  60. * the beginning of @clk_prepare.
  61. *
  62. * Minimum value: 95000 ps
  63. * Maximum value: 300000 ps
  64. */
  65. unsigned int clk_settle;
  66. /**
  67. * @clk_term_en:
  68. *
  69. * Time, in picoseconds, for the Clock Lane receiver to enable
  70. * the HS line termination.
  71. *
  72. * Maximum value: 38000 ps
  73. */
  74. unsigned int clk_term_en;
  75. /**
  76. * @clk_trail:
  77. *
  78. * Time, in picoseconds, that the transmitter drives the HS-0
  79. * state after the last payload clock bit of a HS transmission
  80. * burst.
  81. *
  82. * Minimum value: 60000 ps
  83. */
  84. unsigned int clk_trail;
  85. /**
  86. * @clk_zero:
  87. *
  88. * Time, in picoseconds, that the transmitter drives the HS-0
  89. * state prior to starting the Clock.
  90. */
  91. unsigned int clk_zero;
  92. /**
  93. * @d_term_en:
  94. *
  95. * Time, in picoseconds, for the Data Lane receiver to enable
  96. * the HS line termination.
  97. *
  98. * Maximum value: 35000 ps + 4 * @hs_clk_rate period in ps
  99. */
  100. unsigned int d_term_en;
  101. /**
  102. * @eot:
  103. *
  104. * Transmitted time interval, in picoseconds, from the start
  105. * of @hs_trail or @clk_trail, to the start of the LP- 11
  106. * state following a HS burst.
  107. *
  108. * Maximum value: 105000 ps + 12 * @hs_clk_rate period in ps
  109. */
  110. unsigned int eot;
  111. /**
  112. * @hs_exit:
  113. *
  114. * Time, in picoseconds, that the transmitter drives LP-11
  115. * following a HS burst.
  116. *
  117. * Minimum value: 100000 ps
  118. */
  119. unsigned int hs_exit;
  120. /**
  121. * @hs_prepare:
  122. *
  123. * Time, in picoseconds, that the transmitter drives the Data
  124. * Lane LP-00 Line state immediately before the HS-0 Line
  125. * state starting the HS transmission.
  126. *
  127. * Minimum value: 40000 ps + 4 * @hs_clk_rate period in ps
  128. * Maximum value: 85000 ps + 6 * @hs_clk_rate period in ps
  129. */
  130. unsigned int hs_prepare;
  131. /**
  132. * @hs_settle:
  133. *
  134. * Time interval, in picoseconds, during which the HS receiver
  135. * shall ignore any Data Lane HS transitions, starting from
  136. * the beginning of @hs_prepare.
  137. *
  138. * Minimum value: 85000 ps + 6 * @hs_clk_rate period in ps
  139. * Maximum value: 145000 ps + 10 * @hs_clk_rate period in ps
  140. */
  141. unsigned int hs_settle;
  142. /**
  143. * @hs_skip:
  144. *
  145. * Time interval, in picoseconds, during which the HS-RX
  146. * should ignore any transitions on the Data Lane, following a
  147. * HS burst. The end point of the interval is defined as the
  148. * beginning of the LP-11 state following the HS burst.
  149. *
  150. * Minimum value: 40000 ps
  151. * Maximum value: 55000 ps + 4 * @hs_clk_rate period in ps
  152. */
  153. unsigned int hs_skip;
  154. /**
  155. * @hs_trail:
  156. *
  157. * Time, in picoseconds, that the transmitter drives the
  158. * flipped differential state after last payload data bit of a
  159. * HS transmission burst
  160. *
  161. * Minimum value: max(8 * @hs_clk_rate period in ps,
  162. * 60000 ps + 4 * @hs_clk_rate period in ps)
  163. */
  164. unsigned int hs_trail;
  165. /**
  166. * @hs_zero:
  167. *
  168. * Time, in picoseconds, that the transmitter drives the HS-0
  169. * state prior to transmitting the Sync sequence.
  170. */
  171. unsigned int hs_zero;
  172. /**
  173. * @init:
  174. *
  175. * Time, in microseconds for the initialization period to
  176. * complete.
  177. *
  178. * Minimum value: 100 us
  179. */
  180. unsigned int init;
  181. /**
  182. * @lpx:
  183. *
  184. * Transmitted length, in picoseconds, of any Low-Power state
  185. * period.
  186. *
  187. * Minimum value: 50000 ps
  188. */
  189. unsigned int lpx;
  190. /**
  191. * @ta_get:
  192. *
  193. * Time, in picoseconds, that the new transmitter drives the
  194. * Bridge state (LP-00) after accepting control during a Link
  195. * Turnaround.
  196. *
  197. * Value: 5 * @lpx
  198. */
  199. unsigned int ta_get;
  200. /**
  201. * @ta_go:
  202. *
  203. * Time, in picoseconds, that the transmitter drives the
  204. * Bridge state (LP-00) before releasing control during a Link
  205. * Turnaround.
  206. *
  207. * Value: 4 * @lpx
  208. */
  209. unsigned int ta_go;
  210. /**
  211. * @ta_sure:
  212. *
  213. * Time, in picoseconds, that the new transmitter waits after
  214. * the LP-10 state before transmitting the Bridge state
  215. * (LP-00) during a Link Turnaround.
  216. *
  217. * Minimum value: @lpx
  218. * Maximum value: 2 * @lpx
  219. */
  220. unsigned int ta_sure;
  221. /**
  222. * @wakeup:
  223. *
  224. * Time, in microseconds, that a transmitter drives a Mark-1
  225. * state prior to a Stop state in order to initiate an exit
  226. * from ULPS.
  227. *
  228. * Minimum value: 1000 us
  229. */
  230. unsigned int wakeup;
  231. /**
  232. * @hs_clk_rate:
  233. *
  234. * Clock rate, in Hertz, of the high-speed clock.
  235. */
  236. unsigned long hs_clk_rate;
  237. /**
  238. * @lp_clk_rate:
  239. *
  240. * Clock rate, in Hertz, of the low-power clock.
  241. */
  242. unsigned long lp_clk_rate;
  243. /**
  244. * @lanes:
  245. *
  246. * Number of active, consecutive, data lanes, starting from
  247. * lane 0, used for the transmissions.
  248. */
  249. unsigned char lanes;
  250. };
  251. int phy_mipi_dphy_get_default_config(unsigned long pixel_clock,
  252. unsigned int bpp,
  253. unsigned int lanes,
  254. struct phy_configure_opts_mipi_dphy *cfg);
  255. int phy_mipi_dphy_config_validate(struct phy_configure_opts_mipi_dphy *cfg);
  256. #endif /* __PHY_MIPI_DPHY_H_ */